Semiconductor memory device - Patent Review 5544121

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor memory devices and, specifically, to a clock synchronized type semiconductor memory device which operates in synchronization with externally applied clock signals. More specifically, the present invention relates to a structure of a semiconductor memory device containing a cache, in which a dynamic random access memory (DRAM) having a large storage capacity serving as a main memory, and a static random access memory (SRAM) having small storage capacity serving as a cache memory are integrated on the same semiconductor chip.

2. Description of the Background Art

Historical Review on Memory Environment in a Conventional Data Processing System

(i) Usage of standard DRAM as a main memory

Operation speed of recent 16-bit or 32-bit microprocessing unit (MPU) has been so much increased as to have operation clock frequency as high as 25 MHz or higher. In a data processing system, a standard DRAM (Dynamic Random Access Memory) is often used as a main memory having large storage capacity, since cost per bit is low. Although access time in the standard DRAM has been reduced, the speed of operation of the MPU has been increased much faster than that of the standard DRAM. Consequently, in a data processing system using the standard DRAM as a main memory, increase of wait state is inevitable. The gap in speed of operation between MPU and the standard DRAM is inevitable because the standard DRAM has the following characteristics.

(1) A row address and a column address are time divisionally multiplexed and applied to the same address pin terminals. The row address is taken in the device at a falling edge of a row address strobe signal/RAS. The column address is taken in the device at a falling edge of a column address strobe signal/CAS. The row address strobe signal/RAS defines start of a memory cycle and activates row selecting circuitry. The column address strobe signal/CAS activates column selecting circuitry. Since a prescribed time period called "RAS-CAS delay time (tRCD)" is necessary from the time the signal/RAS is set to an active state to the time the signal/CAS is set to the active state, there is a limit in reducing the access time, namely, there is a limit derived from address multiplexing.

(2) When the row address strobe signal/RAS is once raised to set the DRAM to a standby state, the row address strobe signal/RAS cannot fall to "L" again until a time period called a RAS precharge time (tRP) has lapsed. The RAS precharge time is necessary for surely precharging various signal lines in the DRAM to predetermined potentials. Due to the RAS precharge time TRP, the cycle time of DRAM cannot be reduced. In addition, when the cycle time of the DRAM is reduced, the number of charging/discharging of signal lines in the DRAM is increased, which increases current consumption.

(3) The higher speed of operation of the DRAM can be realized by circuit technique such as improvement of layout, increase of degree of integration of circuits, development in process technique and by applicational improvement such as improvement in the method of driving. However, the speed of operation of the MPU is increased at much faster rate than DRAM. The speed of operation of semiconductor memories is hierarchical. For example, there are high speed bipolar RAMs using bipolar transistors such as ECLRAMs (Emitter Coupled RAM) and Static RAM, and relatively low speed DRAMs using MOS transistors (insulated gate type field effect transistors). It is very difficult to expect the operation speed (cycle time) as fast as several tens ns (nano seconds) in a standard DRAM formed of MOS transistors.

There have been various applicational improvements to stop the gap between speed of operations of the MPU and the standard DRAM. Such improvements mainly comprise the following two approaches.

(1) Use of high speed mode of the DRAM and interleave method

(2) External provision of a high speed cache memory (SRAM).

The first approach (1) includes a method of using a high speed mode such as a static column mode or a page mode, and a method of combining the high speed mode and the interleave method. In the static column mode, one word line (one row) is selected, and thereafter only the column address is changed successively, to successively access memory cells of this row. In the page mode, one word line is selected, and then column addresses are successively taken by toggling the signal/CAS to successively access memory cells connected to the selected one word line. In either of these modes, memory cells can be accessed without toggling the signal/RAS, enabling higher speed accessing than the normal access using the signals/RAS and/CAS.

In the interleave method, a plurality of memories are provided in parallel to a data bus, and by alternately or successively accessing the plurality of memories, the access time is reduced in effect. The use of high speed mode of the DRAM and combination of the high speed mode and the interleave method have been known as a method of using the standard DRAM as a high speed DRAM in a simple and relatively effective manner.

The second approach (2) has been widely used in a main frame art. A high speed cache memory is expensive. However, in the field of personal computers in which high performance as well as low cost are desired, this approach is employed in some parts of the field with a sacrifice of cost.