Error-tolerant byte synchronization recovery scheme

Claims

I claim:

1. A system for detecting a selected error-tolerant synchronization field bit sequence encoded in a sequence of data bits on a data storage means, the system including:

(1) data register means, coupled to the data storage means and having a length of L bits, for serially accepting the sequence of data bits from the data storage means;

(2) synchronization pattern register means, having a length of L bits, for storing the selected error-tolerant synchronization field bit sequence;

(3) comparison means, coupled to the data register means and the synchronization pattern register means, for comparing the contents of the synchronization pattern register means with the contents of the data register means; and

(4) synchronization detection means, coupled to the comparison means and responsive thereto, for locating the error-tolerant synchronization field bit sequence encoded in the sequence of data bits, wherein the synchronization detection means provides an indication of synchronization when an output of the comparison means indicates that no more than b consecutive bits of the synchronization pattern register means do not match corresponding bits of the data register means, but a remainder of the L bits of the synchronization pattern register means do match corresponding bits of the data register means, the remainder of the L bits including all of the L bits except the b consecutive bits, and wherein b is an integer value greater than one.

2. A system for detecting a selected error-tolerant synchronization field bit sequence encoded on a data storage unit, the system including:

(1) a data storage unit;

(2) reading means, coupled to the data storage unit, for reading data bits stored on the data storage unit, the data bits including at least one field consisting of a selected error-tolerant synchronization field bit sequence of length L;

(3) data register means, coupled to the reading means, having a length of L bits, for serially accepting a sequence of data bits from the reading means;

(4) synchronization pattern register means, having a length of L bits, for storing the selected error-tolerant synchronization field bit sequence;

(5) comparison means, coupled to the data register means and the synchronization pattern register means, for comparing the contents of the synchronization pattern register means with the contents of the data register means; and

(6) synchronization detection means, coupled to the comparison means and responsive thereto, for locating the selected error-tolerant synchronization field bit sequence in the sequence of data bits provided by the reading means, wherein the synchronization detection means provides an indication of synchronization when an output of the comparison means indicates that no more than b consecutive bits of the synchronization pattern register means do not match corresponding bits of the data register means, but a remainder of the L bits of the synchronization pattern register means do match corresponding bits of the data register means, the remainder of the L bits including all of the L bits except the b consecutive bits, and wherein b is an integer value greater than one.

3. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein the synchronization detection means includes a plurality of NOR gates.

4. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein the comparison means includes a modulo-two algebraic summing circuit.

5. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein L is equal to 16 bits.

6. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claim 5, wherein b is less than 7 bits.

7. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein the selected error-tolerant byte synchronization field bit sequence is determined with respect to at least one expected bit pattern in a field bit sequence preceding the error-tolerant synchronization field bit sequence.

8. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein L is equal to 8 bits, b is equal to 2 bits, and the selected error-tolerant synchronization field bit sequence is hexadecimal B1.

9. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein L is equal to 10 bits, b is equal to 3 bits, and the selected error-tolerant synchronization field bit sequence is a hexadecimal 1B8, 1BC, 1BE, 1E2, 2D3 or 2D7.

10. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein L is equal to 12 bits, b is equal to 4 bits, and the selected error-tolerant synchronization field bit sequence is hexadecimal DC1.

11. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein L is equal to 14 bits, b is equal to 5 bits, and the selected error-tolerant synchronization field bit sequence is a hexadecimal 3581 or 3781.

12. A system for detecting a selected error-tolerant synchronization field bit sequence as set forth in claims 1 or 2, wherein L is equal to 16 bits, b is equal to 6 bits, and the selected error-tolerant synchronization field bit sequence is a hexadecimal 61C8, 61D4, 61D8, 61DC, 61E2, 61E8, 61EC, 61F2, 61F4, 61F8, 61FC, 61FE, 65C8, 65D4, 65D8, 65DC, 65E2, 65E8, 65EC, 65F2, 65F4, 65F8, 65FC, 65FE, 69C8, 69D4, 69D8, 69DC, 69E2, 69E8, 69EC, 69F4, 69F8, 69FC, 69FE, 6DC8, 6DD8, 6DDC, 6DE8, 6DEC, 6DF8, 6DFC, 6DFE, AB01, AB05, AF01, B701, B70D, BB01, BB05, BF01, D701, DB01, or DF01.

13. A system for detecting a selected error-tolerant synchronization field bit sequence encoded on a data storage unit, the system including:

(1) a data storage unit;

(2) reading means, coupled to the data storage unit, for reading data bits stored on the data storage unit, the data bits including at least one field consisting of a selected error-tolerant synchronization field bit sequence of length L;

(3) data register means, coupled to the reading means, having a length of L bits, for serially accepting a sequence of data bits from the reading means;

(4) synchronization pattern register means, having a length of L bits, for storing the selected error-tolerant synchronization field bit sequence;

(5) comparison means, coupled to the data register means and the synchronization pattern register means, for comparing the contents of the synchronization pattern register means with the contents of the data register means; and

(6) synchronization detection means, coupled to the comparison means and responsive thereto, for locating the selected error-tolerant synchronization field bit sequence in the sequence of data bits provided by the reading means, wherein the synchronization detection means provides an indication of synchronization when an output of the comparison means indicates that no more than b consecutive bits of the synchronization pattern register means do not match corresponding bits of the data register means, but a remainder of the L bits of the synchronization pattern register means do match corresponding bits of the data register means, the remainder of the L bits including all of the L bits except the b consecutive bits, and wherein L is equal to 7 bits, b is equal to 1 bit, and the selected error-tolerant synchronization field bit sequence is a hexadecimal 56 or 58.

14. An error-tolerant synchronization field bit sequence which is a hexadecimal 56, 58, B1, 1B8, 1BC, 1BE, 1E2, 2D3, 2D7, DC1, 3581, 3781, 61C8, 61D4, 61D8, 61DC, 61E2, 61E8, 61EC, 61F2, 61F4, 61F8, 61FC, 61FE, 65C8, 65D4, 65D8, 65DC, 65E2, 65E8, 65EC, 65F2, 65F4, 65F8, 65FC, 65FE, 69C8, 69D4, 69D8, 69DC, 69E2, 69E8, 69EC, 69F4, 69F8, 69FC, 69FE, 6DC8, 6DD8, 6DDC, 6DES, 6DEC, 6DF8, 6DFC, 6DFE, AB01, AB05, AF01, B701, B70D, BB01, BB05, BF01, D701, DB01, or DF01, in a system for detecting the synchronization field bit sequence, the system including a data storage unit having at least one track for storing data each track including at least one sector, each sector including at least one synchronization field for storing the synchronization field bit sequence, wherein the synchronization field bit sequence allows the system to correctly detect the error-tolerant synchronization field bit sequence encoded as a sequence of data bits on the data storage unit which are corrupted by an error burst having a length of as many as b bits by comparing the contents of the synchronization field to the sequence of data bits and by disregarding up to b bits of the error-tolerant synchronization field bit sequence, and wherein b is an integer value greater than one.

15. A method of determining in a computer selected error-tolerant synchronization field bit sequences for inclusion in a sequence of data bits on a data storage unit, comprising the steps of:

(1) selecting a bit pattern P.sub.o, expected to precede the selected error-tolerant synchronization field bit sequence in said sequence of data bits on a data storage device;

(2) generating a comparison result by comparing each of a generated test byte synchronization sequence N.sub.i of length L with a generated possible error data sequence D.sub.ijk that includes P.sub.o ;

(3) testing the comparison result through synchronization detection logic, and if the comparison result indicates that more than b bits of the generated test byte synchronization sequence N.sub.i differ b from corresponding bits of generated possible error data sequence, where b is an integer value greater than one, then:

(a) discarding the sequence N.sub.i ; otherwise,

(b) repeating steps (2) and (3) for a next sequence D.sub.ijk ; and

(4) if an N.sub.i sequence is discarded in step (3), then repeating steps (2) and (3) for a next sequence N.sub.i, and otherwise saving N.sub.i as an error-tolerant byte synchronization sequence.

16. The method of claim 15, further including the step of repeating steps (2)-(4) for a next selected bit pattern P.sub.o, wherein N.sub.i is selected from the error-tolerant field bit synchronization sequences.

17. The method of claim 15, wherein each generated possible error data sequence comprises a possible error pattern E.sub.j of length b, located at position K of N.sub.i.

18. A data storage unit having at least one track for storing data, each track comprising at least one sector, each sector including at least one synchronization field containing an error-tolerant synchronization field bit sequence, wherein the error tolerant synchronization field bit sequence allows a system for detecting the error-tolerant synchronization field bit sequence to correctly detect the error-tolerant synchronization field bit sequence encoded as a sequence of data bits on the data storage unit which are corrupted by an error burst having a length of as many as b bits by comparing the contents of the synchronization field to the sequence of data bits and by disregarding up to b bits of the error-tolerant synchronization field bit sequence, wherein b is an integer value greater than one, and

wherein the error-tolerant synchronization field bit sequence is a hexadecimal 56, 58, B1, 1B8, 1BC, 1BE, 1E2, 2D3, 2D7, DC1, 3581, 3781, 61C8, 61D4, 61D8, 61DC, 61E2, 61E8, 61EC, 61F2, 61F4, 61F8, 61FC, 61FE, 65C8, 65D4, 65D8, 65DC, 65E2, 65E8, 65EC, 65F2, 65F4, 65F8, 65FC, 65FE, 69C8, 69D4, 69D8, 69DC, 69E2, 69E8, 69EC, 69F4, 69F8, 69FC, 69FE, 6DC8, 6DD8, 6DDC, 6DES, 6DEC, 6DF8, 6DFC, 6DFE, AB01, AB05, AF01, B701, B70D, BB01, BB05, BF01, D701, DB01, or DF01.

19. A computer system having selected error-tolerant field bit sequences, comprising:

(1) a data storage unit having at least one track for storing data, each track comprising at least one sector, each sector including at least one synchronization field containing an error-tolerant synchronization field bit sequence; and

(2) means for determining the error-tolerant synchronization field bit sequence according to the following functions:

(a) selecting a bit pattern P.sub.o, expected to precede the selected error-tolerant synchronization field bit sequence in said sequence of data bits on a data storage device,

(b) generating a comparison result by comparing each of a generated test byte synchronization sequence N.sub.i of length L with a generated possible error data sequence D.sub.ijk that includes P.sub.o,

(c) testing the comparison result through synchronization detection logic, and if the comparison result indicates that more than b bits of the generated test byte synchronization sequence N.sub.i differ b from corresponding bits of generated possible error data sequence, where b is an integer value greater than one then;

(i) discarding the sequence N.sub.i, otherwise,

(ii) repeating (b) and (c) for a next sequence D.sub.ijk, and

(d) if an N.sub.i sequence is discarded in (c), then repeating (b) and (c) for a next sequence N.sub.i, and otherwise saving N.sub.i as an error-tolerant byte synchronization sequence.

20. A data storage unit having at least one track for storing data, each track comprising at least one sector, each sector including:

(1) at least one phase-lock oscillator field; and

(2) at least one synchronization field containing an error-tolerant synchronization field bit sequence,

wherein the error-tolerant synchronization field bit sequence allows a system to correctly detect the error-tolerant synchronization field bit sequence encoded as a sequence of data bits on the data storage unit which are corrupted by an error burst having a length of as many as b bits by comparing the contents of the synchronization field to the sequence of data bits and by disregarding up to b bits of the error-tolerant synchronization field bit sequence,

wherein b is an integer value greater than one, and

wherein the error-tolerant synchronization field bit sequence is a hexadecimal 56, 58, B1, 1B8, 1BC, 1BE, 1E2, 2D3, 2D7, DC1, 3581, 3781, 61C8, 61D4, 61D8, 61DC, 61E2, 61E8, 61EC, 61F2, 61F4, 61F8, 61FC, 61FE, 65C8, 65D4, 65D8, 65DC, 65E2, 65E8, 65EC, 65F2, 65F4, 65F8, 65FC, 65FE, 69C8, 69D4, 69D8, 69DC, 69E2, 69E8, 69EC, 69F4, 69F8, 69FC, 69FE, 6DC8, 6DD8, 6DDC, 6DES, 6DEC, 6DF8, 6DFC, 6DFE, AB01, AB05, AF01, B701, B70D, BB01, BB05, BF01, D701, DB01, or DF01.

21. A computer system having selected error-tolerant field bit sequences, comprising:

(1) a data storage unit having at least one track for storing data, each track comprising at least one sector, each sector including:

(a) at least one phase-lock oscillator field, and

(b) at least one synchronization field containing an error-tolerant synchronization field bit sequence; and

(2) means for determining the error-tolerant field bit sequence according to the following functions:

(a) selecting a bit pattern P.sub.o, expected to precede the selected error-tolerant synchronization field bit sequence in said sequence of data bits on a data storage device,

(b) generating a comparison result by comparing each of a generated test byte synchronization sequence N.sub.i of length L with a generated possible error data sequence D.sub.ijk, that includes P.sub.o,

(c) testing the comparison result through synchronization detection logic, and if the comparison result indicates that more than b bits of the generated test byte synchronization sequence N.sub.i, differ b from corresponding bits of generated possible error data sequence, where b is an integer value greater than one, then:

(i) discarding the sequence N.sub.i, otherwise;

(ii) repeating (b) and (c) for a next sequence D.sub.ijk, and

(d) if an N.sub.i sequence is discarded in (c), then repeating (b) and (c) for a next sequence N.sub.i, and otherwise saving N.sub.i as an error-tolerant byte synchronization sequence.

22. A data storage unit having at least one track for storing data, each track comprising at least one sector, each sector including a header comprising:

(1) a first inter-sector gap field;

(2) a first phase-lock oscillator field;

(3) a first synchronization field;

(4) an identification field;

(5) a cyclic redundancy check field;

(6) a first padding field;

(7) a write splice field;

(8) a second phase-lock oscillator field;

(9) a second synchronization field;

(10) a data field;

(11) an error correction code field; and

(12) a second padding field,

wherein the first and second synchronization field contains an error-tolerant synchronization field bit sequence, and wherein the error-tolerant synchronization field bit sequence allows a system to correctly detect the error-tolerant synchronization field bit sequence encoded as a sequence of data bits stored on the data storage unit which are corrupted by an error burst having a length of as many as b bits by disregarding up to b bits of the error-tolerant synchronization field bit sequence, and wherein b is an integer value greater than one.

23. The data storage unit of claim 22, wherein the error-tolerant synchronization field bit sequence is a hexadecimal 56, 58, B1, 1B8, 1BC, 1BE, 1E2, 2D3, 2D7, DC1, 3581, 3781, 61C8, 61D4, 61D8, 61DC, 61E2, 61E8, 61EC, 61F2, 61F4, 61F8, 61FC, 61FE, 65C8, 65D4, 65D8, 65DC, 65E2, 65E8, 65EC, 65F2, 65F4, 65F8, 65FC, 65FE, 69C8, 69D4, 69D8, 69DC, 69E2, 69E8, 69EC, 69F4, 69F8, 69FC, 69FE, 6DC8, 6DD8, 6DDC, 6DE8, 6DEC, 6DF8, 6DFC, 6DFE, AB01, AB05, AF01, B701, B70D, BB01, BB05, BF01, D701, DB01, or DF01.

24. A computer system having selected error-tolerant field bit sequences, comprising:

(1) a data storage unit having at least one track for storing data, each track comprising at least one sector, each sector including a header comprising:

(a) a first inter-sector gap field,

(b) a first phase-lock oscillator field,

(c) a first synchronization field,

(d) an identification field,

(e) a cyclic redundancy check field,

(f) a first padding field,

(g) a write splice field,

(h) a second-phase lock oscillator field;

(i) second synchronization field,

(j) a data field,

(k) an error correction code field, and

(l) a second padding field, wherein the first and second synchronization field contains an error-tolerant synchronization field bit sequence and

(2) means for determining the error-tolerant field bit sequence according to the following functions:

(a) selecting a bit pattern P.sub.o, expected to precede the selected error-tolerant synchronization field bit sequence in said sequence of data bits on a data storage device,

(b) generating a comparison result by comparing each of a generated test byte synchronization sequence N.sub.i of length L with a generated possible error data sequence D.sub.ijk, that includes P.sub.o,

(c) testing the comparison result through synchronization detection logic, and if the comparison result indicates that more than b bits of the generated test byte synchronization sequence N.sub.i differ b from corresponding bits of generated possible error data sequence, where b is an integer value greater than one, then;

(i) discarding the sequence N.sub.i, otherwise,

(ii) repeating (b) and (c) for a next sequence D.sub.ijk, and

(d) if an N.sub.i sequence is discarded in (c), then repeating (b) and (c) for a next sequence N.sub.i, and otherwise saving N.sub.i as an error-tolerant byte synchronization sequence.

25. A system for detecting a selected error-tolerant synchronization field bit sequence encoded on a data storage unit, the system including:

(1) data register means, coupled to the data storage means and having a length of L bits, for serially accepting the sequence of data bits from the data storage means;

(2) synchronization pattern register means, having a length of L bits, for storing the selected error-tolerant synchronization field bit sequence;

(3) comparison means, coupled to the data register means and the synchronization pattern register means, for comparing the contents of the synchronization pattern register means with the contents of the data register means; and

(4) synchronization detection means, coupled to the comparison means and responsive thereto, for locating the error-tolerant synchronization field bit sequence in the encoded sequence of data bits, wherein the synchronization detection means provides an indication of synchronization when an output of the comparison means indicates that no more than b consecutive bits of the synchronization pattern register means do not match corresponding bits of the data register means, but a remainder of the L bits of the synchronization pattern register means do match corresponding bits of the data register means, the remainder of the L bits including all of the L bits except the b consecutive bits, and wherein L is equal to 7 bits, b is equal to 1 bit, and the selected error-tolerant synchronization field bit sequence is a hexadecimal 56 or 58.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to data storage techniques employed in conjunction with computing systems, and more specifically to error-tolerant techniques for recovering byte synchronization information from data storage media.

2. Description of the Prior Art

Byte synchronization recovery schemes are often employed in conjunction with data storage units. Many data storage units, such as magnetic disks, store data in concentric circles called tracks. These tracks are divided into blocks called sectors. A sector normally includes a data field, an identification (ID) field, a phase-lock oscillator (PLO) field, and a byte synchronization ("SYNC") field. A sector may further include a cyclic redundancy check (CRC) field, an error correction code (ECC) field, one or more padding (PAD) fields to fill out a sector, and one or more inter-sector gap fields.

Within a sector, synchronization of the data and ID fields is achieved by detecting a particular bit pattern in the synchronization (SYNC) field. The SYNC field enables a determination of the locations of the boundaries between adjacent bytes on the data storage unit. This process may be referred to as "byte synchronization." The SYNC field also enables a determination of the position of a particular byte with respect to the remaining data on the data storage unit. In the case of a magnetic disk, the SYNC field is typically placed immediately after each PLO field and right before the corresponding ID or data field at the time of formatting the disk.

One purpose of the bit pattern in the SYNC field is to provide proper synchronization for the beginning byte of the ID or data fields at the time of a data Read operation. The SYNC field is generally one byte in length, and the field contains a predetermined pattern of bits, referred to as the byte synchronization pattern. The search for the byte synchronization pattern is done over a certain period of time, which is called the "SYNC search window. If a particular byte SYNC pattern is not detected within that window, the information stored in the corresponding sector cannot be retrieved. If there is an error in the SYNC field, either a loss of data or a false detection of synchronization will result. In either case, access to the information stored in the corresponding sector will not be provided, and the data is effectively lost.

Errors in the SYNC field may be characterized as random bit errors. However, due to the fact that the information stored in the SYNC field is processed by a modulation decoder, a random bit error may be transformed into a data burst error affecting a plurality of data bits. The process of byte synchronization occurs after the data bits from the SYNC search window are passed through the modulation decoder. Therefore, data burst errors may prevent synchronization or may cause false synchronization to occur. Commonly-utilized modulation codes have been developed to minimize the length of such data burst errors. For example, the well-known run-length-limited (1,7) and (2,7) codes place inherent limits upon the error propagation properties of the modulation decoder by ensuring that a single-bit error cannot generate a data burst error more than six bits in length.

In the context of a data storage unit, data burst errors affecting the SYNC field are particularly troublesome. For example, the organization of a typical sector on a disk requires that the byte synchronization be recovered two times per sector. The SYNC search window normally begins near the middle of the PLO field. In case of an error in the SYNC field, presently-existing synchronization hardware will simply fail or falsely detect the synchronization. In other words, the existing scheme does not provide any fault tolerance, and thus is very vulnerable to bit errors. No conventional error correction code can be employed to recover from an error in the SYNC field, since any ECC requires bit/byte synchronization.

Hence, a fault-tolerant synchronization detection system is desirable to avoid the disastrous situation of data loss from errors in the SYNC fields, and to achieve high system reliability and performance. The purpose of fault-tolerant synchronization recovery schemes is to enable synchronization even if there is an error in the SYNC field. What is needed is a fault-tolerant synchronization detection scheme which will recover synchronization correctly from short burst errors in a SYNC field. Such a scheme may be employed in conjunction with improved synchronization bit patterns to improve error tolerance.

The present invention provides such a scheme, as well as a method for determining such improved synchronization bit patterns.

SUMMARY OF THE INVENTION

The invention provides an improved technique for detecting the synchronization bit pattern encoded in the SYNC fields on a data storage unit. The fault-tolerant SYNC detection scheme of the present invention provides proper byte synchronization even if the SYNC field is corrupted by a single burst error of as many as b bits. This scheme utilizes one or more specific bit sequences of length L within the SYNC field. These specific bit sequences are referred to as byte synchronization sequences. The minimum length for L is determined by the maximum length b of the error burst for which recovery is desired. The fault-tolerant SYNC detection logic is implemented to provide a SYNC FOUND signal (logical HIGH) if the inputs are all zero (no error), or if the ones in the input are limited to a span of no more than b consecutive bits and the remaining L-b bits are all zero. Otherwise, the logic provides a SYNC NOT FOUND signal (logical LOW).

A plurality of improved byte synchronization sequences are provided, which yield an improved error tolerance when employed in conjunction with the above scheme. Preferred byte synchronization sequences were developed with the assumption that one of the following patterns can appear in the PLO field: (1) all zeros, (2) all ones, (3) repetitive "1000" (binary), or (4) repetitive "001" (binary). This assumption holds true for commonly-available data storage systems. For a data error burst of a given length, the minimum length of the sequences and the number of such sequences may be specified.

If a different set of patterns in the PLO field is expected, then the corresponding byte synchronization sequences would not be the same. An entirely different set of sequences may be obtained with different parameters for a given pattern (or patterns) in the PLO field. These sequences may be determined by exhaustive computer search. A method for determining such improved byte synchronization sequences is also provided.

Further aspects of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. It should be understood, however, that the detailed description and the specific examples, while representing the preferred embodiment and several alternative embodiments of the invention, are given by way of illustration only.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatical representation of the organization of a typical sector on a magnetic data storage disk.

FIG. 2 is a block diagram illustrating a portion of a prior-art hardware configuration designed to implement a byte synchronization scheme.

FIG. 3 is a table setting forth the probability of an error burst of a specified length when the modulation decoder of FIG. 2 receives a single bit error.

FIG. 4 is a block diagram illustrating a portion of a prior-art hardware configuration for implementing byte synchronization.

FIG. 5 is a block diagram illustrating a hardware configuration for implementing byte synchronization according to the present invention.

FIG. 6 is a partial schematic and block diagram illustrating optimized logic for a preferred embodiment of the present invention.

FIG. 7 is a table setting forth the number and minimum length of error tolerant sequences for specified burst lengths, and the values of such sequences. FIG. 8 is a table that sets forth the number and minimum of error tolerance sequences for specified burst lengths and the number of error tolerant sequences.

Like reference numbers in the various drawings refer to like elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description is of the best presently contemplated modes of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense.

FIG. 1 is a diagrammatical representation of the organization of a typical sector 100 for a magnetic data storage disk. The sector 100 commences with a "header" comprising a first inter-sector gap (ISG) field 102, followed by a first phase-lock oscillator (PLO) field 104, a first synchronization (SYNC) field 106, an ID field 108, a cyclic redundancy check (CRC) field 110, and a first padding (PAD) field 112. The first PAD field 112 is followed by a Write splice field 114, a second PLO field 116, a second SYNC field 118, a Data field 120, an error correction code (ECC) field 122, and a second PAD field 124. A second ISG field 126 is a part of the next disk sector.

It is important to observe that the byte synchronization needs to be recovered two times per sector, at first SYNC field 106 and second SYNC field 118. The data storage disk input/output (I/O) transducer head searches for the bit pattern stored in the SYNC fields 106, 118, during an interval termed the SYNC search window 128, 129, in known fashion. The length of the SYNC search windows 128, 129 is usually programmable. Typically, for the first SYNC field 106, the first SYNC search window 128 may commence near the middle of the PLO field 104 and terminate near the middle of the ID field 108. For the second SYNC field 118, the second SYNC search window 129 may begin near the middle of PLO field 116 and terminate towards the beginning of the Data field 120.

FIG. 2 is a block diagram illustrating a prior-art hardware configuration 200 for byte synchronization. The raw channel bits 202 received from the magnetic disk I/O transducer and a peak detector are input to a modulation decoder 204. The raw channel bits 202 are generally decoded using a modulation decoding scheme such as the run-length-limited (RLL) (1,7) code or (2,7) code, which are both well-known in the prior art. An important characteristic of most modulation decoding schemes is that a single random bit error at the input to the modulation decoder 204 is transformed by the modulation decoder 204 into a string or burst of errors at the output o