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Claims  |
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What is claimed is:
1. An on-chip debug system for a programmable VLSI processor, said on-chip
debug system referred to as a debug port, said debug port comprising:
(a) a plurality of units, said units including (1) a debug bus unit, (2) a
debug command unit, (3) a debug instruction unit, (4) a debug
inject/extract unit, and (5) a program flow unit;
(b) a first internal bus referred to as the internal debug bus;
(c) a second internal bus referred to as the move controller bus;
(d) said debug bus unit being operatively coupled (i) to receive debug
information from at least one other of said plurality of units via the
internal debug bus and (ii) to send debug information to at least one
other of said plurality of units via the move controller bus, said debug
bus unit having
(1) means for sending signals to and receiving signals from an external
interface module at an external interface data exchange rate,
(2) means for receiving a service-request signal from at least one other of
said plurality of units and for arbitrating and acknowledging said
service-request signal,
(3) means for storing debug information received from at least one other of
said plurality of units, and
(4) means for synchronizing the external interface data exchange rate and
an internal debug port data exchange rate;
(e) said debug command unit operatively coupled (i) to receive a debug
command from at least one other of said plurality of units via the move
controller bus, said debug command unit having
(1) means for receiving a debug command from the VLSI processor,
(2) means for selecting and decoding a debug command,
(3) a status latch register for selectively latching one or more status
signals received from at least one of said plurality of units,
(4) means for sending said one or more selectively latched status signals
to at least one of said plurality of units,
(5) an enable latch register for selectively latching one or more enable
signals received from at least one of said plurality of units,
(6) means for sending said one or more selectively latched enable signals
to at least one other of said plurality of units,
(7) a timer,
(8) means for sending timer information to the VLSI processor,
(9) means for sending timer information to at least one other of said
plurality of units via the internal debug bus,
(10) means for sending debug information to at least one other of said
plurality of units via the internal debug bus,
(11) means for sending a service-request signal to the debug bus unit, and
(12) means for receiving a service-request acknowledgment signal from the
debug bus unit;
(f) said debug instruction unit being operatively coupled (i) to receive
debug information from at least one other of said plurality of units via
the move controller bus and (ii) to send debug information to at least one
other of said plurality of units via the internal debug bus, said debug
instruction unit having
(1) means for sending a VLSI instruction to a first register internal to
the VLSI processor,
(2) means for sending VLSI data associated with said VLSI instruction to a
second register internal to the VLSI processor,
(3) means for receiving data from one or more registers internal to said
VLSI processor,
(4) means for sending a service-request signal to the debug bus unit, and
(5) means for receiving a service-request acknowledgment signal from the
debug bus unit;
(g) said debug inject/extract unit being operatively coupled to (i) receive
debug information from at least one other of said plurality of units via
the move controller bus and (ii) send debug information to at least one
other of said plurality of units via the internal debug bus, said debug
inject/extract unit having
(1) means for sending data to a register internal to the VLSI processor,
(2) means for receiving data from a register internal to the VLSI
processor,
(3) means for sending a service-request signal to the debug bus unit, and
(4) means for receiving a service-request acknowledgment signal from the
debug bus unit; and
(h) said program flow unit configured to monitor a task being executed by
the VLSI processor, said task having a branch execution behavior, said
program flow unit being operatively coupled to send debug information to
at least one other of said plurality of units via the internal debug bus,
said program flow unit having
(1) means for monitoring said branch execution behavior,
(2) means for reporting said branch execution behavior to the debug bus
unit,
(3) means for sending a service-request signal to the debug bus unit, and
(4) means for receiving a service-request acknowledgment signal from the
debug bus unit.
2. An on-chip debug system, having a plurality of units, for a programmable
VLSI processor, said on-chip debug system referred to as a debug port,
comprising:
(a) a first internal bus referred to as the internal debug bus;
(b) a second internal bus referred to as the move controller bus;
(c) a debug bus unit for exchanging information between the debug port and
an external interface module, said debug bus unit operatively coupled (1)
to receive debug information from at least one of said plurality of units
via the internal debug bus and (2) to send debug information to at least
one of said plurality of units via the move controller bus;
(d) a debug command unit for decoding and executing a debug command, said
debug command unit operatively coupled (1) to receive a debug command from
at least one of said plurality of units via the move controller bus, (2)
to receive a debug command from the VLSI processor, (3) to selectively
send debug status and timer information to at least one of said plurality
of units via the internal debug bus, and (4) to selectively send a debug
port enable signal to at least one of said plurality of units;
(e) a debug instruction unit for sending a VLSI instruction to a first
register internal to the VLSI processor and for sending VLSI
instruction-data, associated with the VLSI instruction, to a second
register internal to the VLSI processor, and for receiving debug data from
one or more registers internal to the VLSI processor, said debug
instruction unit operatively coupled (1) to receive debug information from
at least one of said plurality of units via the move controller bus and
(2) to send debug information to at least one of said plurality of units
via the internal debug bus;
(f) a debug inject/extract unit for sending task-data to a task being
executed by the VLSI processor and for receiving task-data generated by
the task, said debug inject/extract unit operatively coupled (1) to
receive debug information from at least one of said plurality of units via
the move controller bus and (2) to send debug information to at least one
of said plurality of units via the internal debug bus; and
(g) a program flow unit for monitoring a task being executed by the VLSI
processor, said task having a branch execution behavior, said program flow
unit operatively coupled to send debug information to at least one of said
plurality of units via the internal debug bus.
3. The on-chip debug system for a programmable VLSI processor of claims 1
or 2, wherein said status signals encode information representative of one
or more of (1) state of a user flag, (2) availability of a temporary
memory within the debug bus unit, (3) state of a watchdog counter, (4)
filled status of register memory internal to the debug inject/extract
unit, (5) filled status of register memory internal to the debug
instruction unit, (6) filled status of register memory internal to the
debug command unit, and (7) operational mode of the VLSI processor.
4. The on-chip debug system for a programmable VLSI processor of claims 1
or 2, wherein said enable signals encode information to enable and disable
the operation of one or more of: a realtime counter and the debug flow
unit.
5. The on-chip debug bus unit for a VLSI processor of claims 1 or 2,
wherein said service-request signal is selected from the group consisting
of dbc16c.sr, dbc32c.sr, dbc32d.sr, dbg.sr, dbs.sr, rtcc.sr, rtcv.sr,
wdt.sr, dbd0.sr, dbd1.sr, dbdj.sr, diow.sr, djs0.sr, djs1.sr, djs2.sr,
djs3.sr, djr0.sr, djr1.sr, djr2.sr, djr3.sr, djow0.sr, djow1.sr, djow2.sr,
djow3.sr, df16.sr, df32.sr.
6. An on-chip debug system for a programmable VLSI processor, said on-chip
debug system referred to as a debug port, said debug port comprising:
(a) a plurality of units, said units including (1) a debug bus unit, (2) a
debug command unit, (3) a debug instruction unit, and (4) a debug
inject/extract unit;
(b) a first internal bus referred to as the internal debug bus;
(c) a second internal bus referred to as the move controller bus;
(d) said debug bus unit being operatively coupled (i) to receive debug
information from at least one other of said plurality of units via the
internal debug bus and (ii) to send debug information to at least one
other of said plurality of units via the move controller bus, said debug
bus unit having
(1) means for sending signals to and receiving signals from an external
interface module at an external interface data exchange rate,
(2) means for receiving a service-request signal from at least one other of
said plurality of units and for arbitrating and acknowledging said
service-request signal,
(3) means for storing debug information received from at least one other of
said plurality of units, and
(4) means for synchronizing the external interface data exchange rate and
an internal debug port data exchange rate;
(e) said debug command unit operatively coupled (i) to receive a debug
command from at least one other of said plurality of units via the move
controller bus, said debug command unit having
(1) means for receiving a debug command from the VLSI processor,
(2) means for selecting and decoding a debug command,
(3) a status latch register for selectively latching one or more status
signals received from at least one of said plurality of units,
(4) means for sending said one or more selectively latched status signals
to at least one of said plurality of units,
(5) an enable latch register for selectively latching one or more enable
signals received from at least one of said plurality of units,
(6) means for sending said one or more selectively latched enable signals
to at least one other of said plurality of units,
(7) a timer,
(8) means for sending timer information to the VLSI processor,
(9) means for sending timer information to at least one other of said
plurality of units via the internal debug bus,
(10) means for sending debug information to at least one other of said
plurality of units via the internal debug bus,
(11) means for sending a service-request signal to the debug bus unit, and
(12) means for receiving a service-request acknowledgment signal from the
debug bus unit;
(f) said debug instruction unit being operatively coupled (i) to receive
debug information from at least one other of said plurality of units via
the move controller bus and (ii) to send debug information to at least one
other of said plurality of units via the internal debug bus, said debug
instruction unit having
(1) means for sending a VLSI instruction to a first register internal to
the VLSI processor,
(2) means for sending VLSI data associated with said VLSI instruction to a
second register internal to the VLSI processor,
(3) means for receiving data from one or more registers internal to said
VLSI processor,
(4) means for sending a service-request signal to the debug bus unit, and
(5) means for receiving a service-request acknowledgment signal from the
debug bus unit; and
(g) said debug inject/extract unit being operatively coupled to (i) receive
debug information from at least one other of said plurality of units via
the move controller bus and (ii) send debug information to at least one
other of said plurality of units via the internal debug bus, said debug
inject/extract unit having
(1) means for sending data to a register internal to the VLSI processor,
(2) means for receiving data from a register internal to the VLSI
processor,
(3) means for sending a service-request signal to the debug bus unit, and
(4) means for receiving a service-request acknowledgment signal from the
debug bus unit.
7. An on-chip debug system, having a plurality of units, for a programmable
VLSI processor, said on-chip debug system referred to as a debug port,
comprising:
(a) a first internal bus referred to as the internal debug bus;
(b) a second internal bus referred to as the move controller bus;
(c) a debug bus unit for exchanging information between the debug port and
an external interface module, said debug bus unit operatively coupled (1)
to receive debug information from at least one of said plurality of units
via the internal debug bus and (2) to send debug information to at least
one of said plurality of units via the move controller bus;
(d) a debug command unit for decoding and executing a debug command, said
debug command unit operatively coupled (1) to receive a debug command from
at least one of said plurality of units via the move controller bus, (2)
to receive a debug command from the VLSI processor, (3) to selectively
send debug status and timer information to at least one of said plurality
of units via the internal debug bus, and (4) to selectively send a debug
port enable signal to at least one of said plurality of units;
(e) a debug instruction unit for sending a VLSI instruction to a first
register internal to the VLSI processor and for sending VLSI
instruction-data, associated with the VLSI instruction, to a second
register internal to the VLSI processor, and for receiving debug data from
one or more registers internal to the VLSI processor, said debug
instruction unit operatively coupled (1) to receive debug information from
at least one of said plurality of units via the move controller bus and
(2) to send debug information to at least one of said plurality of units
via the internal debug bus; and
(f) a debug inject/extract unit for sending task-data to a task being
executed by the VLSI processor and for receiving task-data generated by
the task, said debug inject/extract unit operatively coupled (1) to
receive debug information from at least one of said plurality of units via
the move controller bus and (2) to send debug information to at least one
of said plurality of units via the internal debug bus.
8. The on-chip debug system for a programmable VLSI processor of claims 6
or 7, wherein said status signals encode information representative of one
or more of (1) state of a user flag, (2) availability of a temporary
memory within the debug bus unit, (3) state of a watchdog counter, (4)
filled status of register memory internal to the debug inject/extract
unit, (5) filled status of register memory internal to the debug
instruction unit, (6) filled status of register memory internal to the
debug command unit, and (7) operational mode of the VLSI processor.
9. The on-chip debug system for a programmable VLSI processor of claims 6
or 7, wherein said enable signals encode information to enable and disable
the operation a real-time counter.
10. The on-chip debug bus unit for a VLSI processor of claims 6 or 7,
wherein said service-request signal is selected from the group consisting
of dbc16c.sr, dbc32c.sr, dbc32d.sr, dbg.sr, dbs.sr, rtcc.sr, rtcv.sr,
wdt.sr, dbd0.sr, dbd1.sr, dbdj.sr, diow.sr, djs0.sr, djs1.sr, djs2.sr,
djs3.sr, djr0.sr, djr1.sr, djr2.sr, djr3.sr, djow0.sr, djow1.sr, djow2.sr,
and djow3.sr.
11. An on-chip debug system for a programmable VLSI processor, said on-chip
debug system referred to as a debug port, said debug port comprising:
(a) a plurality of units, said units including (1) a debug bus unit, (2) a
debug command unit, and (3) a debug instruction unit;
(b) a first internal bus referred to as the internal debug bus;
(c) a second internal bus referred to as the move controller bus;
(d) said debug bus unit being operatively coupled (i) to receive debug
information from at least one other of said plurality of units via the
internal debug bus and (ii) to send debug information to at least one
other of said plurality of units via the move controller bus, said debug
bus unit having
(1) means for sending signals to and receiving signals from an external
interface module at an external interface data exchange rate,
(2) means for receiving a service-request signal from at least one other of
said plurality of units and for arbitrating and acknowledging said
service-request signal,
(3) means for storing debug information received from at least one other of
said plurality of units, and
(4) means for synchronizing the external interface data exchange rate and
an internal debug port data exchange rate;
(e) said debug command unit operatively coupled (i) to receive a debug
command from at least one other of said plurality of units via the move
controller bus, said debug command unit having
(1) means for receiving a debug command from the VLSI processor,
(2) means for selecting and decoding a debug command,
(3) a status latch register for selectively latching one or more status
signals received from at least one of said plurality of units,
(4) means for sending said one or more selectively latched status signals
to at least one of said plurality of units,
(5) an enable latch register for selectively latching one or more enable
signals received from at least one of said plurality of units,
(6) means for sending said one or more selectively latched enable signals
to at least one other of said plurality of units,
(7) a timer,
(8) means for sending timer information to the VLSI processor,
(9) means for sending timer information to at least one other of said
plurality of units via the internal debug bus,
(10) means for sending debug information to at least one other of said
plurality of units via the internal debug bus,
(11) means for sending a service-request signal to the debug bus unit, and
(12) means for receiving a service-request acknowledgment signal from the
debug bus unit; and
(f) said debug instruction unit being operatively coupled (i) to receive
debug information from at least one other of said plurality of units via
the move controller bus and (ii) to send debug information to at least one
other of said plurality of units via the internal debug bus, said debug
instruction unit having
(1) means for sending a VLSI instruction to a first register internal to
the VLSI processor,
(2) means for sending VLSI data associated with said VLSI instruction to a
second register internal to the VLSI processor,
(3) means for receiving data from one or more registers internal to said
VLSI processor,
(4) means for sending a service-request signal to the debug bus unit, and
(5) means for receiving a service-request acknowledgment signal from the
debug bus unit.
12. An on-chip debug system, having a plurality of units, for a
programmable VLSI processor, said on-chip debug system referred to as a
debug port, comprising:
(a) a first internal bus referred to as the internal debug bus;
(b) a second internal bus referred to as the move controller bus;
(c) a debug bus unit for exchanging information between the debug port and
an external interface module, said debug bus unit operatively coupled (1)
to receive debug information from at least one of said plurality of units
via the internal debug bus and (2) to send debug information to at least
one of said plurality of units via the move controller bus;
(d) a debug command unit for decoding and executing a debug command, said
debug command unit operatively coupled (1) to receive a debug command from
at least one of said plurality of units via the move controller bus, (2)
to receive a debug command from the VLSI processor, (3) to selectively
send debug status and timer information to at least one of said plurality
of units via the internal debug bus, and (4) to selectively send a debug
port enable signal to at least one of said plurality of units; and
(e) a debug instruction unit for sending a VLSI instruction to a first
register internal to the VLSI processor and for sending VLSI
instruction-data, associated with the VLSI instruction, to a second
register internal to the VLSI processor, and for receiving debug data from
one or more registers internal to the VLSI processor, said debug
instruction unit operatively coupled (1) to receive debug information from
at least one of said plurality of units via the move controller bus and
(2) to send debug information to at least one of said plurality of units
via the internal debug bus.
13. The on-chip debug system for a programmable VLSI processor of claims 11
or 12, wherein said status signals encode information representative of
one or more of (1) state of a user flag, (2) availability of a temporary
memory within the debug bus unit, (3) state of a watchdog counter, (4)
filled status of register memory internal to the debug inject/extract
unit, (5) filled status of register memory internal to the debug
instruction unit, (6) filled status of register memory internal to the
debug command unit, and (7) operational mode of the VLSI processor.
14. The on-chip debug system for a programmable VLSI processor of claims 11
or 12, wherein said enable signals encode information to enable and
disable the operation a real-time counter.
15. The on-chip debug bus unit for a VLSI processor of claims 11 or 12,
wherein said service-request signal is selected from the group consisting
of dbc16c.sr, dbc32c.sr, dbc32d.sr, dbg.sr, dbs.sr, rtcc.sr, rtcv.sr,
wdt.sr, dbd0.sr, dbd1.sr, dbdj.sr, and diow.sr.
16. An on-chip debug system for a programmable VLSI processor, said on-chip
debug system referred to as a debug port, said debug port comprising:
(a) a plurality of units, said units including (1) a debug bus unit, (2) a
debug command unit, and (3) a debug inject/extract unit;
(b) a first internal bus referred to as the internal debug bus;
(c) a second internal bus referred to as the move controller bus;
(d) said debug bus unit being operatively coupled (i) to receive debug
information from at least one other of said plurality of units via the
internal debug bus and (ii) to send debug information to at least one
other of said plurality of units via the move controller bus, said debug
bus unit having
(1) means for sending signals to and receiving signals from an external
interface module at an external interface data exchange rate,
(2) means for receiving a service-request signal from at least one other of
said plurality of units and for arbitrating and acknowledging said
service-request signal,
(3) means for storing debug information received from at least one other of
said plurality of units, and
(4) means for synchronizing the external interface data exchange rate and
an internal debug port data exchange rate;
(e) said debug command unit operatively coupled (i) to receive a debug
command from at least one other of said plurality of units via the move
controller bus, said debug command unit having
(1) means for receiving a debug command from the VLSI processor,
(2) means for selecting and decoding a debug command,
(3) a status latch register for selectively latching one or more status
signals received from at least one of said plurality of units,
(4) means for sending said one or more selectively latched status signals
to at least one of said plurality of units,
(5) an enable latch register for selectively latching one or more enable
signals received from at least one of said plurality of units,
(6) means for sending said one or more selectively latched enable signals
to at least one other of said plurality of units,
(7) a timer,
(8) means for sending timer information to the VLSI processor,
(9) means for sending timer information to at least one other of said
plurality of units via the internal debug bus,
(10) means for sending debug information to at least one other of said
plurality of units via the internal debug bus,
(11) means for sending a service-request signal to the debug bus unit, and
(12) means for receiving a service-request acknowledgment signal from the
debug bus unit; and
(f) said debug inject/extract unit being operatively coupled to (i) receive
debug information from at least one other of said plurality of units via
the move controller bus and (ii) send debug information to at least one
other of said plurality of units via the internal debug bus, said debug
inject/extract unit having
(1) means for sending data to a register internal to the VLSI processor,
(2) means for receiving data from a register internal to the VLSI
processor,
(3) means for sending a service-request signal to the debug bus unit, and
(4) means for receiving a service-request acknowledgment signal from the
debug bus unit.
17. An on-chip debug system, having a plurality of units, for a
programmable VLSI processor, said on-chip debug system referred to as a
debug port, comprising:
(a) a first internal bus referred to as the internal debug bus;
(b) a second internal bus referred to as the move controller bus;
(c) a debug bus unit for exchanging information between the debug port and
an external interface module, said debug bus unit operatively coupled (1)
to receive debug information from at least one of said plurality of units
via the internal debug bus and (2) to send debug information to at least
one of said plurality of units via the move controller bus;
(d) a debug command unit for decoding and executing a debug command, said
debug command unit operatively coupled (1) to receive a debug command from
at least one of said plurality of units via the move controller bus, (2)
to receive a debug command from the VLSI processor, (3) to selectively
send debug status and timer information to at least one of said plurality
of units via the internal debug bus, and (4) to selectively send a debug
port enable signal to at least one of said plurality of units; and
(e) a debug inject/extract unit for sending task-data to a task being
executed by the VLSI processor and for receiving task-data generated by
the task, said debug inject/extract unit operatively coupled (1) to
receive debug information from at least one of said plurality of units via
the move controller bus and (2) to send debug information to at least one
of said plurality of units via the internal debug bus.
18. The on-chip debug system for a programmable VLSI processor of claims 16
or 17, wherein said status signals encode information representative of
one or more of (1) state of a user flag, (2) availability of a temporary
memory within the debug bus unit, (3) state of a watchdog counter, (4)
filled status of register memory internal to the debug inject/extract
unit, (5) filled status of register memory internal to the debug command
unit, and (6) operational mode of the VLSI processor.
19. The on-chip debug system for a programmable VLSI processor of claims 16
or 17, wherein said enable signals encode information to enable and
disable the operation of a real-time counter.
20. The on-chip debug bus unit for a VLSI processor of claims 16 or 17,
wherein said service-request signal is selected from the group consisting
of dbc16c.sr, dbc32c.sr, dbc32d.sr, dbg.sr, dbs.sr, rtcc.sr, rtcv.sr,
wdt.sr, djs0.sr, djs1.sr, djs2.sr, djs3.sr, djr0.sr, djr1.sr, djr2.sr,
djr3.sr, djow0.sr, djow1.st, djow2.sr, and djow3.sr.
21. A debug development system for a programmable VLSI processor,
comprising:
(a) an on-chip debug port in accordance with claim 1 operatively coupled to
the VLSI processor, said debug port incorporating an interface circuit;
(b) an external host processor; and
(b) an interface circuit between the host processor and the debug port's
interface circuit operatively configured to permit communication.
22. An on-chip debug bus unit for a VLSI processor comprising:
(a) means for sending signals to and receiving signals from an external
interface module at an external interface data exchange rate;
(b) means for receiving a service-request signal from an on-chip source
external to the debug bus unit;
(c) means for generating a service-request acknowledgment signal for an
on-chip destination external to the debug bus unit;
(d) means for generating a message header signal;
(e) means for (1) receiving and storing said message header signal and (2)
storing a debug information signal received from an on-chip source
external to the debug bus unit; and
(f) means for synchronizing the external interface data exchange rate and
an internal debug bus unit data exchange rate.
23. The on-chip debug bus unit for a VLSI processor of claim 22, wherein
the means for storing said message header signal and debug information
signal consists of an output FIFO memory configured to store a plurality
of 16-bit units of information.
24. The on-chip debug bus unit for a VLSI processor of claim 22, wherein
the external interface module sends and receives signals encoding 8-bits
of information at a time.
25. The on-chip debug bus unit for a VLSI processor of claim 24, wherein
the debug bus unit reformats consecutively received 8-bit signals from
said external interface module to a 16-bit signal for an on-chip
destination external to the debug bus unit.
26. The on-chip debug bus unit for a VLSI processor of claim 22, wherein
said means for receiving a service-request signal is configured to receive
a service-request signal selected from the group consisting of dbc16c.sr,
dbc32c.sr, dbc32d.sr, dbg.sr, dbs.sr, rtcc.sr, rtcv.sr, wdt.sr, dbd0.sr,
dbd1.sr, dbdj.sr, diow.sr, djs0.sr, djs1.sr, djs2.sr, djs3.sr, djr0.sr,
djr1.sr, djr2.sr, djr3.sr, djow0.sr, djow1.sr, djow2.sr, djow3.sr,
df16.sr, df32.sr.
27. An on-chip debug bus unit for a VLSI processor comprising:
(a) a service request arbitrator circuit for (1) receiving a service
request signal, (2) generating a service request acknowledgment signal,
and (3) generating a message header command signal;
(b) a header generator circuit, operatively coupled to (1) receive a
message header command signal from the service request arbitrator circuit
and (2) generate a message header signal;
(c) an output FIFO memory operatively coupled to (1) receive and store a
message header signal from the header generator circuit and (2) receive
and store a message information signal from an on-chip source that is
external to the debug bus unit;
(d) an output FIFO memory write control circuit operatively coupled to (1)
receive a write command signal from the service request arbitrator
circuit, (2) generate a write command signal to the output FIFO memory,
and (3) generate a write address signal to the output FIFO memory;
(e) a protocol logic circuit operatively coupled to (1) receive read and
write command signals from an off-chip source, (2) generate request and
acknowledgment command signals to the off-chip source, and (3) generate a
read command signal;
(f) an output FIFO memory read control circuit operatively coupled to (1)
receive a read command signal from the protocol logic circuit, (2)
generate a read command signal to the output FIFO memory, and (3) generate
a read address signal to the output FIFO memory;
(g) a MUX circuit operatively coupled to (1) receive a signal from the
output memory FIFO representative of a previously stored message composed
of a message header signal portion and a message information signal
portion, (2) receive a byte select signal from the output FIFO memory read
control circuit, (3) generate an output message signal for transmission to
the off-chip source; and
(h) a move controller circuit operatively coupled to (1) receive a signal
from the off-chip source at an external data exchange rate and (2)
transmit a reformatted signal to an on-chip source that is external to the
debug bus unit at an internal debug bus unit data exchange rate.
28. The on-chip debug bus unit for a VLSI processor of claim 27, wherein
said output FIFO memory is configured to store a plurality of 16 -bit
units of information.
29. The on-chip debug bus unit for a VLSI processor of claim 28, wherein
said output message signal consists of a most-significant byte signal
followed by a least-significant byte signal.
30. The on-chip debug bus unit for a VLSI processor of claim 27, wherein
the signal received from the off-chip source is a byte-wide signal.
31. The on-chip debug bus unit for a VLSI processor of claim 27, wherein
said service request arbitrator circuit is configured to receive a
service-request signal selected from the group consisting of dbc16c.sr,
dbc32c.sr, dbc32d.sr, dbg.sr, dbs.sr, rtcc.sr, rtcv.sr, wdt.sr, dbd0.sr,
dbd1.sr, dbdj.sr, diow.sr, djs0.sr, djs1.sr, djs2.sr, djs3.sr, djr0.sr,
djr1.sr, djr2.sr, djr3.sr, djow0.sr, djow1.sr, djow2.sr, djow3.sr,
df16.sr, df32.sr.
32. An on-chip debug command unit for a VLSI processor comprising:
(a) a means for receiving a command message signal from an on-chip source
external to the debug command unit;
(b) a means for receiving a command message signal from the VLSI processor;
(c) means for generating a selected command signal;
(d) means for decoding the selected command signal;
(e) a means for generating an output message signal for an on-chip source
external to the debug command unit;
(f) means for receiving a service-request signal from an on-chip source
external to the debug command unit;
(g) means for generating a service-request acknowledgment signal for an
on-chip destination external to the debug command unit;
(h) means for receiving and storing a status information signal;
(i) means for receiving and storing a device enable signal; and
(j) means for generating a time-signal encoding a real-time clock value.
33. The on-chip debug command unit for a VLSI processor of claim 32,
wherein the means for receiving and storing a status information signal is
configured to receive and store status signals selected from the group
consisting of: state of a user flag, availability of a temporary memory
within a debug bus unit, state of a watchdog counter, filled status of
register memory internal to the debug command unit, filled status of
register memory internal to a debug inject/extract unit, filled status of
register memory internal to a debug instruction unit, and operational mode
of the VLSI processor.
34. The on-chip debug command unit for a VLSI processor of claim 32,
wherein the means for receiving and storing a device enable signal is
configured to receive and store enable signals selected from the group
consisting of RTCE, RSPBE, RSPB, SMME, PROME, DROME, DFE, NEXCE, QEXCE,
SMME, and DAE.
35. An on-chip debug command unit for a programmable VLSI processor, said
VLSI processor having a data bus, comprising:
(a) a DBE register for receiving a command message signal from an on-chip
source external to the debug command unit;
(b) a DBC register for (1) receiving a message signal from the VLSI
processor's data bus, (2) receiving a load signal, and (3) generating an
output message signal for transmission to an on-chip source external to
the debug command unit;
(c) a service request logic circuit for (1) generating a service request
signal, (2) receiving a service request acknowledgment signal, and (3)
generating a DBC register load signal;
(d) a MUX control logic circuit for (1) receiving a command message signal
from the DBE register, (2) receiving a message signal from the DBC
register, and (3) generating a selected command signal;
(e) a command decode logic circuit for (1) receiving the selected command
signal, (2) generating a decoded command signal, and (3) generating an
enable signal;
(f) a DBS register for (1) receiving a status information signal, and (2)
latching said status information signal for subsequent retrieval by
on-chip source external to the debug command unit;
(g) a DBG register for (1) receiving a device enable signal, and (2)
latching said device enable signal for subsequent retrieval by on-chip
sources external to the debug command unit; and
(h) a real-time counter circuit, having a real-time clock, for (1)
receiving a real-time request signal, and (2) generating a time-signal
encoding the real-time clock's value.
36. The on-chip debug command unit for a VLSI processor of claim 35,
wherein said DBC register is a 32 -bit double-buffered register.
37. The on-chip debug command unit for a VLSI processor of claim 35,
wherein said DBG register is configured to receive and latch enable
signals selected from the group consisting of RTCE, RSPBE, RSPB, SMME,
PROME, DROME, DFE, NEXCE, QEXCE, SMME, and DAE.
38. The on-chip debug command unit for a VLSI processor of claim 35,
wherein said real-time clock is a 32-bit counter.
39. An on-chip debug instruction unit for a programmable VLSI processor,
said VLSI processor having (i) a data bus, (ii) an address bus, and (iii)
an instruction bus, comprising:
(a) means for receiving a data signal from an on-chip source external to
the debug instruction unit;
(b) means for sending a VLSI instruction signal to a first VLSI processor
register via the VLSI processor instruction bus;
(c) means for sending a VLSI data signal associated with the VLSI
instruction signal to a second VLSI processor register via the VLSI
processor data bus;
(d) means for sending a VLSI address signal associated with the VLSI
instruction signal to a third VLSI processor register via the VLSI
processor address bus;
(e) means for sending a service-request signal to an on-chip source
external to the debug instruction unit; and
(f) means for receiving a service-request acknowledgment signal from an
on-chip source external to the debug instruction unit.
40. The on-chip debug instruction unit for a VLSI processor of claim 35,
wherein said means for sending a service-request signal is configured to
generate a service-request signal selected from the group consisting of
dbd0.sr, dbd1.sr, dbdj.sr, and diow.sr.
41. An on-chip debug instruction unit for a programmable VLSI processor,
said VLSI processor having (i) a data bus, (ii) an address bus, and (iii)
an instruction bus, comprising:
(a) a DBB buffer for receiving a data signal from an on-chip source
external to the debug instruction unit;
(b) a DBI register for (1) receiving a data signal from the DBB buffer and
(2) generating an instruction signal for transmission to the VLSI
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