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BACKGROUND OF THE INVENTION
The present invention relates to technique of transmitting a signal between
elements such as a CPU and a memory device or memory IC (for example,
between digital circuits each composed of CMOS elements or functional
blocks of CMOS elements), and, more particularly to techniques of quickly
transmitting a signal through one bus in which one main transmission line
has plural elements connected thereto.
As a technique of quickly transmitting a signal between digital circuits
each composed of a semiconductor integrated circuit, there has been
proposed a technique of a low-amplitude interface for propagating a signal
having a signal amplitude as low as about 1 volt.
As a representative example of such a low-amplitude interface, a GTL
(Gunning Transceiver Logic) interface or a CTT (Center Tapped Termination)
interface has been heretofore proposed. These low-amplitude interfaces are
discussed in detail in pp 269 to 290 of Nikkei Electronics, Nov. 27, 1993.
FIG. 1 shows a prior art arrangement of such a low-amplitude interface in
which one main transmission line has plural branched lines.
A numeral 100 denotes a transmission line terminated by termination power
supplies 60 and 61 and termination resistors 50 and 51. The transmission
line 100 is connected to a driving circuit block 1 and receiving circuit
blocks 2, 3 and 4.
The transmission line 100 has an impedance of 50.OMEGA.. Each of branched
lines 11 to 14 has an impedance of 50.OMEGA.. Each of the terminating
resistors 50 and 51 has an impedance of 50.OMEGA.. Each voltage of the
terminating power supplies 60 and 61 is 0.5 volt. The sending or driving
circuit 21 has an on resistance of 10.OMEGA..
When the driving circuit 21 is at a logical "High" output, the circuit 21
operates to connect the transmission line 11 to a 1-volt power supply (not
shown). When the driving circuit 21 is at a logical "Low" output, the
circuit 21 operates to connect the transmission line 11 to the ground,
that is, a 0-volt power supply (not shown). Numerals 32 to 34 denote
receiving circuits included in a receiving circuit block, respectively.
These receiving circuits compare received signals with the reference
voltage V.sub.ref to determine if the received signal is a Low or High
level. In this arrangement, V.sub.ref is set at 0.5 V.
Next, a description will be given as to how a signal is transmitted to each
point in FIG. 1 on this bus when the driving circuit 21 is switched from
the Low output to the High output. At first, a potential of the
transmission bus 100 is derived when the driving circuit 21 is at the Low
output. The voltage at the point A on the transmission line at this time
corresponds to a voltage given by dividing the terminating power source of
0.5 volt by the terminating resistances 50 and 51 and the on resistance of
the sending circuit 21. That is, the voltage is derived by:
0.5 V.times.10.OMEGA./(10.OMEGA.+50.OMEGA./2)=0.14 (V)
Next, the potential will be derived of the transmission line which occurs
when the output of the sending circuit 21 is switched from the Low output
to the High output so that a signal is transmitted to a point A of FIG. 1
as follows. Immediately after the output of the sending circuit 21 is
switched, the power supply voltage is divided by the on-resistance of the
sending circuit and the impedance 50.OMEGA. of the transmission line 11.
Hence, the potential boost at the point A is derived by:
1 V.times.50.OMEGA./(50.OMEGA.+10.OMEGA.)=0.83 (V)
The addition of the initial voltage 0.14 V and the voltage boost, that is,
0.97 V corresponds to the potential at the point A.
The potential occurring when the waveform of the amplitude of 0.83 V
reaches the branch point B is derived as follows. If the transmission line
100 is viewed from the transmission line 11, since the transmission line
100 is divided into two, left and right parts, the virtual impedance of
the transmission line 100 if viewed from the transmission line 11 becomes
a half of an impedance 50.OMEGA. of the transmission line 100, that is,
25.OMEGA.. On the other hand, since the impedance of the transmission line
11 is 50.OMEGA., the mismatch of the impedance results in bringing about
the reflection of a signal at the point B.
The reflective coefficient is derived as follows.
(50.OMEGA.-25.OMEGA.)/(50.OMEGA.+25.OMEGA.)=0.33
This means that a one-third part of the signal amplitude of 0.83 V
transmitted to the point A, that is, a signal of the amplitude 0.28 V is
reflected and returned to the sending circuit side. The signal of the left
amplitude 0.55 V is transmitted to the transmission line 100 as a first
transmitted wave. Hence, the potential of the transmitted signal
corresponds to an addition of 0.55 V and the initial potential, that is,
0.69 V.
When the signal having the amplitude of 0.28 V returned to the sending
circuit reaches the sending circuit, the signal is mirror-reflected and
reaches the point B again. A two-third part of the signal passes through
the transmission line 100, while the remaining one-third part of the
signal is returned to the transmission line 11. According to such an
action, the signal travels to and fro on the transmission line 11 again
and again. Each time the signal waveform reaches the point B, the
two-third part of each waveform is output to the transmission line 100. By
this operation, the amplitude of 0.83 V originally at the point A is
dividedly transmitted to the transmission line 100 bit by bit.
The signal of 0.69 V which passed through the point B and transmitted to
the transmission line 100 reaches the point C. At this point, two
transmission lines are each made to have an impedance of 50.OMEGA. before
the passage of the signal. Hence, the mismatch of the forward synthesized
impedance 25.OMEGA. to the impedance of 50.OMEGA. of the transmission line
on which the signal has passed results in bringing about the reflection of
the signal.
The reflective coefficient is as follows:
(50.OMEGA.-25.OMEGA.)/(50.OMEGA.+25.OMEGA.)=0.33
The potential of the waveform passed through the point C corresponds to a
potential derived by multiplying the signal amplitude of 0.55 V at the
point B by a transmittance 2/3 (=1-1/3) and adding the initial potential
to the multiplied value. That is,
0.55 V.times.2/3+0.14 V=0.50 (V)
A similar reflection takes place at the point E or the point G. The
potential at the point E is 0.38 V and the potential at the point G is
0.30 V.
These results are shown in FIGS. 2A to 2C. FIG. 2A shows signals which come
to and go out of the point C, that is, a signal of the point B coming to
the point C and signals of the point D and the point E going out of the
point C. For explaining them clearly, the signal at the point A is shown
as well. Likewise, FIG. 2B shows signals which come to and go out of the
point E. FIG. 2C shows signals which come to and go out of the point G. In
FIGS. 2A to 2C, a numeral 201 denotes a signal waveform at the point A in
FIG. 1. A numeral 202 denotes a waveform at the point B. A numeral 203
denotes a waveform at the point C. A numeral 204 denotes a waveform at the
point D. A numeral 205 denotes a waveform at the point E. A numeral 206
denotes a waveform at the point F. A numeral 207 denotes a waveform at the
point G. A numeral 208 denotes a waveform at the point H. When the signal
drops, the same thing takes place. The signal waveforms at the drop of the
signal are as shown in FIGS. 3A to 3C. In FIG. 3, numerals 201 to 208
denote signal waveforms at the point A to the point H shown in FIG. 1,
respectively.
From the situation described above, it is understood that the use of the
conventional signal transmitting circuit makes it impossible to allow the
first signal at the point A indicating a High level from the driving
circuit 21 to exceed the reference voltage Vref (0.5 V in the above
condition) at all of the receiving circuit blocks for establishing that
the signal is at the High level. In other words, due to the large degree
of reflection at the various points B, C, E and G, the original High level
voltage at the point A for the first signal is attenuated to very low
levels of voltage that will not exceed the reference voltage V.sub.ref at
the receivers. Therefore, even though the sending circuit 21 is indicating
a High level, the receivers 32, 33 and 34 will not be able to recognize
this for the first signal. Eventually, after repeated signals, the level
of voltage at points B, C and D will increase to levels much closer to the
level at point A, but, until this occurs, the receivers will not be able
to recognize the High level.
The signal entering each branched line at the branch point C, E or G, like
the transmission line 11, is reflected over and over inside of the
branched line. When the reflected waveform returns to the branch point,
the two-third part of the signal goes to the transmission line 100. This
brings about a waveform distortion on the transmission line 100.
As mentioned above, in the foregoing prior art, the reflections take place
at each branch point. The potential drops resulting from the reflections
are overlapped with each other. Hence, the rise of the signal potential is
delayed in a remote place of the driving circuit. This results in
disadvantageously increasing the delay time, and thereby prevents quickly
transmitting the signal.
Further, the signal entered into the receiving circuit block is reflected
in the receiving circuit part and then goes into the transmission line
100. This also results in disadvantageously distorting the signal
waveform, thereby lowering the reliability of the signal transmission.
To speed up the signal transmission and make the signal amplitude on the
line 100 smaller, the above prior art is arranged so that the supply
voltage is 1 V. In the circuit discussed in the aforementioned paper, to
achieve an amplitude of 1 V at the normally used power supply of 3.3 V,
the driving circuit is arranged to give a special value of 100.OMEGA. to
its on-resistance for realizing a small amplitude.
The special value given to the on resistance as mentioned in the paper,
however, makes the widely available transistors having an on resistance of
about 10 W useless. In other words, specially designed transistors are
required.
Further, such a higher on resistance given to the sending circuit 21 leads
to increasing the power consumption of the driving circuit, thereby
disadvantageously increasing the overall power consumption.
As another known prior art arrangement relevant to the present invention,
U.S. Pat. No. 4,922,449 to Donaldson et al may be referred to. This U.S.
Patent discloses a technique of providing a resistor between a circuit
block and an inter-block signal transmission line in a circuit line
structure having plural circuit blocks containing a driving circuit and a
receiving circuit and the inter-block signal transmission line for
propagating a signal between the circuit blocks. The object of providing
the resistor therebetween is for reducing passage current appearing at the
time of signal collision by the source switching operation, that is,
reducing the amplitude of the signal on the inter-block signal
transmission bus. The resistance is set as 20 W to 40 W. This resistance
may bring about a signal reflection at a branch point between the
transmission line inside of the circuit block and the inter-block
transmission line. The signal reflection may disadvantageously inhibit the
realization of fast signal transmission. That is, this technique does not
define any resistance based on a relation of an impedance between the
inter-block signal transmission line and the signal transmission line
inside of the block.
Moreover, another prior art arrangement which provides a resistor between
an inter-block signal transmission line and a signal transmission line
inside of the circuit block is disclosed in JP-B-54-5929. In this prior
art arrangement, a resistor is provided only between the circuit block on
the side of the receiving circuit and the inter-block signal transmission
line, but no resistor is provided between the circuit block provided with
a sending circuit and the inter-block signal transmission bus. Like U.S.
Pat. No. 4,922,449, a signal reflection takes place when the signal
outputted from the sending circuit is transmitted onto the inter-block
signal transmission bus. As in the previously described arrangement, this
signal reflection may disadvantageously inhibit realization of fast signal
transmission.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a signal transmitting
device, a circuit block, and an integrated circuit which are arranged to
overcome the foregoing disadvantages, suppress the drop of a signal
potential on a transmission line having branched lines, prevent repetitive
reflections in each branched line, and keep an amplitude of a signal small
on the line, for quickly transmitting a signal.
To achieve the object in a preferred mode, a signal transmitting device
comprises a first circuit block including a driving circuit for driving a
signal and an intra-block transmission line for transmitting a signal from
the driving circuit to the outside of the circuit block, a second circuit
block including a receiving circuit for receiving a signal and an
intra-block transmission line for transmitting a signal to be inputted to
the receiving circuit, and an inter-block transmission line for
transmitting the signal between the circuit blocks, wherein the
inter-block transmission line is terminated by one or two elements each
having a resistance equal to or close to a characteristic impedance value
of the inter-block transmission line. In addition, the resistance of each
of resistors 80 to 83 is provided with a resistance equal to or close to a
value obtained by subtracting a half of the impedance of the inter-block
transmission line from the impedance of the intra-block transmission line.
In a circuit device having plural blocks each having both of a driving
circuit and a receiving circuit, likewise, the inter-block transmission
line is terminated by one or two elements each having a resistance equal
to or close to a characteristic impedance of the inter-block transmission
line. Each intra-block transmission line is provided to have a resistance
equal to or close to a value obtained by subtracting a half of the
characteristic impedance of the inter-block transmission line from the
impedance of the intra-block transmission line.
In the case where a package with a long lead frame such as quad flat
package (QFP) or a pin grid array (PGA) is used in an integrated circuit
having a driving or a receiving circuit integrated thereon termination is
made to the inter-block transmission line, a resistor is provided for
impedance matching between the inter-block transmission line and the
intra-block transmission line, and the impedance of the lead frame and the
impedance of the intra-block transmission line are matched.
In accordance with the present invention, by inserting a resistor having a
resistance close to a value derived by reducing a half of an impedance of
the line from the impedance of the branched line, it is possible to
prevent repetition of reflections inside of the branched line and
attenuate the amplitude of the transmission line by dividing the inserted
resistance and the terminating resistance, thereby enabling to quickly
transmit the signal.
In the case where a large number of branch points exist on the inter-block
transfer line, the capacitance because of the existence of the resistors,
the inter-block transmission line is not able to see the branched line
directly (i.e., the total of the transmission line load capacitance and
the capacitance of the driving and receiving circuits). This is effective
in suppressing the line impedance from being lowered. Further, the
waveform distortion due to live-insertion can be suppressed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a conventional unidirectional transmission
line;
FIGS. 2A to 2C are charts showing signal waveforms (leading waveforms)
appearing in the case of using the conventional transmission line;
FIGS. 3A to 3C are charts showing signal waveforms (tailing waveforms)
appearing in the case of using the conventional transmission line;
FIG. 4 is a block diagram showing an embodiment 1 of the present invention;
FIG. 5 is a circuit diagram showing an example of a driving circuit;
FIG. 6 is a circuit diagram showing an example of a differential receiving
circuit;
FIGS. 7A to 7C are graphs showing signal waveforms (leading waveforms) in
the embodiment 1 of the present invention;
FIGS. 8A to 8C are graphs showing signal waveforms (tailing waveforms) in
the embodiment 1 of the present invention;
FIG. 9 is a graph showing a waveform distortion occurring when
live-insertion is executed in the case of using the conventional
transmission line;
FIG. 10 is a graph showing a waveform distortion due to live-insertion in
the case of using the circuit according to the embodiment 1 of the present
invention;
FIG. 11 is a block diagram showing an embodiment 2 of the present
invention;
FIGS. 12A to 12B are graphs showing waveforms occurring when the sending
circuit is switched by using the conventional transmission line;
FIGS. 13A to 13B are diagrams showing waveforms of switching operation by
driving circuit of the embodiment 2;
FIG. 14 is a block diagram showing an embodiment 3 of the invention;
FIG. 15 is a diagram showing a modification of the embodiment 3;
FIGS. 16A to 16C are graphs showing signal waveforms (leading waveforms)
occurring in the case of the circuit according to the embodiment 3 of the
present invention;
FIGS. 17A to 17C are graphs showing signal waveforms (tailing waveforms)
occurring in the case of the circuit according to the embodiment 3 of the
present invention;
FIGS. 18A to 18C are graphs showing signal waveforms (leading waveforms)
occurring in the case of changing an impedance on a transmission line in
the circuit according to the embodiment 1 of the present invention;
FIGS. 19A to 19C are graphs showing signal waveforms (tailing waveforms)
occurring in the case of changing an impedance on a transmission line in
the circuit according to the embodiment 1 of the present invention;
FIG. 20 is a circuit diagram showing an arrangement of the embodiment 3 of
the present invention in which a capacitor is used in place of the
resistor;
FIG. 21 is a circuit showing another arrangement of the embodiment 3 of the
present invention in which a capacitor is used in place of the resistor;
FIGS. 22A to 22C are graphs showing signal waveforms (leading waveforms)
occurring in the case of using the arrangement shown in FIG. 20;
FIGS. 23A to 23C are graphs showing signal waveforms (tailing waveforms)
occurring in the case of using the arrangement shown in FIG. 20;
FIG. 24 is a graph showing a signal waveform occurring in a circuit
arrangement shown in FIG. 4;
FIG. 25 is a graph showing a signal waveform occurring in a case that
resistors 80 to 83 have smaller values in the circuit arrangement shown in
FIG. 4;
FIG. 26 is a graph showing a signal waveform occurring in a case that the
resistors 80 to 83 have larger values in the circuit arrangement shown in
FIG. 4;
FIG. 27 is a block diagram showing an embodiment 4 of the present
invention;
FIG. 28 is a sectional view showing a QFP package;
FIG. 29 is a sectional view showing a PGA package; and
FIG. 30 is a diagram showing an example of a device on which the QFP
package is mounted.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiment of the present invention will be described in detail with
reference to the accompanying drawings.
FIG. 4 shows in fundamental block diagram, a first embodiment of a
unidirectional transmission line to which the present invention is
applied.
In FIG. 4, a numeral 1 denotes a driving circuit block (unit) having a
driving circuit 21. Numerals 2 to 4 denote receiving circuit blocks
provided with receiving circuits 32 to 34, respectively. The circuit
blocks include resistors 80 to 83 and transmission lines 11 to 14,
respectively. A transmission line 100 is connected to the circuit blocks 1
to 4, and both ends of the transmission bus 100 are terminated by the
resistors 50 and 51, each having a resistance equal to or close to a
characteristic impedance value of the transmission line 100.
In FIG. 4, the transmission line 100 has an impedance of 50.OMEGA.. The
branched lines 11 to 14 each have an impedance of 100.OMEGA.. Each of the
termination resistors 50 and 51 has a resistance of 50.OMEGA.. Terminating
power supplies 60 and 61 operate to supply a voltage of 1.5 V. The driving
circuit 21 has an on resistance of 10.OMEGA..
The driving circuit 21 operates to connect a transmission line to a 3
V-power supply (such as 62 in FIG. 5) when the driving circuit 21 holds
the output high or connect the transmission line to a ground potential
(such as 63, in FIG. 5) when the driving circuit 21 holds the output low.
In FIG. 4, numerals 32 to 34 denote receiving circuits.
The resistors 80 to 83 are each defined to have a resistance of 75.OMEGA..
The method of defining the resistance will be described later.
It is noted that in this embodiment, the transmission line 100 is
terminated at both of the ends. However, it may be terminated at one end
by just one resistor, if preferred. Further, this embodiment provides
three receiving circuit blocks each having a receiving circuit. However,
the present invention is applicable to a signal transmission device
including at least one block having the receiving circuit.
FIG. 5 shows an example of the sending or driving circuit 21 used in the
arrangement of FIG. 4. This driving circuit 21 is a push-pull driving
circuit composed of a pull-up transistor 70 and a pull-down transistor 71.
The pull-up transistor 70 shown in FIG. 5 is made of an N-channel MOS
field-effect transistor (NMOS). The material of the transistor 70 is not
limited to NMOS. For example, a P-channel MOS field-effect transistor
(PMOS) may be used for making the transistor 70.
A low-amplitude driving circuit provided with the push-pull driving circuit
is discussed in detail in the Nikkei Electronics paper referred to
previously as a prior art arrangement. In this paper, however, the driving
circuit uses a transistor with as high an on-resistor as about 100.OMEGA..
On the contrary, the present invention uses a transistor with an on
resistance of about 10.OMEGA. which is now widely available. The present
invention may use the conventional driving circuit, because the sum of
on-resistance of the resistors 80 to 83 added in this embodiment and the
transistor on resistance of about 10.OMEGA. is close to the on resistance
of 100.OMEGA. of the prior art device so that the amplitude on the
transmission bus 100 is approximately the same magnitude as that of the
prior art.
For example, assume that the impedance and the termination resistor of the
transmission line 100 is 50.OMEGA., the impedance of the branched line is
100.OMEGA., the terminating power supply feeds a voltage of 1.5 V, and the
power supply for the driving circuit feeds a voltage of 3 V. With these
assumptions, the signal amplitude becomes 0.6 V on the transmission line
used in the foregoing paper indicating the use of the transistor with the
on resistance of 100.OMEGA., and the amplitude is substantially equal to
the amplitude of 0.68 V of the transmission line 100 shown in FIG. 4.
By lowering the on-resistance of the driving circuit 21 from 100.OMEGA. to
10.OMEGA., it is possible to reduce the power consumed in the driving
circuit. For example, in the above condition, the prior art device
arranged to use an on resistance of 100.OMEGA. consumes a power of 14.4
mW, while the present invention may greatly reduce the power consumption
down to 1.9 mW. Moreover, the present embodiment may use a driving circuit
having an on-resistance of 10.OMEGA. or more, concretely, about 50.OMEGA..
Such a driving circuit may offer the same effect as above.
Next, an example of the receiving circuits of FIG. 4 is shown in FIG. 6.
This receiving circuit is a differential receiving circuit for determining
if an input signal is logically High or Low based on whether or not an
input voltage is higher or lower than the reference voltage V.sub.ref. The
reference voltage used herein may be produced inside of an integrated
circuit. However, if noises appearing inside of the integrated circuit or
noises which have entered from the outside cause the power supply to
fluctuate, the reference voltage may fluctuate accordingly. Hence, it is
better to feed the reference voltage from the outside. Further, it is
preferable that the receiving circuit is an NMOS type differential
receiving circuit for receiving an input signal through the effect of the
NMOS. If this type receiving circuit is used as the reference voltage, the
voltage of the terminating power supply is used. In this case, the
reference voltage is equal to half of a supply voltage. Hence, it is
possible to receive a small amplitude waveform of 1 V or less around the
reference voltage.
For example, under the following condition, the amplitude at receiving
circuit is 0.68 V. Specifically, if each of the resistances of terminating
resistors 50, 51 is 50 ohms, each of the resistances of matching resistors
80, 81, 82 and 83 is 75 ohms and the on-resistance of driving circuit is
10 ohms, the supply voltage for the driving circuit is 3 V, and the
terminating supply voltage is 1.5 V, when the driving circuit is at a low
output, the voltage at each receiving circuit is 1.16 V (=1.5 V-(1.5
V-0).times.(50.OMEGA./2)/(50.OMEGA./2+75.OMEGA.+10)=1.5-0.34) and when the
driving circuit is at a high output , the voltage at each receiving
circuit is 1.84 V (=1.5 V+(3-1.5).times.(50/2)/(50/2+75+10)=1.5+0.34).
Thus, the amplitude at each receiving circuit is 0.68 V (=1.84-1.16).
In FIG. 4, just one receiving circuit 32 to 34 of each circuit block is
described by way of example. However, the present invention is not limited
by the number of the receiving circuits.
In the signal transmission circuit arranged as described above, the
resistance of each of the resistors 80 to 83 is made equal to a value
derived by subtracting a half of an impedance of the line 100 from an
impedance of the intra-block transmission line 11. The impedance of the
line 100 is required to be halved, because the signal from the driving
circuit block is branched into two ways at a contact point B with the bus
100. That is, the following expression is established:
Rm=Zs-ZO/2 (1)
where Zs denotes an impedance of the transmission line 11, ZO denotes an
impedance of the line 100, and Rm denotes a resistance of the resistor 80.
As is understood from this expression, the total impedance of the resistor
80 and the line 100 as viewed from the transmission line 11 is made equal
to the impedance of the transmission line 11 itself. This makes it
possible to prevent repetitive reflections inside of a branched line.
The resistors 81 to 83 may be defined by the similar method. As such,
another block may have the same effect as the foregoing block 1.
Next, to describe the effect of the resistor derived by the expression (1),
the kind of waveform which is transmitted to each point of FIG. 4 when the
driving circuit 21 is switched from a Low output to a High output will be
discussed below with reference to the circuit diagram of FIG. 4.
First, it is necessary to derive a potential of the transmission line 100
occurring when the driving circuit 21 feeds a Low output. The voltage of
the transmission bus is made equal to the voltage derived by dividing the
terminating supply voltage of 1.5 V by the termination resistors 50 and
51, the resistor 80 and the on resistance of the driving circuit 21.
Concretely, the voltage at the point B on the transmission line when the
driving circuit 21 provides a Low output is as follows:
1.5 V.times.(75.OMEGA.+10.OMEGA.)/(10.OMEGA.+75.OMEGA.+25.OMEGA.)=1.16 (V)
In the circuit of FIG. 4, the signal driven from the driving circuit 21 is
not reflected at the B point. Therefore, the overall signal is transmitted
to the transmission line 100. The potential of the signal transmitted to
the point B when the output of the driving circuit is switched from Low to
High is equal to the voltage given by dividing the terminating supply
voltage of 1.5 V and the supply voltage of 3 V of the driving circuit 21
by the terminating resistors 50 and 51, the resistor 80, and the on
resistance of the driving circuit 21. Hence, the signal potential at the B
point when the driving circuit 21 provides a High output is derived as
follows:
1.5 V+(3 V-1.5 V).times.25.OMEGA./(10.OMEGA.+75.OMEGA.+25.OMEGA.)=1.84 V
That is, the amplitude of the signal transmitted to the point B is;
1.84 V-1.16 V=0.68 V
When the signal of the amplitude of 0.68 V transmitted to the transmission
line 100 reaches the point C, though the transmission line of 50.OMEGA.,
the resistor of 75.OMEGA. and the transmission bus of 100.OMEGA. are
viewed in the front, the mismatch of the impedance brings about
reflection, because the total impedance of 38.9.OMEGA. of these two lines
is different from the impedance of 50.OMEGA. of the transmission line
through which the signal passes. The transmittance coefficient is: 1-the
reflection coefficient=1-1-(50-38.9)/(50+38.9)=0.875 The potential of the
signal passing through the point C is equal to the value derived by
multiplying the signal amplitude of 0.68 V at the point B by the
transmittance coefficient of 0.875 and adding an initial potential to the
multiplied value. That is, the potential of the signal is:
0.68 V.times.0.875+1.16 V=1.76 V
Similar reflections take place at the point E or the point G. The potential
at the E or the G point are 1.68 V and 1.61 V, respectively.
These results are shown in FIGS. 7A to 7C. FIG. 7A shows signal waveforms
which come to and go out of the point C, that is, the signal waveform at
the point B which comes to the point C and the signal waveforms at the
points D and E which go out of the point C. Likewise, FIG. 7B shows signal
waveforms which come to and go out of the point E. FIG. 7C shows signal
waveforms which come to and go out of the point G. In FIGS. 7A-7C, a
numeral 702 denotes a signal waveform at the point B i | | |
