Asynchronous transfer mode adapter for desktop applications

What is claimed is:

1. An ATM adapter for adapting a desktop user station to a local ATM network, comprising:

an adapter for interfacing said local ATM network, said adapter comprising an ATM integrated circuit for interfacing between a host device data bus and a local ATM network physical layer, said ATM integrated circuit, comprising:

a host interface circuit comprising a bus interface circuit, a DMA control circuit and a slave access control circuit, said bus interface circuit for interfacing said data host device bus, said DMA control circuit for controlling memory access operations between said ATM integrated circuit and associating with a RAM interface/arbiter interface circuit, said slave access control circuit for controlling operation of an interrupt circuit and a statistics circuit;

a segmentation engine associated with said RAM/interface arbiter circuit for segmenting data from said host device data bus into ATM cells in preparation for said data to be transferred transfer on said local ATM network;

a reassembly engine associated with said RAM/interface arbiter circuit for reassembling ATM cells from said local ATM network into data suitable for transfer to said host device data bus;

said RAM interface/arbiter circuit for interfacing said DMA control circuit, said slave access control circuit, said segmentation engine, and said reassembly engine with a memory circuit associated with said ATM integrated circuit; and

a physical interface circuit associated between said segmentation engine and said reassembly engine on a first interface and the local ATM network on a second interface for interfacing said ATM integrated circuit physically with said local ATM network;

further wherein said host interface circuit, said physical interface circuit, said segmentation engine, said reassembly engine, and said RAM interface/arbiter circuit are formed as an integrated circuit.

2. The asynchronous transfer mode adapter circuit of claim 1, further comprising a memory arbiter circuit for arbitrating access to said memory from among said memory access controller, said slave access control circuit, said segmentation engine, and said reassembly engine.

3. The asynchronous transfer mode adapter circuit of claim 1, wherein said integrated circuit transmits ATM cells as protocol data units.

4. The asynchronous transfer mode adapter circuit of claim 1, wherein said adapter supports both AAL5 and non-AAL5 transfer modes.

5. The asynchronous transfer mode adapter circuit of claim 1, wherein said segmentation engine uses predefined descriptors for avoiding the transfer of meaningless information, while moving pointers for indicating the receipt and processing of ATM cells.

6. The asynchronous transfer mode adapter circuit of claim 1, further comprising circuitry for supporting AAL5 conformance protocols at a common part convergence sublayer.

7. The asynchronous transfer mode adapter circuit of claim 1, further comprising AAL5 conformance protocols in said segmentation engine.

8. The asynchronous transfer mode adapter circuit of claim 1, further comprising AAL5 conformance protocols in said reassembly engine.

9. The asynchronous transfer mode adapter circuit of claim 1, wherein said physical interface circuit comprises circuitry for interfacing a Utopia interface.

10. The asynchronous transfer mode adapter circuit of claim 1, further comprising circuitry for communicating operation and maintenance cells with said local area network.

11. The asynchronous transfer mode adapter circuit of claim 1, further comprising peak cell rate circuitry within said segmentation engine for shaping traffic flow within said segmentation engine.

12. The asynchronous transfer mode adapter circuit of claim 1, wherein said segmentation engine segments eight channels of data simultaneously for transfer on said local area network.

13. The asynchronous transfer mode adapter circuit of claim 1, wherein said reassembly engine comprises circuitry for reassembling 1024 cells within said integrated circuit.

14. The asynchronous transfer mode adapter circuit of claim 1, wherein said reassembly engine provides ten bits of virtual channel identifier space.

15. An ATM adapter for desktop applications having an ATM integrated circuit, said ATM integrated circuit comprising:

a host interface circuit for interfacing a host device, said host interface circuit comprising a host device bus interface circuit, a DMA control circuit, and a slave access control circuit;

said host device bus interface circuit for interfacing said host interface circuit with a host device data bus for communicating host device data between said host interface circuit and said host device data bus;

said DMA control circuit associated with said bus interface circuit for controlling DMA operations associated with said host device data;

said slave access control circuit associated with said bus interface circuit for controlling operations of said host interface circuit relating to host device bus interrupts and statistics;

a physical interface circuit associated with an ATM physical layer for communicating ATM formatted data with a local ATM network;

a segmentation engine associated with said physical interface circuit for transmitting ATM formatted data to said physical interface circuit, said segmentation engine associated further for receiving said host device data and segmenting said host device data to form outgoing ATM formatted data;

a reassembly engine associated with said physical interface circuit for receiving incoming ATM formatted data from said local ATM network and generating therefrom from host device data for transmission to said host interface circuit;

a RAM interface/arbiter circuit associated with a RAM bus for communicating with a RAM, said RAM interface/arbiter circuit further associated with said DMA control circuit, said slave access control circuit, said segmentation engine and said reassembly engine for interfacing and arbitrating access to said RAM of signals communicated with said DMA control circuit, said slave access control circuit, said segmentation engine, and said reassembly engine; and

further wherein said host interface circuit, said physical interface circuit, said segmentation engine, said reassembly engine, and said RAM interface/arbiter circuit are formed as an integrated circuit.

16. The ATM integrated circuit of claim 15, wherein said segmentation engine segments AAL5 traffic and further wherein said physical interface circuit communicates AAL5 traffic with the local ATM network.

17. The ATM integrated circuit of claim 15, wherein said segmentation engine segments traffic other than AAL5 traffic and further wherein said physical interface circuit transmits to the local ATM network traffic other than AAL5 traffic.

18. The ATM integrated circuit of claim 15, wherein said segmentation engine further comprises a segmentation buffer, said segmentation buffer further comprising a segmentation buffer descriptor portion and a data portion for receiving data to be segmented into ATM formatted data.

19. The ATM integrated circuit of claim 15, wherein said segmentation engine further performs traffic shaping in response to a pre-scale parameter and a rate resolution parameter.

20. The ATM integrated circuit of claim 15, wherein said reassembly engine updates a service list describing completed reassembly operations on said ATM formatted data.

21. The ATM integrated circuit of claim 15, wherein said segmentation engine further comprises circuitry for performing the steps of:

enqueueing a protocol data unit for the DMA control circuit;

reading a queue in response to the enqueued protocol data unit;

segmenting the protocol data unit; and

providing data to said host interface circuit in response to said segmented protocol data unit.

22. The ATM integrated circuit of claim 15, wherein said reassembly engine further comprises circuitry for performing the steps of:

receiving a host device data from said host interface circuit;

enqueueing a DMA receive queue in response to said host device data;

reading a DMA receive queue from a memory map associated with said DMA control circuit;

receiving an operation and maintenance cell through said physical interface circuit;

responding to a change signal from said host interface circuit; and

receiving an incomplete cell from said host interface circuit.

23. The ATM integrated circuit of claim 15, further comprising circuitry for supporting operation and maintenance cells associated with said local ATM network.

24. The ATM integrated circuit of claim 15, further comprising circuitry for permitting simultaneous operation of at least eight segmentation channels from said RAM interface/arbiter circuit and at least 1,024 reassembly operations on said ATM formatted data.

25. The ATM integrated circuit of claim 15, further comprising circuitry for processing virtual channel identifier and virtual path identifier information.

26. The ATM integrated circuit of claim 15, further comprising circuitry for shaping peak cell rate traffic.

27. The ATM integrated circuit of claim 15, further comprising circuitry for inserting ATM cell header fields in association with said ATM formatted data that is to be communicated on said local ATM network.

28. The ATM integrated circuit of claim 15, further comprising circuit for allocating reassembly buffer space associated with said reassembly engine and wherein said host interface circuitry further comprises circuitry for notifying the host device data bus of the receipt of information from said local ATM network.

29. The ATM integrated circuit of claim 15, further comprising circuitry for reporting status of said ATM integrated circuit and for reporting errors associated with operation of said ATM integrated circuit.

30. The ATM integrated circuit of claim 15, further comprising interface circuitry for associating said physical interface circuitry with a UTOPIA interface.

31. The ATM integrated circuit of claim 15, wherein said physical interface circuit further comprises circuitry for operating in a non-pipelined read UTOPIA mode.

32. The ATM integrated circuit of claim 15, wherein said physical interface circuit further comprises circuitry for operating in an asynchronous interface mode.

33. The ATM integrated circuit of claim 15, wherein said physical interface circuit further comprises a mode control register for controlling the operational mode of said physical interface circuit.

34. The ATM integrated circuit of claim 15, wherein said slave access control circuit further comprises circuitry for accessing adapter memory associated with said memory circuit and memory associated with internal registers within said ATM integrated circuit in response to addresses determined by said host interface circuit.

35. The ATM integrated circuit of claim 15, wherein said integrated circuit comprises circuitry for responding to local ATM network data having the types of byte burst, half-word burst, word burst, two-word burst, four-word burst, eight-word burst, and sixteen-word burst.

36. The integrated circuit of claim 15, wherein said host interface circuit associates for generating a words-maybe cycle including a complete burst, a portion of said complete burst having data that will be ignored by said host device.

37. The ATM integrated circuit of claim 15, wherein said host interface circuit further comprises a statistics circuit for maintaining a plurality of statistics counters of trashed cells.

38. The ATM integrated circuit of claim 15, wherein said host interface circuit further comprises a statistics circuit, said statistics circuit comprising a virtual channel identifier trash counter circuit comprising an overflow trash counter.

39. The ATM integrated circuit of claim 15, wherein said host interface circuit further comprises interrupt circuitry for processing interrupt generation.

40. The ATM circuit of claim 15, wherein said host interface circuit further comprises interrupt circuitry, said interrupt circuitry further comprising circuitry for responding to interrupts arising from an event within said ATM integrated circuit and further comprising circuitry responsive to interrupts arising from an external source associated with said physical interface circuit.

41. The ATM integrated circuit of claim 15, wherein said DMA control circuit further comprises circuitry for shaping traffic in response to a peak cell rate counter circuit for traffic on a single segmentation channel associated with said segmentation engine.

42. The ATM integrated circuit of claim 15, wherein said DMA control circuit further comprises an arbiter-multiplexor circuit associated with said DMA control circuit for shaping traffic across a plurality of segmentation channels associated with said segmentation engine.

Description Submit all comments and votes

TECHNICAL FIELD OF THE INVENTION

The present invention is generally concerned with data communication systems and methods for transmitting and exchanging electronic data between two points and, more particularly, to an asynchronous transfer mode (ATM) adapter for providing ATM capability in a workstation or desktop environment.

BACKGROUND OF THE INVENTION

In today's telecommunications and data processing industries, high speed, low-cost distribution and exchange of large amounts of information has become highly important. Manufacturing companies desire to distribute CAD/CAM design activities among premises. Publishing companies seek to design layouts electronically and share them among groups at different sites. Hospitals want to share detailed medical records in near real time. Until recently, all of these activities have been constrained by technology to a single building or campus. Companies have needs to lift constraints by using real-time networking technologies to replace overnight courier delivery. There is also a trend in both commerce and government toward data center consolidation. Organizations would like to serve local work groups from remote data centers. They need networking to do that and they need networking to back up these new, consolidated data centers so that they do not become a single point of failure for their entire operation.

Something that all these applications have in common is that they require that bits be passed at speeds higher than conventional T1 rate of 1.544 Mbps. Some applications demand higher speed on a sustained basis. Some applications require more bandwidth so that a burst can be delivered quickly. T1 or slower is what is typically installed in a wide area network. This represents a mismatch with the local area where the slowest speed generally used is 10 Mbps, i.e., in the Ethernet environment. The need for more bandwidth alone, however, is not enough to justify a new technology. Time division multiplexing (TDM) effectively scales up to SONET speeds of 155 Mbps. The problem with TDM is that it cannot provide true bandwidth-on-demand. New applications that are emerging present traffic to the network as large bursts of bits followed by lengthy interburst gaps.

ATM, when implemented properly, is able to make bandwidth available to carry the burst without disrupting other users. It is also able to make the bandwidth available to other users during the interburst period, thereby maintaining the cost-efficiency while carrying the applications in near real time.

In designing networks that use ATM technology, four factors require consideration: 1) complexity--complexity must appear to go away; networks should be kept as simple as possible; 2) economics--recurring bandwidth and operations costs must be contained; 3) transmission delay--the time it takes traffic to travel from origin to destination must be short; and 4) user demand--characteristics of the network must be appropriate to the application; that means information transfer may be required by the application to occur in near real time.

ATM combines the strengths of traditional packet switching--bandwidth efficiency--with those of circuit switching--high throughput, low delay, and transparency. Application traffic (voice, data, video, and image) is encapsulated in 53-byte cells for transport across the network. In contrast to traditional packet switching, no error processing occurs at the ATM layer, but is handled by the higher protocols in the attached DTE equipment. Therefore, ATM cells can be switched in hardware in gigabit speed with low delays. Because of the low latency and high throughput capabilities, ATM is the ideal technology to support these applications over the corporate network. It can support isochronous traffic, like voice and video, as well as bursty data, like local area internetworking, and traditional data, like SNA and X.25. The scalability of ATM makes it an attractive alternative for today's shared-media local area networks (LANs).

Since only meaningful information, such as active speech or payload data, is encapsulated in ATM cells for transfer across the network, bandwidth resources are used efficiently. By not wasting bandwidth resources for idle flags and silence periods during conversation, networks can be designed to make better use of available wide area facilities. ATM networks can be designed for least cost, while maintaining the quality of service (QoS) requirements of a wide variety of applications.

The challenges that must be overcome to attain seamless network vision are substantial. First, there are differences surrounding ATM deployment in the local versus wide area networks. These result in varying implementations in local area network and wide area network products that must interoperate to provide total network solutions. Second, there is the requirement for multi-vendor interoperability. Third, there are economic aspects that must be considered when migrating to the seamless ATM network.

Most of the focus in the local area network arena today has been put on pure data traffic. Voice and video are typically handled by specific communications equipment, completely separate from the local area network. Although multimedia is seen as one of the drivers of ATM to the desktop, current ATM LAN implementations are directed to the support of LAN data traffic only. On the other hand, a wide variety of traffic type traditionally has been supported over the wide area. To effectively integrate these traffic types with their specific performance criteria, ATM equipment must include sophisticated queuing, congestion, and routing algorithms.

The seamless network providing desktop-to-desktop multimedia networking is an exceedingly attractive solution that meets the high performance and flexibility required by future enterprise environments. To date, however, no method, system, or architecture having both an economically practical price and the desired level of performance exists that provides ATM network capabilities in the desktop environment.

Consequently, there is the need for a system that provides ATM network capabilities in the desktop environment.

There is a need for an ATM method and system that satisfactorily addresses the important considerations of local area and wide area network interoperability, multi-vendor interoperability, and economy in manufacture and implementation.

There is, in essence, the need for a method and system that satisfactorily addresses requirements in terms of both price and performance in bringing ATM to the desktop.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides an asynchronous transfer mode (ATM) adapter for desktop applications that overcomes or substantially reduces limitations that exist in the ATM network environment.

According to one aspect of the invention there is provided an ATM adapter for desktop applications that includes an adapter for interfacing an ATM network. The adapter includes an ATM application specific integrated circuit (ASIC). The ATM ASIC may interface with a data bus such as an SBus using a host interface circuit. The host interface circuit includes a bus interface, a direct memory access or DMA controller and a slave access controller. The DMA controller controls DMA operations within the ATM ASIC and associates with a RAM interface arbiter. The slave access controller controls operation of both an interrupt circuit that goes to the SBus and a statistics circuit. The RAM interface arbiter arbitrates communication between the DMA controller, the slave access control circuit, a segmentation engine, and a reassembly engine. The RAM interface arbiter communicates with the RAM bus to a RAM associated with an adapter. The segmentation engine segments data into ATM format for transfer through a physical interface circuit. The physical interface circuit also receives formatted ATM information and sends that information to the reassembly engine. The reassembly engine reassembles the ATM data and transmits it through the RAM interface/arbiter circuit to the RAM bus. From the RAM bus, data may pass again through the RAM interface/arbiter to the DMA controller and onto the SBus through the host bus interface.

The present invention provides numerous technical advantages including the ability to communicate at the desktop level with an ATM network both economically and with a high degree of performance efficiency and quality of service. The present invention solves numerous problems associated with operating in a local area network using ATM formats and protocols.

More particular technical advantages that the present invention provides relate to ATM aspects of the ATM ASIC. For example, the ATM ASIC provides AAL5 conformance for the common part convergence sublayer, as well as desired segmentation and reassembly aspects. The ATM ASIC provides operation and maintenance cell support, simultaneous operation of eight segmentation channels and 1024 reassembly operations. Support for ten bits of virtual channel identifier and zero bits of virtual path identifier is also provided by the ATM ASIC of the present invention. In addition, peak cell rate traffic shaping support is a particularly attractive technical advantage or feature of the present invention. The present invention furthermore provides support for non-AAL5 traffic while providing status and error reporting capabilities. These and other technical advantages and features of the present invention will be apparent upon the review of the following detailed description together with the associated FIGUREs.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and its modes of use and advantages are best understood by reference to the following description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:

FIG. 1 provides an overview of the ATM communication process together with the protocols that operate at various ATM protocol layers of communication between two end stations;

FIG. 2 illustrates conceptually the operation of a local area network that provides ATM communication to the desktop;

FIG. 3 provides a block diagram of the application specific integrated circuit of the present embodiment that forms part of the ATM adapter for the present embodiment of the invention;

FIG. 4 provides a table indicating the mode control register bit positions of the present embodiment;

FIGS. 5 through 18 include in detail the register bits, types, defaults, names, and descriptions for the present embodiment of the invention;

FIGS. 19 through 23 provide timing diagrams for the RAM, PHY layer, and EEPROM of the present embodiment;

FIG. 24 provides a table detailing absolute minimum and maximum ratings for the present embodiment of the invention;

FIG. 25 is a table that provides recommended operating conditions for the present embodiment;

FIG. 26 provides access, read, and write time ranges for the present embodiment of the invention;

FIG. 27 includes a memory map that illustrates conceptually the allocation of registers in the present embodiment of the invention;

FIG. 28 provides a block diagram of the segmentation engine of the present embodiment;

FIG. 29 provides a conceptual illustration of the eight segmentation channels of the present embodiment;

FIGS. 30 and 31 show the bit-aligned contents for AAL5 and non-AAL5 segmentation buffers, respectively, in the present embodiment;

FIG. 32 provides a table describing the segmentation control block field contents and functions in the present embodiment;

FIG. 33 conceptually illustrates the DMA transmit queue format for the present embodiment;

FIG. 34 is a table describing the DMA transmit queue field pointers to the next wright area and the current read area of the DMA transmit queue for the present embodiment;

FIG. 35 illustrates in block diagram form the peak cell rate circuit of the present embodiment;

FIG. 36 includes a table of the peak cell rate values for the present embodiment;

FIG. 37 includes a table that lists the possible size and location parameter values for the present embodiment;

FIG. 38 illustrates building the 19 bit addresses when addressing into a segmentation or reassembly queue in the present embodiment.

FIG. 39 conceptually illustrates the reassembly data structures that the present embodiment uses;

FIG. 40 depicts the format of the VCI table of the present embodiment;

FIGS. 41 and 42 show, respectively, the reassembly buffers for AAL5 and non-AAL5 transfer modes;

FIG. 43 provides a Service List format for the present embodiment;

FIG. 44 includes a table of the pointers to the Service List of the present embodiment;

FIG. 45 depicts the DMA receive queue format for the reassembly operations of the present embodiment;

FIG. 46 provides a table describing the DMA receive queue pointers for the present embodiment;

FIGS. 47 depicts in more general terms the application, libraries, operating systems, and hardware functions applicable to the present embodiment; and

FIGS. 48 through 51 provide host interface pin descriptions for the present embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The illustrative embodiments of the present invention are best understood by referring to the FIGUREs wherein like numerals are used for like and corresponding parts of the various components.

FIG. 1 provides an overview of the ATM communication process together with the functions that take place at various layers of communication between communicating end stations. Within the framework of ATM protocol layers 10, ATM protocols provide communication paths between end station A and end station B. End station A may be, for example, an end station, while end station B may be, for example, a workstation or peripheral, an end station or a B-ISDN switch. Protocol diagram 10, therefore, represents the various protocols that exist when end station A communicates through ATM protocol layers 12 to end station B which uses ATM protocol layers 14. Fibre or twisted pair connection 16 represents the physical connection between end station A and end station B. ATM protocol layers 12 for end station A include upper layers 18 through which service occurs between ATM adaptation layer (AAL) layer 20. AAL layer 20 services and receives service from ATM layer 22. ATM layer 22 services and receives service from physical layer 24. Fibre or twisted pair connection 16 connects physical layer 24 for end station A with physical layer 26 for end station B. For end station B, physical layer 26 services and receives service from ATM layer 28. ATM layer 28 services and receives service from AAL layer 30. Upper layers 32 service and receives service from AAL layer 30.

For the layers of FIG. 1, which includes a transfer control protocol/internet protocol (TCP/IP) or equivalent services in upper layers 18. AAL layers 20 and 30 provide protocols for segmentation, reassembly, reassembly error detection, and message identification multiplexing. ATM layers 20 and 28 include protocols for cell multiplexing, cell relaying, and interface identification. Physical layers 22 and 28 include transfer convergence layers 34 and 36, as well as physical medium dependent layers 38 and 40, respectively. At physical layers 22 and 28, header error control (HEC) generation, HEC verification, and cell framing recovery protocols operate at the physical layers 22 and 28. At physical medium dependent sublayers 38 and 40, bit timing and physical medium interface protocols appear.

At each of the layers between end station A and end station B in FIG. 1, protocols also exist to permit peer-to-peer addressing. For example, bidirectional arrow 42 indicates peer-to-peer protocols that exist between upper layers 18 and 32. Bidirectional arrow 44 indicates protocols that exist for information exchanged between AAL layer 20 and AAL layer 30. Bidirectional arrow 46 depicts peer-to-peer protocols that exist for information exchanged in control between ATM layer 22 and ATM layer 28, and bidirectional arrow 48 indicates peer-to-peer protocols for physical layer 22 and physical layer 28 information exchanged in control.

With ATM, three planes exist: (1) the user plane, (2) the control plane, and (3) the management plane. In the user plane transfer of end-user information occurs. The user plane consists of physical layer 22 and ATM layer 22. For each end-user application, the ATM protocol model includes AAL layer 20 and higher layers as necessary. The control plane provides for the transfer of information to support connection establishment and control functions necessary for providing switched services. The control plane shares ATM layer 22 and physical layer 22 protocols with the user plane. The control plane also uses AAL protocols and higher layer signalling protocols. The management plane provides operations and management (OAM) functions and the capability to exchange information between the user plane and the control plane. The management plane includes management functions for layer management and plane management. The layer of management functions of the management plane include detection of failures in protocol abnormalities. The management plane functions include management and coordination functions related to the complete system.

Physical layer 24 provides access to the fibre or twisted pair 16 for the transport of ATM cells between end station A and end station B. It includes methods for mapping cells into transfer conversion sublayers 34 and 36 as well as methods dependent on the physical medium that exists within physical medium dependent sublayers 38 and 40. ATM layer 22 and 28 make possible to transport a cell between end-user locations.

To more completely understand the services that occur at each of the above-described layers, reference is here made to known ATM documents and specifications, including ITU-T recommendation X.210, Open Systems Interconnection, Layer Service Deformation Convention, Geneva, Switzerland, 1989; ITU-T Recommendation 1.361, B-ISDN ATM Layer Specification, Geneva, Switzerland, June 1992; T1S1.5/92-410, Broadband ISDN-ATM Layer Functionality Specification, August 1992; ATM Forum, ATM User-Network Interface Specification, Version 3.0, August, 1993; The ATM Forum, An ATM PHY Data path Interface, Level 1-Version 1.22; SUN Microsystems: SBus Specification B.0, 1990; and ANSI T1. ATM-1993, Broadband ISDN-ATM Layer Functionality Specification, New York. All of the above references and standards are here expressly incorporated by reference. Moreover, and consistent with much of the terminology of the above references, TABLE 1 includes terms having general meanings that include, at a minimum, those specified.

TABLE 1 ______________________________________ AAL A layer that adapts higher-layer user protocols (e.g., TCP/IP, APPN) to the ATM protocol (layer). AAL connection An association established by the AAL between two or more next higher layer entities. Asynchronous A transfer mode in which the transfer mode (ATM) information is organized into cells. It is asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. ATM Layer An association established by the connection ATM Layer to support communication between two or more ATM service users (i.e., between two or more next higher layer entities or between two or more ATM management entities). The communication over an ATM Layer connection may be either bidirectional or unidirectional. When it is bidirectional, two VCCs are used. When it is unidirectional, only one VCC is used. ATM peer-to-peer A virtual channel connection (VCC) connection or a virtual path connection (VPC). ATM traffic A generic list of traffic descriptor parameters that can be used to capture the intrinsic traffic characteristics of a requested ATM connection. ATM user-user An association established by the connection ATM Layer to support communication between two or more ATM service users [i.e., between two or more next-higher-layer entities or between two or more ATM management (ATM) entities]. The communication over an ATM Layer connection may be either bidirectional or unidirectional. When it is bidirectional, two VCCs are used. When it is unidirectional, only one VCC is used. Broadband A service or system requiring transfer channels capable of supporting rates greater than the Integrated Service Digital Network (ISDN) primary rate. Cell ATM Layer protocol data unit. Cell header ATM Layer protocol control information. Connection The concatenation of ATM Layer links in order to provide an end- to-end information transfer capability to access points. Header Protocol control information located at the beginning of a protocol data unit. Operation and A cell that contains ATM Layer maintenance (OAM) Management (LM) information. It cell does not form part of the upper- layer information transfer. Physical Layer An association established by the (PHY) connection PHY between two or more ATM, entities. A PHY connection consists of the concatenation of PHY links in order to provide an end-to-end transfer capability to PHY SAPS. Protocol A set of rules and formats (semantic and syntactic) that determines the communication behavior of layer entities in the performance of the layer functions. Protocol control Information exchanged between information (PCI) corresponding entities, using a lower-layer connection, to coordinate their joint operation. Protocol data unit A unit of data specified in a (PDU) layer protocol and consisting of protocol control information and layer user data. Relaying A function of a layer by means of which a layer entity receives data from a corresponding entity and transmits them to another corresponding entity. Service access The point at which an entity of a point (SAP) layer provides services to its layer management entity or to an entity of the next higher layer. Service data unit A unit of interface information (SDU) whose identity is preserved from one end of a layer connection to the other. Sublayer A logical subdivision of a layer. Switched connection A connection established via signalling. Traffic parameter A parameter for specifying a particular traffic aspect of a connection. Trailer Protocol control information located at the end of a PDU. Transit delay The time difference between the instant at which the first bit of a PDU crosses one designated boundary and the instant at which the last bit of the same PDU crosses a second designated boundary. Virtual channel A communication channel that (VC) provides for the sequential unidirectional transport of ATM cells. Virtual path (VP) A unidirectional logical association or bundle of VCs. ______________________________________

FIG. 2 illustrates conceptually the operation of a local area network that provides ATM communication to the desktop to illustrate the portion of a communications network that the present invention addresses. The present invention makes possible a highly efficient local area network that includes, as its basis, information exchange and control for ATM connections. In FIG. 2, customer site 50 includes local ATM-based network 52 having ATM switch 54, ATM switch 56, ATM switch 58, and ATM switch 60.

In the example, ATM switch 54 may connect with ATM switch 56 through interface 62 and ATM switch 60 through interface 64. Similarly, ATM switch 58 may connect to ATM switch 56 through interface 66 and to ATM switch 60 through interface 68. Connected to local ATM-based network 52 may be, for example, user end station 70 to ATM switch 54, user end station 72 to ATM switch 56, and user end station 74 to ATM switch 56. ATM switch 56 may also, for example, connect to a host 76 which may be a super computer or other end station as well as to memory end station 78. ATM switch 58 may connect to user end station 80 as well as to a peripheral 82 which may be, for example, a printer or other end station.

In local ATM-based network 52, ATM switch 60 may also connect to user end station 84, to router 86 (which may further connect to non-ATM wide area network), and to an ATM/B-ISDN public wide area network 88 outside of customer site 50. The topology that the local ATM environment of customer site 50 depicts, therefore, includes point-to-point links such as links 90 between ATM switch 54 and end station 70. In addition, local ATM environment 50 includes interfaces between ATM switches such as link 61 between ATM switch 54 and ATM switch 56. Even further, link 92 between ATM switch 60 and ATM/B-ISDN public wide area network 88 depicts an interface between the local environment and the wide area network environment. Within this environment, the present invention makes possible ATM-based information transfer and exchange possible from desktop-to-desktop.

The present embodiment provides ATM capabilities to the desktop through a 155.52 Mbps adapter for any SBus platform. The present embodiment interfaces a 155.52 Mbps SBus adapter for SPARCstations and SPARCservers such as those manufactured by Sun Microsystems, Inc. and other vendors for a multimode fibre or Category 5 unshielded twisted-pair interface at 155.52 Mbps. Other embodiments of the present invention may adapt ATM technology to a Peripheral Component Interconnect bus, such as that used in Intel Corp. Pentium and IBM PowerPC computers and the GIO bus by Silicon Graphics, Inc. The adapter of the present embodiment may also support midrange speed ATM at 52 Mbps over Categor