Apparatus and method for synchronizing asynchronous signals

What is claimed is:

1. An electronic apparatus for processing an input signal having synchronizing components including in combination:

a) an input processing section responsive to said input signal to separate said synchronizing components therefrom and to provide a processed signal;

b) a clock section for generating a sampling clock;

c) a sampling section operative to sample said processed signal and provide samples thereof in response to said clock section;

d) an interpolation section responsive to groups of said samples to perform interpolation thereof to provide filtered samples having improved resolution;

e) a memory section responsive to a reference signal and said filtered samples to provide a stored signal synchronized in response to said reference signal which reference signal may be a phase shifted version of said input signal.

2. Apparatus as claimed in claim 1 wherein said clock section operates to provide a sampling clock having a predetermined relationship with said synchronizing components.

3. Apparatus as claimed in claim 1 wherein said sampling section operates to continuously sample the full amplitude of said input signal over at least one repetition period and wherein said memory section stores at least said one repetition period worth of said filtered samples.

4. Apparatus as claimed in claim 1 wherein said synchronizing components define horizontal lines and said clock section for generating a sampling clock operates to provide a known number of sampling clocks for each horizontal line and wherein said sampling section operates to sample said input signal to provide said known number of samples for each said horizontal line, and where said interpolation section is responsive to said known number of samples which have a first resolution to provide a second number of filtered samples having a second resolution.

5. Apparatus as claimed in claim 1 wherein said sampling section operates to continuously sample said input signal over at least one repetition period and wherein said memory section stores at least said one repetition period worth of said filtered samples, said apparatus further including an input signal disruption section to detect when said input signal is disrupted, with said memory section responsive thereto to repetitively output said repetition period of stored filtered samples during at least the pendency of said disruption.

6. Apparatus as claimed in claim 1 further including

f) a second input processing section responsive to a second input signal to separate synchronizing components therefrom and to provide a second processed signal;

g) a second clock section for generating a second sampling clock;

h) a second sampling section operative to sample said second processed signal and provide samples thereof in response to said clock section;

i) a second interpolation section responsive to groups of said samples from h) above to provide filtered samples;

j) a memory section responsive to said reference signal from e) above and said filtered samples from i) above to provide synchronization of said filtered samples from i) to said reference signal which reference signal may be a version of one of said input signal or said second input signal.

7. An apparatus responsive to a reference signal and operative with a plurality of input electronic signals having uncontrolled synchronization thereto including in combination for each said input signal:

a) an input processing section responsive respectively to said input signal to provide synchronizing components related thereto and to provide a processed signal which is a version of said input signal;

b) for each said input signal a clock section for generating a sampling clock;

c) a sampling section operative to sample said processed signal and provide samples thereof in response to said clock section;

d) a memory section responsive to said reference signal and said samples to provide a stored signal synchronized in response to said reference signal.

8. Apparatus as claimed in claim 7 further including an interpolation section responsive to groups of said samples from c) to perform interpolation thereof to provide filtered samples with said memory section from d) responsive to said filtered samples in place of said samples from c) to provide synchronization of said filtered samples in response to said reference signal.

9. An electronic apparatus for processing an input signal which is a video signal including in combination:

a) an input processing means responsive to said input signal to separate horizontal synchronizing components therefrom and to provide a processed signal which has been restored to a known DC value;

b) a clock means for generating a sampling clock which is phase locked to said horizontal synchronizing components;

c) a sampling means operative to sample and digitize said processed signal and provide samples thereof in response to said sampling clock;

d) an interpolation means responsive to groups of said samples to perform interpolation thereof to provide filtered samples having improved bits of resolution;

e) a memory means responsive to a reference signal to temporarily store said filtered samples to provide a stored signal synchronized in response to said reference signal which reference signal may be a version of said input signal.

10. Apparatus as claimed in claim 9 wherein said clock means operates to provide a sampling clock having a predetermined integer multiple frequency relationship with said synchronizing components and with a known phase relationship.

11. Apparatus as claimed in claim 9 wherein said sampling means operates to continuously sample the full amplitude from sync tip to peak white of said input signal over at least one repetition period of the scanning and color subcarrier cycles and wherein said memory means stores at least said one repetition period worth of said filtered samples.

12. Apparatus as claimed in claim 9 wherein said sampling means operates to sample said input signal to provide a known number of samples for each horizontal line, and where said interpolation means is responsive to said known number of samples which have a first number of bits resolution to provide a second number of filtered samples having a second number of bits resolution.

13. Apparatus as claimed in claim 9 wherein said sampling means operates to continuously sample said input signal over at least one repetition period of the scanning and color subcarrier cycles and wherein said memory means stores at least said one repetition period worth of said filtered samples, said apparatus further including an input signal disruption means to detect when said input signal is disrupted, with said memory means responsive thereto to cease storing of samples and repetitively output said repetition period of stored filtered samples during at least the pendency of said disruption.

14. Apparatus as claimed in claim 9 further including

f) a second input processing means responsive to a second input signal which is a video signal to separate synchronizing components therefrom and to provide a second processed signal;

g) a second clock means for generating a second sampling clock which is phase locked to said synchronizing components from f);

h) a second sampling means operative to sample and digitize said second processed signal and provide samples thereof in response to said second sampling clock from g);

i) a second interpolation means responsive to groups of said samples from h) to provide filtered samples;

j) a memory means responsive to said reference signal from e) to temporarily store said filtered samples from i) to provide synchronization of said filtered samples from i) in response to said reference signal from e) which reference signal may be a version of one of said input signal or said second input signal.

15. An apparatus responsive to a reference signal and operative with a plurality of mutually unsynchronized input signals which are video signals including in combination:

a) for each said input signal an input processing means responsive respectively to said input signal to provide horizontal synchronizing components related thereto and to provide a processed signal which is a DC restored version of said input signal;

b) for each said input signal a clock means for generating a sampling clock phase locked to said horizontal synchronizing components corresponding thereto;

c) for each said input signal a sampling means operative to sample and digitize the corresponding said processed signal and provide samples thereof in response to the corresponding said clock means;

d) for each said input signal a memory means responsive to said reference signal and the corresponding said samples to provide a stored signal synchronized in response to said reference signal.

16. Apparatus as claimed in claim 15 further including for each said input signal an interpolation means responsive to the corresponding groups of said samples from c) to perform interpolation thereof to provide filtered samples with the corresponding said memory means from d) responsive to said filtered samples in place of said samples from c) to provide synchronization of said filtered samples in response to said reference signal.

17. Apparatus as claimed in claim 1, 2, 3, 5, 6, 8, 9, 10, 11, 12, 13, 14, or 16 wherein said interpolation operates in response to a first number of samples at a first amplitude resolution to provide a second number of samples at a second improved amplitude resolution.

18. An electronic apparatus for processing an input signal having synchronizing components including in combination:

a) an input processing section responsive to said input signal to separate said synchronizing components thererefrom and to provide a processed signal;

b) a clock section for generating a sampling clock;

c) a sampling section operative to continuously sample said input signal over at least one repetition period in response to said sampling clock and provide samples thereof;

d) an input signal disruption section to detect when said input signal is disrupted;

e) a memory section responsive to said sampling section to store said samples of at least one repetition period and to provide a stored signal synchronized in response to a reference signal which reference signal may be a version of said input signal, with said memory section further responsive to said input signal disruption section to repetitively output said repetition period of stored samples during at least the pendency of said disruption.

19. Apparatus as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 or 18 wherein said memory section is operative to temporarily store a secondary signal in an amount corresponding to the storage of said input signal.

20. Apparatus as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 or 18 further including:

a reference signal detector operative to determine the presence of an external reference signal;

a switch responsive to said reference signal detector and operative to select said input video signal for use as said reference signal.

21. Apparatus as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 or 18 further including:

a reference signal detector operative to determine the presence of an external reference signal;

a switch responsive to said reference signal detector and operative to select said input video signal for use as said reference signal with said apparatus operating thereby as a fixed length delay;

a phase adjustment responsive to said input signal being used as said reference signal to allow the length of said fixed length delay to be adjustable.

22. Apparatus as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 or 16 further including:

a digitizer section to digitize said samples of said input signal;

said interpolation operative to provide digital filtered samples having improved quantizing error;

a image processing circuit responsive to said digital filtered samples in undelayed or relatively delayed form, or both, to improve the visual quality of the image represented by said digital filtered samples.

23. Apparatus as claimed in claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 or 18 further including:

a video processing circuit operative to select portions contained within the blanking areas of said stored signal from said memory section in order that said selected portions may be preserved and passed and further operating such that known ones of the repetitive sync burst and blanking portions contained within the blanking areas of said stored signals from said memory section are reconstructed and inserted in said stored signals from said memory section.

24. A method for processing an input signal having synchronizing components including in combination the steps of:

a) recovering said synchronizing components from said input signal;

b) providing a processed signal in response to said input signal;

c) generating a sampling clock;

d) sampling said processed signal to provide samples thereof in response to said sampling clock;

e) interpolating said samples to provide filtered samples having improved resolution;

f) temporarily storing said filtered samples to provide a synchronized signal synchronized in response to said reference signal which reference signal may be a version of said input signal.

25. The method of claim 24 wherein the step c) of generating said sampling clock includes providing a predetermined phase relationship between said sampling clock and said synchronizing components.

26. The method of claim 24 wherein said sampling of step d) is performed in a manner to sample the full amplitude of said input signal continuously over at least one repetition period thereof and wherein said storing step f) includes storing at least said one repetition period worth of said filtered samples.

27. The method of claim 24 wherein said synchronizing components define horizontal lines and said sampling clock provides a known number of samples for each horizontal line and wherein said sampling step d) provides samples in said known number for each said horizontal line, with said interpolation step e) responsive to said known number of samples which have a first resolution to provide a second number of filtered samples having a second resolution.

28. The method of claim 24 wherein said sampling is performed continuously to sample said input signal over at least one repetition period and wherein said storing step stores at least said one repetition period worth of said filtered samples, said method further providing;

a step to detect when said input signal is disrupted;

with said storing step responsive thereto to repetitively output said repetition period of stored filtered samples as said synchronized signal during at least the pendency of said disruption.

29. The method of claim 24 further including

g) a second input processing step responsive to a second input signal to separate synchronizing components therefrom and to provide a second processed signal;

h) a second clock generating step for generating a second sampling clock;

i) a second sampling step operative to sample said second processed signal and provide samples thereof in response to said sampling clock;

j) a second interpolation step responsive to groups of said samples from h above to provide filtered samples;

k) a storing step to store said filtered samples from j) above to provide synchronization of said filtered samples from j) to said reference signal which reference signal may be a version of one of said input signal or said second input signal.

30. A method responsive to a plurality of input signals of an electronic type and having uncontrolled synchronization with respect to a reference signal, including for each said input signal the steps of:

a) for each said input signal providing synchronizing components related thereto;

b) providing a processed signal which is a version of said input signal;

c) for each said input signal generating a sampling clock;

d) sampling said processed signal and provide samples thereof in response to said sampling clock;

e) temporarily storing said samples to provide a synchronized signal which is synchronized in response to said reference signal.

31. The method of claim 30 further including:

the step of interpolating groups of said samples from step d) to provide filtered samples;

with said storing step e) responsive to said filtered samples in place of said samples from d) to provide synchronization of said filtered samples in response to said reference signal.

32. The method as claimed in claim 24, 25, 26, 27, 28, 29, or 30 wherein said interpolation operates in response to a first number of samples at a first resolution to provide a second improved number of filtered samples at a second resolution.

33. The method as claimed in claim 24, 25, 26, 27, 28, 29, 30 or 31 including a second storing step operative to store a secondary signal by a storage period corresponding to the storage time of said synchronized signal.

34. The method as claimed in claim 24, 25, 26, 27, 28, 29, 30 or 31 further including:

a reference signal detecting step to determine the presence of an external said reference signal;

a switching step responsive to said reference signal detecting step to select said input video signal for use as said reference signal when no external said reference signal is present.

35. The method as claimed in claim 24, 25, 26, 27, 28, 29, 30 or 31 further including:

a reference signal detecting step operative to determine the presence of an external said reference signal;

a switching step responsive to said reference signal detecting step and operative to select said input video signal for use as said reference signal when no external said reference signal is present with said method operating thereby as a fixed length delay;

a phase adjustment step responsive to said input video signal being used as said reference signal to provide an adjustable length of said fixed length delay.

36. The method as claimed in claim 24, 25, 26, 27, 28, 29, or 31 further including:

a digitizing step to digitize said samples of said processed signal;

said interpolation step operative to provide digital filtered samples having reduced quantizing error;

a image processing step responsive to said digital filtered samples in undelayed or relatively delayed form, or both, to improve the visual quality of the image represented by said digital filtered samples.

37. The method as claimed in claim 24, 25, 26, 27, 28, 29, 30 or 31 further including:

a step of video processing operative to select portions contained within the blanking areas of said synchronized video signal in order that said selected portions may be preserved and passed and further operating such that known ones of repetitive sync burst and blanking portions contained within the blanking areas of said synchronized signal are reconstructed and inserted in said synchronized signal.

Description Submit all comments and votes

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of synchronizing asynchronous signals and finds particular use in synchronizing video type signals in television systems.

2. Description of the Prior Art

The prior art contains many circuits for video synchronizers, beginning with U.S. Pat. No. 4,018,990. These synchronizers generally provide video synchronization by sampling and digitizing the active video portion of a video signal in response to the timing thereof, storing the digitized video in a memory, reading the digitized video from the memory at a proper time in response to a reference signal to achieve synchronization thereof, converting the read digitized video back to analog, and reconstructing and combining sync, burst and blanking with the read analog video.

Various techniques and circuits to perform these functions are well known in the art, and emphasis has been placed on improving performance in terms of minimizing noise and distortion from the digitizing process, and improving the immunity of the devices to noise which may be carried with or interfere with the signal which is being synchronized.

SUMMARY OF THE INVENTION

The inventive video synchronizer and improvements described herein are designed to allow synchronization of high quality video like signals while providing minimum distortion and maximum transparency. Because full sync tip to peak white video is digitized in the preferred embodiment shown herein, one would normally expect quantizing errors to be significant. The inventive features of the preferred embodiment however show the use of sophisticated digital signal processing techniques such as oversampling and interpolation, such that these errors are kept to unexpected low levels.

The inventive concepts described herein are applicable for many video signal standards, including but not limited to MONOCHROME, SECAM, PAL, NTSC and HDTV versions. The preferred embodiment is suitable to be constructed on a single small, low power PC board which because of small size and low power may be installed in various case configurations. It is also shown to pass one or more secondary signal with the video signal in a separate parallel but time related path.

The inventive concepts described herein are well suited for use in synchronizing satellite feeds, inter-suite connections and in house signals, thus eliminating the use of expensive and cumbersome multiple genlocking and timing schemes.

OBJECTS OF THE INVENTION INCLUDE:

An improved video synchronizer designed to allow synchronization of high quality video like signals while providing minimum distortion and maximum transparency.

A synchronizer which maintaining high signal quality at a reasonable price.

A synchronizer which digitizes full sync tip to peak white video with low quantizing error and distortion.

A digital signal device which makes use of oversampling and interpolation, such that sampling and quantizing errors are kept to unexpected low levels.

A video synchronizer which may be constructed on a single PC board and which may be installed in various case configurations.

A multiple signal synchronizer configuration in which a single genlock circuit may be utilized to provide reference signals for multiple synchronizers, but still retain individual genlock phase controls for each.

A signal synchronizer to use the input signal as the reference to allow the synchronizer to be used as an adjustable, fixed length delay, which use may be automatically switched.

A signal synchronizer capable of using recursive and nonrecursive adaptive filtering for noise reduction, image enhancement or other features.

A signal synchronizer capable of storing a full repetition period of the signal in memory.

A video signal synchronizer capable of digitizing and storing the entire video signal, including all sync, burst, horizontal blanking and vertical blanking so as to pass all signals encoded outside the active video area.

A video synchronizer capable of selecting ones of the signals contained within the blanking areas, so that those signals may be preserved and passed with only the repetitive sync burst and blanking reconstructed and reinserted in the stored signals from the memory.

A video signal processing device having a memory for storing the video signal and having a parallel storage path useful in video or television systems for the passing of one or more related or unrelated secondary signals with the video signal in order to maintain separate parallel but time related transmission paths for the secondary signals.

A synchronizer for video type signals in which reduction in size and power consumption is brought about by minimizing the electronic circuitry.

These and other objects of the invention will become apparent to one skilled in the art from the description herein, taken in conjunction with the attached drawings.

FIG. 1 shows a block diagram of the preferred embodiment of the invention, which diagram is applicable for the various video signal standards which the invention may be used with, including NTSC and PAL.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the preferred embodiment of the invention.

FIG. 2 is a top level schematic diagram of the remaining schematic diagrams of the preferred embodiment of the invention.

FIG. 3 is a first section schematic diagram of the Input video and A/D sections of the preferred embodiment of the invention.

FIG. 4 is a second section schematic diagram of the Input video and A/D sections of the preferred embodiment of the invention.

FIG. 5 is a third section schematic diagram of the Input video and A/D sections of the preferred embodiment of the invention.

FIG. 6 is a fourth section schematic diagram of the Input video and A/D sections of the preferred embodiment of the invention.

FIG. 7 is a first section schematic diagram of the Memory Timing and Control sections of the preferred embodiment of the invention.

FIG. 8 is a second section schematic diagram of the Memory Timing and Control sections of the preferred embodiment of the invention.

FIG. 9 is a third section schematic diagram of the Memory Timing and Control sections of the preferred embodiment of the invention.

FIG. 10 is a fourth section schematic diagram of the Memory Timing and Control sections of the preferred embodiment of the invention.

FIG. 11 is a first section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 12 is a second section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 13 is a third section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 14 is a fourth section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 15 is a fifth section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 16 is a sixth section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 17 is a seventh section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 18 is a eighth section schematic diagram of the Memory sections of the preferred embodiment of the invention.

FIG. 19 is a first section schematic diagram of the Digital Filter sections of the preferred embodiment of the invention.

FIG. 20 is a second section schematic diagram of the Digital Filter sections of the preferred embodiment of the invention.

FIG. 21 is a first section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 22 is a second section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the Invention.

FIG. 23 is a third section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 24 is a fourth section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 25 is a fifth section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 26 is a sixth section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 27 is a seventh section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 28 is a eighth section schematic diagram of the D/A and Output Video sections of the preferred embodiment of the invention.

FIG. 29 is a first mechanical diagram of a first mechanical embodiment of the invention showing a single electronic printed circuit board which embodies the electronics of the preferred embodiment housed in a single board case.

FIG. 30 is a second mechanical diagram of a second mechanical embodiment of the invention showing six electronic printed circuit boards which each of which embodies the electronics of the preferred embodiment housed in a six board case.

FIG. 31 is a third mechanical diagram of a third mechanical embodiment of the invention showing twelve electronic printed circuit boards each of which embodies the electronics of the preferred embodiment housed in a twelve board case.

FIG. 32 is a block diagram of a plurality of synchronizers which share a common output clock circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The preferred embodiment described herein is preferred for use with reference signals of a type similar to the common black burst signal. Alternatively, other signals may be utilized for reference, for example individual ones of clock, subcarrier, H and V sync and field one reference may be utilized in respect to the multiple synchronizer configuration described herein. In such multiple synchronizer configuration a single genlock circuit may be utilized to provide such reference signals for all of the multiple synchronizers being utilized, but still retaining individual phase controls for each. Such is very useful since it is a common requirement to synchronize several signals to a common reference, Unlike other synchronizers which switch to an independent internally generated reference in the event that an external reference signal is not supplied, the preferred embodiment of the present invention teaches to automatically switch to use the input video like signal as the reference. This novel feature allows the synchronizer to be used as an adjustable, fixed length delay, useful for a variety of timing and other purposes.

Novel digital signal processing techniques are also shown, such as video oversampling, recursive and nonrecursive adaptive noise reduction filtering. In the preferred embodiment, 10 bit oversampling with 12 bit processing and D-A conversion are used to maintain the utmost video signal integrity. A full 8 field video memory is shown for both PAL and NTSC, thus eliminating the need for chroma inverters and their inherent degradation of the signal.

The preferred embodiment of the invention makes use of video oversampling which is performed at 2560.times.f.sub.h (40.3 MHz in NTSC) in the A-D conversion to provide digitized samples of the video, followed by digital interpolation filtering of the digitized samples to provide filtered samples in order to completely eliminate the high frequency phase distortion normally found in analog anti alias filters. This frequency is much higher than the highest standard frequency in use which is four times subcarrier (14.3 MHz for NTSC). In addition, this technique considerably reduces the quantizing and other distortions which normally plague digital devices. While the use of oversampling to ease input anti alias filtering is known in the industry. It should be noted that it is believed that the use of oversampling and interpolation to an increased number of bits of resolution is believed to be a novel feature in view of the unexpected result of reducing distortions occurring in the sampling and A-D conversion process. Most pronounced of these reduced distortions is a better than theoretical quantizing noise performance. Such decrease in quantizing noise allows system performance to be greater than that of the A/D and D/A convertors (which seldom are perfect), and in fact greater that what is normally considered theoretically possible for the given resolution of the A-D convertor. In addition other benefits are had, such as reduced differential gain and phase as well as reduced harmonic and phase distortion are all achieved by oversampling and interpolation, all of which are often reduced to levels lower than those achieved by a given A-D convertor operating without such oversampling and interpolation.

In addition to the excellent video performance, the inventive concepts described herein with respect to the preferred embodiment show to sample, digitize and store the entire video signal, including all syncs, burst, horizontal blanking and vertical blanking. Such storage of the entire video signal is contrary to the established practice in the art, where only the active video portion of the signal is digitized and stored, and the repetitive sync, burst and blanking portions of the signal (which are mathematically defined and repetitive in nature) are reconstructed and added to the active video read from the memory. By digitizing and storing the full signal, all VITS (Vertical Interval Test Signals), VIRS (Vertical Interval Reference Signal), VITC (Vertical Interval Time Code), sound in sync and any other of the useful but nonrepetitive signals encoded outside the active video area may be preserved and passed. For the purpose of further explanation of the invention, these information containing signals which reside outside of active video area of the signal will be referred to as the nonrepetitive signals (although some are in fact repetitive), and the repetitive signals such as horizontal and vertical sync and blanking, and color burst will be referred to generally as syncs or synchronizing signals. It will be known to one skilled in the art from the teachings herein that select portions contained within the blanking areas of the stored video from the memory may be preserved and passed and known ones of the repetitive sync burst and blanking portions may be reconstructed and inserted in the synchronized video.

Although the continuous digitizing and storing of video type signals presents a number of particular technical challenges, the most critical being that there is no time to clear, reset or synchronize FIFO memories and DRAM memory address circuits, such problems are overcome by the present invention, which solutions will be apparent to one skilled in the art from the teachings herein.

The ability to pass VITC will be quite useful for inter suite use and the preservation of sound in sync will be especially useful for PAL applications where such signals are commonly used. Alternatively, if the user does not desire to maintain this information, or wishes to insert new information, full reinsertion of sync, blanking and burst may be selected. Alternatively, as will be apparent from the teachings herein, it will be shown to digitize only the active video, and selected ones of the nonrepetitive signals contained within the blanking areas, so that those signals may be preserved and passed and selected ones of the repetitive sync burst and blanking may be reconstructed and reinserted in the stored signals from the memory. Furthermore, in the preferred embodiment a full repetition period of memory is used, for example 8 fields for PAL, thus there is no chance of upsetting the proper chroma subcarrier sequence in either PAL or NTSC and the need for chroma inverters or other chroma phase correction schemes is eliminated.

With the widespread use of digital video processing, audio synchronization is becoming a significant problem. The preferred embodiment shows inventive concepts which incorporate a digital delay output (DDO) which provides a steering signal to drive a companion audio synchronizer such as those described in U.S. Pat. Nos. 4,313,135 and 5,202,761, thus guaranteeing accurate audio to video synchronization.

The preferred embodiment described herein is shown schematically in FIGS. 2-28 and may be constructed with commonly available parts whose generic or manufacturers part numbers are given. While the part numbers for the ICs are commonly known, in the event that one does not immediately recognize the manufacturer, the IC Master may be consulted to locate the manufacturer from the part number prefix which is given. The preferred embodiment constructed according to the teaching herein meets the following technical description and is capable of meeting the following specifications with components which are commonly available. These specifications are common to both PAL and NTSC versions and where applicable will apply for other systems as well.

The preferred embodiment may be constructed on a single PC board suitable for mounting in a variety of case configurations, including a single board desk top version, a 6 board rack mount version, and a 12 board rack mount version. The 6 and 12 board versions may mix boards operating on various signal standards, for example NTSC and PAL boards. Schematic diagrams are shown in FIGS. 2-28 which have been constructed and tested to meet the following specifications and performance levels:

______________________________________ Sampling Rate 2560 .times. f.sub.h, 40.3 MHz NTSC, 40.0 MHz PAL Input 10 Bits Quantizing Digital 2.fwdarw.1 decimation with 10.fwdarw.12 bit interpolation Filtering nonrecursive adaptive interpolation filtering digital anti-alias filtering optional adaptive recursive noise reduction optional digital temporal integration Memory 12 Bit video, including full storage of H and V blanking interval. Bandwidth .+-. 1% to 8 MHz Thru Gain Unity .+-. 1% S/N 60 dB unweighted over 10 Mhz bandwidth Chroma/Luma <1% gain error Chroma/Luma <5 ns timing error Chroma/Luma <0.5% intermodulation Differential <1% Gain Differential <1.degree. Phase K Factor <0.5% (2T pulse) 2T Pulse to <1% Bar Error ratio Short Time <1% Distortion Line Time <0.25% Distortion Field Time <0.25% Distortion Input/Output -60 dB to 8 Mhz Crosstalk PROCESSING AMPLIFIER control selectable pass incoming blanking interval or insert new sync, burst and blanking. Inserted sync edges and burst envelope are sine.sup.2 shaped. Sync and burst amplitude are adjustable. GENLOCK H .phi. adjust .+-. 3 .mu.s (output H to reference H) V .phi. adjust 3 H advance to 1H delay (output V to reference V) Burst .phi. 360.degree. (Inserted burst to reference burst) adjust VIDEO PROC Video setup .+-. 10 IRE (operative with inserted sync) Video gain .+-. 20 IRE H .phi. adjust .+-. 3 .mu.s (active video to inserted sync) Hue .phi. .+-. 20.degree. (active video to inserted burst) adjust INPUTS Video in (differential looping) Reference (differential looping) OUTPUTS Video 1 Video 2 / DDO (strap selectable) FRONT PANEL CONTROLS and ADJUSTMENTS Output Gain Output Hue Input Setup Input Gain Input 75.OMEGA. term Hue Digital Filter Select Genlock Burst .phi. Genlock V.phi. Genlock H.phi. POWER 110/120 or 220/240 volt strap selectable 50/60 Hz 32 Watts Max. 27 Watts typical ENVIRONMENTAL Temperature Operating: 0.degree. C. to +45.degree. C. Storage: -55.degree. C. to +75.degree. C. Humidity: 10-95%, non condensing TYPICAL MOUNTING CASE SIZES FOR PREFERRED EMBODIMENT Single board 1.75"H .times. 8.75"W .times. 17"D case Six Board case 3.5"H .times. 19"W .times. 18.5"D 19" rack mount Twelve Board 7"H .times. 19"W .times. 18.5"D case 19" rack mount ______________________________________

The diagram of FIG. 1 shows a video input terminal which is preferred to be of the high impedance looping type, which input is coupled to a processing section 1. The processing section operates to DC restore the video, remove common