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Claims  |
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We claim:
1. The linear feedback shift register comprising cascaded input
boundary-scan cells of an IEEE std. 1149.1 boundary scan circuit, said
input boundary-scan cells forming an input boundary-scan register that is
adapted to be connected to input nodes of a logic circuit of the boundary
scan circuit, said input boundary-scan register being reconfigurable to
operate as a test pattern generator that is adapted to provide test
patterns to the logic circuit for a predetermined number of clock cycles
upon receipt of a built-in self-test control signal from a test access
port system of the boundary scan circuit, wherein:
each of said input boundary-scan cells is one of a first cell, a second
cell and a third cell;
said first cell includes: a four-channel first multiplexer having a first
data input which serves as a signal input, a second data input which
serves as a feedback input, third and fourth data inputs which are
connected to one another and which serve as a scan input, a pair of
channel select inputs which are adapted to receive a first control signal
(BIST*) and a second control signal (ShiftDR) respectively, and an output;
a D-type flip-flop having a data input connected to said output of said
first multiplexer, a clock input adapted to receive a clock signal
(mClockDR), and an output which serves as a scan output; and a two-channel
second multiplexer having a first data input which is connected to said
first data input of said first multiplexer, a second data input which is
connected to said output of said flip-flop, a channel select input which
is adapted to receive a third control signal (Mode), and an output which
serves as a signal output;
said second cell includes: a four-channel first multiplexer having a first
data input which serves as a signal input, second, third and fourth data
inputs which are connected to one another and which serve as a scan input,
a pair of channel select inputs which are adapted to receive said first
control signal (BIST*) and said second control signal (ShiftDR)
respectively, and an output; a D-type flip-flop having a data input
connected to said output of said first multiplexer, a clock input which is
adapted to receive said clock signal (mClockDR), and an output which
serves as a scan output; and a two-channel second multiplexer having a
first data input which is connected to said first data input of said first
multiplexer, a second data input which is connected to said output of said
flip-flop, a channel select input which is adapted to receive said third
control signal (Mode), and an output which serves as a signal output; and
said third cell includes: a two-input XOR gate having a first input which
serves as a feedback input, a second input which serves as a scan input,
and an output; a four-channel first multiplexer having a first data input
which serves a signal input, a second data input which is connected to
said output of said XOR gate, third and fourth data inputs which are
connected to one another and which are further connected to said second
input of said XOR gate, a pair of channel select inputs which are adapted
to receive said first control signal (BIST*) and said second control
signal (ShiftDR) respectively, and an output; a D-type flip-flop having a
data input connected to said output of said first multiplexer, a clock
input which is adapted to receive said clock signal (mClockDR), and an
output which serves as a scan output; and a two-channel second multiplexer
having a first data input which is connected to said first data input of
said first multiplexer, a second data input which is connected to said
output of said flip-flop, a channel select input which is adapted to
receive said third control signal (Mode), and an output which serves as a
signal output.
2. The linear feedback shift register according to claim 1, wherein:
said linear feedback shift register has a characteristic polynomial
p(x)=1+c.sub.1 x+c.sub.2 x.sup.2 +. . . +c.sub.n x.sup.n ;
a first one of said input boundary-scan cells is said first cell and
corresponds to a coefficient c.sub.0 of the characteristic polynomial; and
a succeeding one of said input boundary-scan cells is said second cell if a
coefficient c.sub.i of the characteristic polynomial is zero for
1.ltoreq.i.ltoreq.n-1, and is said third cell if the coefficient c.sub.i
of the characteristic polynomial is one for 1.ltoreq.i.ltoreq.n-1.
3. The linear feedback shift register according to claim 2, wherein a
previous one of said input boundary-scan cells corresponding to the
coefficient c.sub.i-1 of the characteristic polynomial is connected to a
succeeding one of said input boundary-scan cells corresponding to the
coefficient c.sub.i of the characteristic polynomial by connecting said
scan output of said previous one to said scan input of said succeeding
one, said feedback inputs of said first and third cells being connected to
said scan output of a final one of said input boundary-scan cells
corresponding to the coefficient c.sub.n-1 of the characteristic
polynomial.
4. A multiple-input shift register, comprising cascaded output
boundary-scan cells of an IEEE Std. 1149.1 boundary scan circuit, said
output boundary-scan cells forming an output boundary-scan register that
is adapted to be connected to output nodes of a logic circuit of the
boundary scan circuit, said output boundary-scan register being
reconfigurable to operate as an output response analyzer driven by the
logic circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of the
boundary scan circuit, contents of said output boundary-scan register
being scannable for comparison with a predetermined signature to detect
presence of a fault after said predetermined number of clock cycles.
5. The multiple-input shift register according to claim 4, wherein:
each of said output boundary-scan cells is one of a first cell, a second
cell and a third cell;
said first cell includes: a two-input XOR gate having a first input which
serves as a signal input, a second input which serves as a feedback input,
and an output; a four-channel first multiplexer having a first data input
which is connected to said first input of said XOR gate, a second data
input which is connected to said output of said XOR gate, third and fourth
data inputs which are connected to one another and which serve as scan
inputs, a pair of channel select inputs which are adapted to receive a
first control signal (BIST*) and a second control signal (ShiftDR)
respectively, and an output; a D-type first flip-flop having a data input
connected to said output of said first multiplexer, a clock input adapted
to receive a first clock signal (mClockDR), and an output which serves as
a scan output; a D-type second flip-flop having a data input connected to
said output of said first flip-flop, a clock input adapted to receive a
second clock signal (UpdateDR), and an output; and a two-channel second
multiplexer having a first data input which is connected to said first
input of said XOR gate, a second data input which is connected to said
output of said second flip-flop, a channel select input which is adapted
to receive a third control signal (Mode), and an output which serves as a
signal output;
said second cell includes: a two-input XOR gate having a first input which
serves as a signal input, a second input which serves as a scan input, and
an output; a four-channel first multiplexer having a first data input
which is connected to said first input of said XOR gate, a second data
input which is connected to said output of said XOR gate, third and fourth
data inputs which are connected to one another and which are further
connected to said second input of said XOR gate, a pair of channel select
inputs which are adapted to receive said first control signal (BIST*) and
said second control signal (ShiftDR) respectively, and an output; a D-type
first flip-flop having a data input connected to said output of said first
multiplexer, a clock input adapted to receive said first clock signal
(mClockDR), and an output which serves as a scan output; a D-type second
flip-flop having a data input connected to said output of said first
flip-flop, a clock input adapted to receive said second clock signal
(UpdateDR), and an output; and a two-channel multiplexer having a first
data input which is connected to said first input of said XOR gate, a
second data input which is connected to said output of said second
flip-flop, a channel select input which is adapted to receive said third
control signal (Mode), and an output which serves as a signal output; and
said third cell includes: a two-input first XOR gate having a first input
which serves as a signal input, a second input which serves as a scan
input, and an output; a two-input second XOR gate having a first input
which is connected to said output of said first XOR gate, a second input
which serves as a feedback input, and an output; a four-channel first
multiplexer having a first data input which is connected to said first
input of said first XOR gate, a second data input which is connected to
said output of said second XOR gate, third and fourth data inputs which
are connected to one another and which are further connected to said
second input of said first XOR gate, a pair of channel select inputs which
are adapted to receive said first control signal (BIST*) and said second
control signal (ShiftDR) respectively, and an output; a D-type first
flip-flop having a data input connected to said output of said first
multiplexer, a clock input adapted to receive said first clock signal
(mClockDR), and an output which serves as a scan output; a D-type second
flip-flop having a data input connected to said output of said first
flip-flop, a clock input adapted to receive said second clock signal
(UpdateDR), and an output; and a two-channel second multiplexer having a
first data input which is connected to said first input of said first XOR
gate, a second data input which is connected to said output of said second
flip-flop, a channel select input which is adapted to receive said third
control signal (Mode), and an output which serves as a signal output.
6. The multiple-input shift register according to claim 5, wherein:
said multiple-input shift register has a characteristic polynomial
p(x)=1+c.sub.1 x+c.sub.2 x.sup.2 +. . . +c.sub.n x.sup.n ;
a first one of said output boundary-scan cells is said first cell and
corresponds to a coefficient c.sub.0 of the characteristic polynomial; and
a succeeding one of said output boundary-scan cells is said second cell if
a coefficient c.sub.i of the characteristic polynomial is zero for
1.ltoreq.i.ltoreq.n-1, and is said third cell if the coefficient c.sub.i
of the characteristic polynomial is one for 1.ltoreq.i.ltoreq.n-1.
7. The multiple-input shift register according to claim 6, wherein a
previous one of said output boundary-scan cells corresponding to the
coefficient c.sub.i-1 of the characteristic polynomial is connected to a
succeeding one of said output boundary-scan cells corresponding to the
coefficient c.sub.i of the characteristic polynomial by connecting said
scan output of said previous one to said scan input of said succeeding
one, said feedback inputs of said first and third cells being connected to
said scan output of a final one of said output boundary-scan cells
corresponding to the coefficient c.sub.n-1 of the characteristic
polynomial.
8. An input boundary-scan cell for an IEEE Std. 1149.1 boundary scan
circuit, said input boundary-scan cell forming a part of an input
boundary-scan register that is connected to input nodes of a logic circuit
of said boundary scan circuit and that is reconfigurable so as to operate
as a test pattern generator which provides test patterns to said logic
circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of said
boundary scan circuit when executing built-in self-testing, said input
boundary-scan cell comprising:
a four-channel first multiplexer having a first data input which serves as
a signal input, a second data input which serves as a feedback input,
third and fourth data inputs which are connected to one another and which
serve as a scan input, a pair of channel select inputs which are adapted
to receive a first control signal (BIST*) and a second control signal
(ShiftDR) respectively, and an output;
a D-type flip-flop having a data input connected to said output of said
first multiplexer, a clock input adapted to receive a clock signal
(mClockDR), and an output which serves as a scan output; and
a two-channel second multiplexer having a first data input which is
connected to said first data input of said first multiplexer, a second
data input which is connected to said output of said flip-flop, a channel
select input which is adapted to receive a third control signal (Mode),
and an output which serves as a signal output.
9. An input boundary-scan cell for an IEEE Std. 1149.1 boundary scan
circuit, said input boundary-scan cell forming a part of an input
boundary-scan register that is connected to input nodes of a logic circuit
of said boundary scan circuit and that is reconfigurable so as to operate
as a test pattern generator which provides test patterns to said logic
circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of said
boundary scan circuit when executing built-in self-testing, said input
boundary-scan cell comprising:
a four-channel first multiplexer having a first data input which serves as
a signal input, second, third and fourth data inputs which are connected
to one another and which serve as a scan input, a pair of channel select
inputs which are adapted to receive a first control signal (BIST*) and a
second control signal (ShiftDR) respectively, and an output;
a D-type flip-flop having a data input connected to said output of said
first multiplexer, a clock input which is adapted to receive a clock
signal (mClockDR), and an output which serves as a scan output; and
a two-channel second multiplexer having a first data input which is
connected to said first data input of said first multiplexer, a second
data input which is connected to said output of said flip-flop, a channel
select input which is adapted to receive a third control signal (Mode),
and an output which serves as a signal output.
10. An input boundary-scan cell for an IEEE Std. 1149.1 boundary scan
circuit, said input boundary-scan cell forming a part of an input
boundary-scan register that is connected to input nodes of a logic circuit
of said boundary scan circuit and that is reconfigurable so as to operate
as a test pattern generator which provides test patterns to said logic
circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of said
boundary scan circuit when executing built-in self-testing, said input
boundary-scan cell comprising:
a two-input XOR gate having a first input which serves as a feedback input,
a second input which serves as a scan input, and an output;
a four-channel first multiplexer having a first data input which serves as
a signal input, a second data input which is connected to said output of
said XOR gate, third and fourth data inputs which are connected to one
another and which are further connected to said second input of said XOR
gate, a pair of channel select inputs which are adapted to receive a first
control signal (BIST*) and a second control signal (ShiftDR) respectively,
and an output;
a D-type flip-flop having a data input connected to said output of said
first multiplexer, a clock input which is adapted to receive a clock
signal (mClockDR), and an output which serves as a scan output; and
a two-channel second multiplexer having a first data input which is
connected to said first data input of said first multiplexer, a second
data input which is connected to said output of said flip-flop, a channel
select input which is adapted to receive a third control signal (Mode),
and an output which serves as a signal output.
11. An output boundary-scan cell for an IEEE Std. 1149.1 boundary scan
circuit, said output boundary-scan cell forming a part of an output
boundary-scan register that is connected to output nodes of a logic
circuit of said boundary scan circuit and that is reconfigurable so as to
operate as an output response analyzer which is driven by said logic
circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of said
boundary scan circuit when executing built-in self-testing, said output
boundary-scan cell comprising:
a two-input XOR gate having a first input which serves as a signal input, a
second input which serves as a feedback input, and an output;
a four-channel first multiplexer having a first data input which is
connected to said first input of said XOR gate, a second data input which
is connected to said output of said XOR gate, third and fourth data inputs
which are connected to one another and which serve as scan inputs, a pair
of channel select inputs which are adapted to receive a first control
signal (BIST*) and a second control signal (ShiftDR) respectively, and an
output;
a D-type first flip-flop having a data input connected to said output of
said first multiplexer, a clock input adapted to receive a first clock
signal (mClockDR), and an output which serves as a scan output;
a D-type second flip-flop having a data input connected to said output of
said first flip-flop, a clock input adapted to receive a second clock
signal (UpdateDR), and an output; and
a two-channel second multiplexer having a first data input which is
connected to said first input of said XOR gate, a second data input which
is connected to said output of said second flip-flop, a channel select
input which is adapted to receive a third control signal (Mode), and an
output which serves as a signal output.
12. An output boundary-scan cell for an IEEE Std. 1149.1 boundary scan
circuit, said output boundary-scan cell forming a part of an output
boundary-scan register that is connected to output nodes of a logic
circuit of said boundary scan circuit and that is reconfigurable so as to
operate as an output response analyzer which is driven by said logic
circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of said
boundary scan circuit when executing built-in self-testing, said output
boundary-scan cell comprising:
a two-input XOR gate having a first input which serves as a signal input, a
second input which serves as a scan input, and an output;
a four-channel first multiplexer having a first data input which is
connected to said first input of said XOR gate, a second data input which
is connected to said output of said XOR gate, third and fourth data inputs
which are connected to one another and which are further connected to said
second input of said XOR gate, a pair of channel select inputs which are
adapted to receive a first control signal (BIST*) and a second control
signal (ShiftDR) respectively, and an output;
a D-type first flip-flop having a data input connected to said output of
said first multiplexer, a clock input adapted to receive a first clock
signal (mClockDR), and an output which serves as a scan output;
a D-type second flip-flop having a data input connected to said output of
said first flip-flop, a clock input adapted to receive a second clock
signal (UpdateDR), and an output; and
a two-channel second multiplexer having a first data input which is
connected to said first input of said XOR gate, a second data input which
is connected to said output of said second flip-flop, a channel select
input which is adapted to receive a third control signal (Mode), and an
output which serves as a signal output.
13. An output boundary-scan cell for an IEEE Std. 1149.1 boundary scan
circuit, said output boundary-scan cell forming a part of an output
boundary-scan register that is connected to output nodes of a logic
circuit of said boundary scan circuit and that is reconfigurable so as to
operate as an output response analyzer which is driven by said logic
circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of said
boundary scan circuit when executing built-in self-testing, said output
boundary-scan cell comprising:
a two-input first XOR gate having a first input which serves as a signal
input, a second input which serves as a scan input, and an output;
a two-input second XOR gate having a first input which is connected to said
output of said first XOR gate, a second input which serves as a feedback
input, and an output;
a four-channel first multiplexer having a first data input which is
connected to said first input of said first XOR gate, a second data input
which is connected to said output of said second XOR gate, third and
fourth data inputs which are connected to one another and which are
further connected to said second input of said first XOR gate, a pair of
channel select inputs which are adapted to receive a first control signal
(BIST*) and a second control signal (ShiftDR) respectively, and an output;
a D-type first flip-flop having a data input connected to said output of
said first multiplexer, a clock input adapted to receive a first clock
signal (mClockDR), and an output which serves as a scan output;
a D-type second flip-flop having a data input connected to said output of
said first flip-flop, a clock input adapted to receive a second clock
signal (UpdateDR), and an output; and
a two-channel second multiplexer having a first data input which is
connected to said first input of said first XOR gate, a second data input
which is connected to said output of said second flip-flop, a channel
select input which is adapted to receive a third control signal (Mode),
and an output which serves as a signal output. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a boundary scan circuit and to a testing method
performed thereby, more particularly to a built-in self-testing method for
an IEEE Std. 1149.1 boundary scan circuit and to an IEEE Std. 1149.1
boundary scan circuit with a built-in self-testing capability.
2. Description of the Related Art
Built-in self-test (BIST), which is defined as the testing of an integrated
circuit through built-in hardware features, is a testing method which can
overcome testing problems usually encountered when conducting tests for
complex VLSI circuits. Chip level BIST architecture involves: a test
pattern generator, such as a linear feedback shift register (LFSR),
connected to input nodes of an application logic; an output response
analyzer, such as a multiple input signature register (MISR), connected to
output nodes of the application logic; and a test controller for
controlling operation of the test pattern generator and the output
response analyzer.
LFSRs are well studied and widely used in VLSI circuitry because they are
simple and fairly regular in structure, which are important for VLSI
implementation. They are also used extensively in design for testability
(DFT) techniques because their shift property integrates easily with
serial scan. Their good performance in pseudo-exhaustive and pseudo-random
pattern generation, and their ability to compress the circuit output
response also make them popular in BIST environments. FIGS. 1 and 2
respectively show the circuit designs of an LFSR and an MISR having the
characteristic polynomial p(x)=1+c.sub.1 x+c.sub.2 x.sup.2 +. . . +c.sub.n
x.sup.n.
Since BIST permits execution of the testing operation at the speed of the
system clock, testing can be performed at a much shorter time than other
known testing techniques. In addition, BIST does not require the use of an
Automatic Test Equipment (ATE). However, the silicon area must be
increased to accommodate the test pattern generator, the output response
analyzer and the test controller. This results in a lower chip yield and
in higher manufacturing costs.
Recent advancements in the field of electronics manufacturing, such as
surface mount technology (SMT) and multi-chip module (MCM), have caused
numerous testing problems at the board level. The IEEE has issued a
boundary scan standard (IEEE Std. 1149.1) to help alleviate the problem of
testing connections at this level.
IEEE Std. 1149.1 provides a framework for reducing the test costs at board
level by reusing pre-existing test patterns to a component on a board
regardless of how pins of the component are interconnected. FIG. 3
illustrates a boundary scannable board design. A boundary-scan cell is
provided adjacent to each component pin so that signals at component
boundaries can be controlled and observed to determine whether a short
circuit or open circuit condition has occurred on the board, and to detect
the presence of a fault in an integrated circuit on a circuit board. Also,
in-circuit testing is achieved by mere use of a special instruction to
shift the pre-existing test patterns to the chip boundary, thereby
simplifying testing at the board level. Moreover, the input and output
boundary-scan cells, which cooperate to form input and output
boundary-scan registers, can facilitate design debugging and fault
diagnosis since the boundary-scan registers can be used to sample data
flowing through the component without interfering with normal operation of
the latter.
Referring to FIG. 4, a conventional boundary-scan cell of an IEEE Std.
1149.1 boundary scan circuit is shown to comprise a two-channel first
multiplexer 11, a D-type first flip-flop 12, a D-type second flip-flop 13,
and a two-channel second multiplexer 14. The first multiplexer 11 has a
first data input which serves as a signal input, a second data input which
serves as a scan input, a channel select input which receives a first
control signal ShiftDR, and an output. The first flip-flop 12 has a data
input connected to the output of the first multiplexer 11, a clock input
for receiving a first clock signal ClockDR, and an output which serves as
a scan output. The second flip-flop 13 has a data input connected to the
output of the first flip-flop 12, a clock input for receiving a second
clock signal UpdateDR, and an output. The second multiplexer 14 has a
first data input which serves as a signal input, a second data input which
is connected to the output of the second flip-flop 13, a channel select
input which receives a second control signal Mode, and an output which
serves as a signal output.
Referring to FIG. 5, the boundary scan test circuitry includes a test
access port (TAP) system. Testing is performed by shifting test
instructions and test data into the boundary-scan component via the TAP
system. The TAP system is a 16-state system and has several input ports
and one output port. These ports include: Test Data In (TDI) which
provides serial inputs for test instructions shifted into the instruction
register and for data shifted through the boundary-scan register or other
test data registers; Test Data Out (TDO) which is the serial output for
test instructions and data from the test data registers; Test Clock (TCK)
which provides the clock for the test logic and which is a dedicated input
that allows the serial test data path to be used independent of
component-specific system clocks and that permits shifting of test data
concurrently with normal component operation; Test Mode Select (TMS) which
cooperates with TCK to cause operation of the TAP system from one state to
another; and Test Reset (TRST*) which is an active-low input signal that
provides asynchronous initialization of the TAP system.
Boundary scan test functions are accomplished via various test instructions
which are defined by IEEE Std. 1149.1. Three of these test instructions,
EXTEST, SAMPLE/PRELOAD and BYPASS, are mandatory for every boundary-scan
device.
The EXTEST instruction is concerned primarily with testing of circuitry
external to the device using the boundary-scan register of the device. A
test vector is pre-loaded into the boundary-scan register, and the EXTEST
instruction is used to drive the test vector to the external circuitry.
When the EXTEST instruction is used to test the interconnection line, a
test pattern is pre-loaded into the output boundary-scan register of one
device and is then propagated to the next device. The response is latched
on the input cells and is shifted to the TDO for examination. The EXTEST
instruction also permits cluster testing, wherein components that do not
incorporate boundary scan technology are tested. In cluster testing, data
is shifted to the cluster/device input cells. Outputs from the cluster are
captured by the input cells of a second boundary-scan device. The captured
data is then shifted out of the second boundary-scan device for
examination.
The BYPASS instruction allows the TDO buffer to generate the same bit
stream as TDI. This is done by placing a single shift-register, called the
bypass register, between TDI and TDO. When one does not wish to test a
particular component, but the test data sequence must shift through that
component to test another device, the BYPASS instruction is issued to that
particular component to bypass the test data sequence.
The SAMPLE/PRELOAD instruction permits the execution of two functions: it
allows sampling of normal operation data at the periphery of a component,
and placing of an initial data pattern at latched parallel outputs of the
boundary-scan cells. This instruction is used to load data onto the
latched outputs prior to selection of another test instruction, such as
the EXTEST instruction.
As with BIST, boundary scan technology requires an increase in the silicon
area to accommodate the TAP system and the input and output boundary-scan
registers.
The general acceptance of boundary scan by the designer and the Automatic
Test Equipment (ATE) community makes boundary scan an effective test
strategy. The incorporation of BIST with the boundary scan registers and
the TAP controller provides a flexible framework at all levels of
testing--chip level, board level and system level.
Although the use of BIST in a boundary scan environment has been proposed
beforehand, the traditional approach is to provide separate hardware for
performing BIST and boundary scan test. This increases the hardware
overhead incurred.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a built-in self-testing
method for an IEEE Std. 1149.1 boundary scan circuit which involves
sharing of flip-flops and controllers between BIST and boundary scan
testing so that no substantial increase in the hardware overhead is
incurred.
A second object of the present invention is to provide an IEEE Std. 1149.1
boundary scan circuit with a built-in self-testing capability which
incorporates boundary-scan cells that are operable so as to perform both
BIST and boundary scan test.
A third object of the present invention is to provide a test pattern
generator, such as a linear feedback shift register, which utilizes input
boundary-output boundary-scan cells when executing built-in self-testing;
reconfiguring the input boundary-scan register to operate as a test pattern
generator that provides test patterns to the logic circuit for a
predetermined number of clock cycles upon receipt of the built-in
self-test control signal;
reconfiguring the output boundary-scan register to operate as an output
response analyzer that is driven by the logic circuit for the
predetermined number of clock cycles upon receipt of the built-in
self-test control signal; and
scanning contents of the output boundary-scan register and comparing the
contents of the output boundary-scan register with a predetermined
signature to detect presence of a fault after the predetermined number of
clock cycles.
According to another aspect of the present invention, an IEEE Std. 1149.1
boundary scan circuit capable of performing built-in self-testing includes
a logic circuit, cascaded input boundary-scan cells that form an input
boundary-scan register connected to input nodes of the logic circuit,
cascaded output boundary-scan cells that form an output boundary-scan
register connected to output nodes of the logic circuit, and a test access
port system for controlling operation of the input and output
boundary-scan cells. The test scan cells of an IEEE Std. 1149.1 boundary
scan circuit to provide test patterns to a logic circuit when executing
BIST.
A fourth object of the present invention is to provide an output response
analyzer, such as a multiple-input shift register, which utilizes output
boundary-scan cells of an IEEE Std. 1149.1 boundary scan circuit that are
driven by a logic circuit when executing BIST.
A fifth object of the present invention is to provide a family of input and
output boundary-scan cells for an IEEE Std. 1149.1 boundary scan circuit
that can be reconfigured to operate as a test pattern generator or as an
output response analyzer when executing BIST.
According to one aspect of the present invention, a built-in self-testing
method for an IEEE Std. 1149.1 boundary scan circuit which includes a
logic circuit, cascaded input boundary-scan cells that form an input
boundary-scan register connected to input nodes of the logic circuit,
cascaded output boundary-scan cells that form an output boundary-scan
register connected to output nodes of the logic circuit, and a test access
port system for controlling operation of the input and output
boundary-scan cells, comprises the steps of:
controlling the test access port system to provide a built-in self-test
control signal to the input and access port system includes controllable
means for providing a built-in self-test control signal to the input and
output boundary-scan cells when executing built-in self-testing, in
addition to the original test access port defined by IEEE Std.
1149.1--1990. The input boundary-scan register is reconfigurable to
operate as a test pattern generator that provides test patterns to the
logic circuit for a predetermined number of clock cycles upon receipt of
the built-in self-test control signal, and the output boundary-scan
register is reconfigurable to operate as an output response analyzer that
is driven by the logic circuit for the predetermined number of clock
cycles upon receipt of the built-in self-test control signal. Contents of
the output boundary-scan register are scannable for comparison with a
predetermined signature to detect presence of a fault after the
predetermined number of clock cycles.
The test access port system operates in a Run-Test/Idle mode when built-in
self-testing is executed. The boundary scan circuit further comprises
means for providing a system clock to the input and output boundary-scan
cells when built-in self-testing is executed.
According to still another aspect of the present invention, a linear
feedback shift register, which acts as a test pattern generator, comprises
cascaded input boundary-scan cells of an IEEE Std. 1149.1 boundary scan
circuit. The input boundary-scan cells form an input boundary-scan
register that is adapted to be connected to input nodes of a logic circuit
of the boundary scan circuit. The input boundary-scan register is
reconfigurable to operate as a test pattern generator that is adapted to
provide test patterns to the logic circuit for a predetermined number of
clock cycles upon receipt of a built-in self-test control signal from a
test access port system of the boundary scan circuit.
According to a further aspect of the present invention, a multiple-input
shift register, which acts as an output response analyzer, comprises
cascaded output boundary-scan cells of an IEEE Std. 1149.1 boundary scan
circuit. The output boundary-scan cells form an output boundary-scan
register that is adapted to be connected to output nodes of a logic
circuit of the boundary scan circuit. The output boundary-scan register is
reconfigurable to operate as an output response analyzer driven by the
logic circuit for a predetermined number of clock cycles upon receipt of a
built-in self-test control signal from a test access port system of the
boundary scan circuit. Contents of the output boundary-scan register are
scannable for comparison with a predetermined signature to detect presence
of a fault after the predetermined number of clock cycles.
Since no separate test pattern generator, output response analyzer and BIST
controller is required in the BIST boundary scan circuitry of this
invention, no substantial increase in the overall hardware overhead is
incurred.
BRIEF DESCRIPTION OF THE DRAWINGS
Other features and advantages of the present invention will become apparent
in the following detailed description of the preferred embodiment with
reference to the accompanying drawings, of which:
FIG. 1 is a block diagram of a conventional linear feedback shift register
(LFSR);
FIG. 2 is a block diagram of a conventional multiple-input shift register
(MISR);
FIG. 3 illustrates a conventional boundary scannable board design;
FIG. 4 is a schematic circuit diagram of a conventional boundary-scan cell;
FIG. 5 is a circuit block diagram of a conventional boundary-scan device;
FIG. 6 is a schematic circuit diagram of a first input boundary-scan cell
according to the present invention;
FIG. 7 is a schematic circuit diagram of a second input boundary-scan cell
according to the present invention;
FIG. 8 is a schematic circuit diagram of a third input boundary-scan cell
according to the present invention;
FIG. 9 illustrates how the family of input boundary-scan cells shown in
FIGS. 6 to 8 are combined to form an LFSR with a characteristic polynomial
p(x)=x.sup.4 +x.sup.3 +1;
FIG. 10 is a schematic circuit diagram of a first output boundary-scan cell
according to the present invention;
FIG. 11 is a schematic circuit diagram of a second output boundary-scan
cell according to the present invention;
FIG. 12 is a schematic circuit diagram of a third output boundary-scan cell
according to the present invention;
FIG. 13 illustrates how the family of output boundary-scan cells shown in
FIGS. 10 to 12 are combined to form an MISR with a characteristic
polynomial p(x)=x.sup.4 +x.sup.3 +1;
FIG. 14 illustrates the architecture of an instruction register and decoder
for generating the various control signals for the boundary-scan cells of
this invention;
FIG. 15 is a table which shows the codes assigned to the different test
instructions to be loaded into the instruction register, and the logic
values of the different control signals in accordance with the test
instructions;
FIG. 16 is a schematic circuit diagram of an instruction decoder which
complies with the table shown in FIG. 15;
FIG. 17 is a schematic circuit diagram of a logic circuit for providing a
system clock to the boundary-scan cells during a Run-Test/Idle controller
state of the test access port (TAP) system; and
FIG. 18 is a sample logic circuit which incorporates the BIST boundary scan
circuit of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In the boundary scan circuit of the present invention, the input
boundary-scan register should be reconfigurable as a pseudo-random pattern
generator (PRPG), while the output boundary-scan register should be
reconfigurable as a signature analyzer (SA) to incorporate the BIST
capability in the boundary scan environment. To achieve this purpose, a
family of boundary-scan cells which can be reconfigured as a linear
feedback shift register (LFSR) or as a multiple-input shift register
(MISR) is disclosed.
FIGS. 6 to 8 illustrate three input boundary-scan cells 20, 30, 40 which
can be combined to form an LFSR.
Referring to FIG. 6, the input boundary-scan cell 20 comprises a
four-channel first multiplexer 21, a D-type flip-flop 22, and a
two-channel second multiplexer 23. The first multiplexer 21 has a first
data input which serves as a signal input, a second data input which
serves as a feedback input fb, third and fourth data inputs which are
connected to one another and which serve as a scan input, a pair of
channel select inputs which receive a first control signal BIST* and a
second control signal ShiftDR respectively, and an output. The flip-flop
22 has a data input connected to the output of the first multiplexer 21, a
clock input for receiving a clock signal mClockDR, and an output which
serves as a scan output. The second multiplexer 23 has a first data input
which is connected to the first data input of the first multiplexer 21, a
second data input which is connected to the output of the flip-flop 22, a
channel select input which receives a third control signal Mode, and an
output which serves as a signal output.
Referring to FIG. 7, the input boundary-scan cell 30 comprises a
four-channel first multiplexer 31, a D-type flip-flop 32, and a
two-channel second multiplexer 33. The first multiplexer 31 has a first
data input which serves as a signal input, second, third and fourth data
inputs which are connected to one another and which serve as a scan input,
a pair of channel select inputs which receive the first control signal
BIST* and the second control signal ShiftDR respectively, and an output.
The flip-flop 32 has a data input connected to the output of the first
multiplexer 31, a clock input for receiving the clock signal mClockDR, and
an output which serves as a scan output. The second multiplexer 33 has a
first data input which is connected to the first data input of the first
multiplexer 31, a second data input which is connected to the output of
the flip-flop 32, a channel select input which receives the third control
signal Mode, and an output which serves as a signal output.
Referring to FIG. 8, the input boundary-scan cell 40 comprises a
four-channel first multiplexer 41, a D-type flip-flop 42, a two-channel
second multiplexer 43 and a two-input exclusive-OR (XOR) gate 44. The XOR
gate 44 has a first input which serves as a feedback input fb, a second
input which serves as a scan input, and an output. The first multiplexer
41 has a first data input which serves as a signal input, a second data
input which is connected to the output of the XOR gate 44, third and
fourth data inputs which are connected to one another and which are
further connected to the second input of the XOR gate 44, a pair of
channel select inputs which receive the first control signal BIST* and the
second control signal ShiftDR respectively, and an output. The flip-flop
42 has a data input connected to the | | |
