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TECHNICAL FIELD OF THE INVENTION
The invention relates to computer display systems, more particularly to
bit-mapped graphic display systems, and still more particularly to digital
display controllers for bit-mapped graphic display systems.
BACKGROUND OF THE INVENTION
Computer display systems, especially those with bit-mapped graphic
capabilities, have gained widespread popularity in recent years due to the
proliferation of personal computers, high levels of functional integration
in graphic display systems, and increasing capability and decreasing cost
of computer graphics interfaces and color video monitors.
Bit-mapped computer graphics display systems are characterized by a video
frame buffer memory which contains a digital representation of an image to
be displayed. The memory is organized such that each group of "n" bits
represents a single dot or "pixel" on a display screen. The "n" bits
associated with each pixel determine its intensity, color, or other
attribute. This direct mapping of bits to individual display pixels is the
source of the name "bit-mapped". In normal operation, an image stored in a
video frame buffer memory is displayed by rapidly accessing the pixel data
in the memory in a raster-scan (e.g., left-to-right, top-to-bottom) order,
and presenting this data to a video monitor repeatedly in a serial video
stream. While some monitors accept a multi-bit digital video stream,
others require that the digital data be converted to an analog form for
display. This is usually accomplished in a DAC (Digital to Analog
Converter) whereby multi-bit digital pixel data is converted to one or
more analog intensity (brightness) signals. For color displays, three
analog intensity signals are typically used, one for each of the three
primary colors of light: red, blue and green. One or more synchronizing
signals are used to synchronize the video monitor to the start of the
memory access cycle so that each pixel is displayed in a fixed or
pre-determined position on the monitor screen.
Exemplary of bit-mapped graphics systems currently in use are "VGA"
controllers, widely used in personal computer graphics applications. A
typical modern VGA (Video Graphics Array) color graphics system for an ISA
personal computer (Industry Standard Architecture, sometimes referred to
as "IBM compatible") has up to 1 Mbyte (1,048,576 bytes) of video frame
buffer memory and is capable of displaying up to 256-color graphics images
at a displayed resolution of up to 1024.times.768 pixels (picture elements
or dots).
FIG. 1 is a block diagram of a typical VGA interface 100 (a bit-mapped
graphics display controller) for a personal computer. An integrated video
controller 105 interfaces between a host computer (not shown) via address
lines 120, data lines 125, and control lines 115. These address, data, and
control lines, 120, 125, and 115, respectively, permit the host computer
to read and write registers located within the video controller 105. The
data bus (i.e, the collection of data lines) is shown as 16 bits wide,
indicating a connection to a host computer with a bus width of at least 16
bits (typical of ISA computers). A clock synthesizer 110, provides master
timing for the video controller 105. The integrated video controller 105
is implemented as a single chip.
A notational convention for indicating bus width (the number of signals
carried between two functional blocks in a block diagram) is used herein
whereby a number immediately to the left of a diagonal slash "/" through a
line indicates the number of signals or wires (bus width) associated with
the line. This convention is reflected in the Figures.
The video controller 105 generates video timing signals and provides access
to an external (to the video controller) video frame buffer memory 130. In
FIG. 1, the video frame buffer memory 130 comprises eight 256K.times.4
(262,144.times.4) dynamic RAM (DRAM) memory chips 130a-130h, providing a
total of 1 Mbyte (1,048,576.times.8) of total available video frame buffer
memory, organized as a 256K.times.32 bit memory. Each DRAM chip 130a-130h
has a corresponding set of four data I/O lines 132a-132h connected to the
video controller 105, for a total video bus width (width of the video
frame buffer memory unit of exchange with the video controller 105) of 32
bits. The video controller 105 governs all access to the video frame
buffer memory 130, and generates an 18 bit address on lines 134, provided
in common to all of the video memory chips 130a-130h.
The integrated video controller 105 accesses the video frame buffer memory
130 for two purposes: 1) to store and/or retrieve pixel data to/from the
video frame buffer memory 130 as commanded by the host computer; and 2) to
display the pixel data stored in the memory on a video monitor. Video
monitors require that the displayed image be periodically refreshed, so
the video controller 105 must repeatedly scan through the pixel data in
the video frame buffer memory 130. Computer access to the frame buffer
memory 130 must be interleaved between the display refresh accesses, thus
limiting the amount of time the frame buffer memory is available to the
computer.
The integrated video controller 105 itself contains three functional
blocks: a video controller core 106, a FIFO 107a, a memory access control
functional block 107b, and a video shift register 108. The video
controller core 106 contains registers and logic which implement the basic
video timing and interface to the host processor. The FIFO (First-In,
First-Out buffer) and memory access control functional block manages all
accesses to the video frame buffer memory, and performs the memory
accesses required for display refresh, interleaving host computer pixel
data, buffered in the FIFO, with the display refresh accesses. The memory
access controller permits programmed (host computer) access to the video
frame buffer memory in between display refresh accesses (if any such
access time is available) and during vertical and horizontal retrace
intervals (the time periods when the display "beam" is resetting itself to
scan another row of pixels or between images).
For display refresh, the video frame buffer memory 130 is accessed 32 bits
at a time. The 32 bits of video data is then placed in a video shift
register 108 internal to the video controller 105 and shifted out in a
serial video stream on lines 142. The serial video stream (i.e., 142) as
shown is 8 bits wide, indicating a capability of displaying up to 256
colors or intensity values for each pixel. A RAM-DAC 140 (Random Access
Memory-Digital to Analog Converter) converts the digital pixel data on
lines 142 to one or more analog video signals 144 for a video monitor (not
shown). A synchronizing signal 146 (Sync) is generated by the video
controller 105 to synchronize the video monitor to the video frame buffer
access cycle.
While the discussion hereinabove with respect to FIG. 1 makes reference to
a VGA-type bit-mapped graphics controller (video controller), the
discussion applies to bit-mapped graphics controllers in general, and is
not intended to limit the field of this specification to VGA-type
controllers or to ISA-type computers. The discussion hereinafter is of a
more general nature.
On early video systems, the computer could only gain access to the video
frame buffer memory during brief periods of time, because the video
refresh access dominated access to the video frame buffer memory. This led
to very slow screen update speeds. In response to this, some early systems
provided rapid access to the video frame buffer memory by shutting down
the video display while an image was being refreshed, causing "video
flicker" while new pixel data was being written to or read from the video
frame buffer memory. Other early systems would simply over-ride the video
refresh access while the frame buffer memory was being read or written by
the host computer, causing erratic display dots or "video snow" to appear
on the video monitor during computer access to the frame buffer memory.
While this did improve display speed, the resulting erratic displays were
considered annoying at best, and unacceptable at worst. It is a
requirement of virtually all modern video display systems that
"transparent" access (access without disruption of display refresh
operations) be provided to the video frame buffer memory. This, of course,
requires a faster effective video frame buffer access time, implying
faster memories or faster memory access techniques.
A significant factor in the cost of memory chips used in video display
subsystems is access time. In general, the faster the memory, the higher
the chip cost. DRAMs (Dynamic Random Access Memories) are usually the
least expensive type of memory available for such applications. While
DRAMs require periodic "refreshing" of memory locations, the repeated
serial-access nature of the video refresh memory access provides a natural
mechanism for refreshing DRAMs transparently.
One technique which is used to provide faster "apparent" video memory speed
is to provide a very wide video memory bus. In the video system of FIG. 1,
the video memory bus width (132a-h) is 32 bits. This means that 32 bits of
pixel data are accessed at once. If there are 8 bits of pixel data per
pixel, this means that video memory need be accessed only once every four
pixels. However, at extremely high non-interlaced display resolutions
(e.g. 1024.times.768) with high refresh rates (e.g., 72 Hz), the pixel
rate is approximately 75 MHz (Megahertz), or 13.33 ns (nanoseconds) per
pixel. This means that for this high resolution and refresh rate, it is
necessary to access video memory once every 53.33 ns. While this is not
impossible using current technology, it is certainly very challenging, and
leaves virtually no time for the host computer to access the video frame
buffer memory. Only vertical and horizontal re-trace intervals (the time
while the video monitor beam is invisibly "resetting" itself) is available
for host computer access, i.e., a very small percentage of the time.
If the video memory bus width were widened to 64 bits, however, it becomes
necessary to access the video frame buffer memory only once every 106.66
ns. At video memory bus width of 128 bits, the required access rate drops
to once every 213.33 ns. At these reduced access times, it is possible to
interleave host computer memory accesses with display refresh accesses
without disrupting the display. Alternatively, it is possible to use
slower DRAMs.
In practice, however, such wide bus widths are not practical for a number
of reasons. For example, a 128 bit wide video memory bus requires 128
video data pins on the video controller, and enough printed circuit board
area to route the 128 associated signal traces from the pins of the video
controller to the video memory chips. As a result, the lengths of the
signal traces increase, and parasitic capacitances, induced noise and
crosstalk between signal traces increase. The increased lengths of the
signal traces and increased parasitic capacitances serve to reduce the
effective speed of the video memory by increasing the signal propagation
delay across the signal traces. Further, very wide memory bus widths
require a greater number of relatively smaller memory chips, increasing
both circuit board size and component cost dramatically. As a result, very
high performance video systems providing high display resolutions, high
refresh rates and higher numbers of bits per pixel (e.g., 24), tend to be
large and expensive.
Interlaced operation of video monitors (providing an image in two sweeps of
the screen by displaying alternating, interleaved rows of pixels) provides
one means for reducing the required memory access time, but the resultant
perceived display flicker tends to cause eye strain, and is generally
regarded as undesirable or unacceptable.
A further limitation on the performance of video systems is related to
package-related delays. Every pin of a package has an associated
capacitance, requiring a relatively large driver circuit on the integrated
circuit to overcome the capacitance and provide acceptable signal speed.
These drivers require a disproportionately large portion of die area, and
integrated circuits with very large numbers of pins require very large
dies just to provide the required driver circuits. Even if a video memory
chip could be designed with zero internal access time, there are lower
limits on the pin-related delay times. As memories become faster, the
pin-related delays present a larger portion of the total memory access
time, thereby placing implicit lower limits on memory access time for any
given package.
As a result of the performance limitations discussed hereinabove, many
modern computer graphics display systems suffer from a video bandwidth
"bottleneck" problem, whereby the host computer is capable of computing
pixel values faster than the video controller is capable of accepting them
and presenting them to the video frame buffer memory. As a result, overall
system performance is negatively affected by delays inherent in the design
of the video controller and video frame buffer system. These delays are
particularly noticeable at high refresh rates and display resolutions,
where display refresh-related demands on the video frame buffer memory are
greatest. This bottleneck problem is only partially addressed in some
systems by providing a FIFO (e.g. 107 with respect to FIG. 1) for
buffering pixel data from the host processor. The data is unloaded from
the FIFO by a memory access controller when a break occurs in the display
refresh sequence. However, when the host processor attempts to manipulate
large amounts of data, the FIFO fills up and the processor is forced to
wait. Providing a larger FIFO merely delays the time when the FIFO becomes
full. The basic problem is that the processor is capable of putting data
into the FIFO at a rate faster than the rate the video frame buffer memory
is available for unloading the FIFo.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide an improved
bit-mapped graphics display controller.
It is another object of the present invention to provide a technique for
improving the amount of time a host computer may gain access to video
frame buffer memory in a bit-mapped graphics display system.
It is a further object of the present invention to reduce the cost of
high-performance bit-mapped graphics display systems.
It is a further object of the present invention to provide a technique for
reducing the speed required of video frame buffer memory by
high-performance bit-mapped graphics display systems.
It is a further object of the present invention to eliminate or minimize
the video "bottleneck" problem.
It is a further object of the present invention to reduce the amount of
circuit board space required by high-performance bit-mapped graphics
display systems.
It is a further object of the present invention to provide a practical
technique for implementing very wide video memory buses in
high-performance bit-mapped graphics display systems without significantly
increasing printed circuit board space or integrated circuit package size
(pin count).
It is a further object of the present invention to minimize the amount of
delay introduced in a bit-mapped graphic system by wiring delays,
parasitic capacitances, and pin buffer delays.
According to the invention, a video controller functional block and video
frame buffer memory are integrated together on a single semiconductor die
(integrated circuit chip). The video frame buffer memory is organized in a
"wide" format, where a "wide" format is one at least "n" bits in width,
where "n" is, for example 128,256, 512,768, or 1024. The wide video memory
format is made possible by the integration of the video controller and the
video frame buffer memory, since all of the connections are internal to
the integrated circuit die and do not require pad buffers, pins, or extra
packages. By providing a wide video memory format, the display refresh
function requires less frequent access to the video frame buffer memory.
As a result, the percentage of the time that the video frame buffer memory
is "tied up" in display refresh is proportionately reduced, allowing the
host processor (computer) more frequent access to pixel data in the video
frame buffer memory.
Such a bit-mapped video controller (graphics controller) integrated onto a
single semiconductor die comprises a video controller functional block on
the semiconductor die, a video frame buffer memory on the semiconductor
die organized in a "wide" format, an interface between the video
controller functional block and a host computer, means on the
semiconductor die for retrieving pixel data from the video frame buffer
memory and providing it in a serial video format, and means on the
semiconductor die for exchanging pixel data between the video controller
and the video frame buffer memory.
According to a feature of the invention, a cache memory may be provided
between the video controller functional block and the video frame buffer
memory.
According to another feature of the invention, a FIFO buffer may be
provided between the video controller functional block and the video frame
buffer memory.
In a particular implementation, a single semiconductor die has a video
controller functional block on the semiconductor die, a one megabyte video
frame buffer memory organized in a 256 bit wide by 32768 bit deep format
on the semiconductor die, an interface between the video controller
functional block and a host computer, first means on the semiconductor
die-for retrieving pixel data from the video frame buffer memory by
accessing pixel data in the video frame buffer memory and providing it in
a serial video format, means for providing one or more video synchronizing
signals, a cache memory on the semiconductor die, logically positioned
between the video controller functional block and the video frame buffer
memory, and providing a buffer for pixel data accesses therebetween, and
means on the semiconductor die for interleaving video frame buffer memory
accesses such that pixel data accesses from the video controller via the
cache memory are permitted only between pixel data accesses by the first
means.
The cost of high-performance bit-mapped graphics display systems is reduced
in this manner, by eliminating a large number of packages, and providing
cost-effective, practical means for providing a wide video memory bus.
With many of the performance constraints eliminated, and with the video
"bottleneck" problem eliminated, high-performance bit-mapped systems may
be readily built at minimal cost.
Printed circuit board space is minimized by eliminating the packages
required for video memory (in prior art implementations), and by
simplifying connections and reducing the number of traces required on a
printed circuit board.
Other objects, features and advantages of the invention will become
apparent in light of the following description thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a bit-mapped graphics display controller with
external frame buffer memory, of the prior art.
FIG. 2 is a block diagram of an integrated video controller chip for a
bit-mapped graphics display system, according to the present invention.
FIGS. 3 and 4 are block diagrams of alternative implementations of the
integrated video controller chip of FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
The present invention eliminates many of the significant problems
associated with prior-art video controller systems by integrating the
video controller and video frame buffer memory on a single integrated
circuit chip. By doing this, no packages are required for the video frame
buffer memory. All connections between the video frame buffer memory and
the video controller are internal to the chip, requiring no pad buffers
(pin drivers) and having extremely short length and very small parasitic
capacitance. Also, by eliminating the pin and wiring delays between the
video controller and the video frame buffer memory, the effective speed of
a DRAM memory of a given technology is increased. In a bit-mapped graphics
display system incorporating the techniques of the invention, where a
large video frame buffer memory is used, as much as 20 ns or more of
memory access time may be eliminated by integrating the video controller
and video frame buffer memory together on a single semiconductor die.
A major consideration in prior-art bit-mapped video graphics controllers is
the organization and size of video frame buffer memory, since very wide
video frame buffers tend to require large numbers of chips, large numbers
of video controller pins, and a great deal of printed circuit board space.
In the present inventive technique, since no package pins are used between
the video frame buffer memory and the video controller, video frame buffer
bus widths may be made arbitrarily large, for example, greater than
128,256,512 or 1024 bits wide, without concern about the impact of video
frame buffer memory organization on the number of packages or on pin
count. For the purposes of this specification, a "wide" video bus or video
memory is defined as a video bus or video memory having a width greater
than or equal to "n" bits of video data, where "n" is, for example, 128,
256, 512, 768, or 1024.
By making the video frame buffer bus width very large, the frequency of
video frame buffer memory access required for refreshing a video display
is proportionately reduced, providing greater availability of the video
frame buffer memory to the host computer. For example, in a bit-mapped
display system with a video bus width of 256 bits, at a displayed
non-interlaced resolution of 1024 by 768 pixels, with 256 colors (8 bits)
per pixel, the video frame buffer need be accessed only once every 426.666
ns, easily permitting several host computer accesses to video frame buffer
memory between sequential display refresh accesses.
Unlike traditional integration efforts, where existing discrete components
are simply re-implemented in a smaller number of chips, the present
inventive technique makes possible wide-bus video memory architectures
which would not otherwise be practical.
FIG. 2 is a block diagram of a single-chip bit-mapped graphics display
controller 200 according to the present invention. A video controller core
206, cache memory 207a, memory access control functional block 207b, a
video shift register 208, and a 1 Megabyte DRAM video frame buffer memory
230 are integrated together on one chip. The boundaries of the chip 200
are indicated by a dashed line. The video controller core 206 provides
basic video signal timing and interfaces to a host processor (computer)
via control lines 215, address lines 220 and data lines 225. A master
timing signal 210 (essentially a master clock signal) provides a frequency
reference to the video controller core 206 for the generation of basic
video timing and synchronization signals 246. The video controller core
206 accesses pixel data in the video frame buffer memory 230 via the cache
memory 207a. The video controller core 206 accesses video frame buffer
memory 230 (as commanded by the host computer) via the cache memory 207a
across lines 262. The cache memory 207a is optional, but provides improved
access to the video frame buffer memory 230 over comparable FIFO memory
interfaces (such as that depicted in FIG. 1). The cache memory is based
upon a (relatively) small high-speed (e.g., 10-20 ns) static RAM buffer.
Any of a variety of suitable cache memory techniques, (e.g.,
direct-mapped, set-associative, etc.) may be used. Cache memories are
widely known in the art, and will not be further elaborated upon herein.
The video controller core 206 is a functional counterpart of the video
controller core described hereinabove as 106 with respect to FIG. 1.
The video frame buffer memory 230 is organized as a 32768 bit deep by 256
bit wide memory, i.e., it is accessed 256 bits at a time. The video memory
data is presented on a 256 bit wide video frame memory bus 232, which
connects the video frame buffer memory 230 to the cache memory 207a and
the video shift register 208. In a single chip configuration of this type,
using conventional 4 megabit or 16 megabit DRAM technology, it is not
difficult to obtain effective memory access times of 50 ns or less.
The memory access control functional block 207b governs all access to the
video frame buffer memory 230. Control signals 252 generated by the memory
access control functional block 207b cause the video frame buffer memory
230 to be written and read. Video frame buffer memory access requests
(from the cache memory 207a) and grants (from the memory access controller
207b) are exchanged along lines 252. Control signals 260 cause video
memory data on video memory bus 232 to be written to the video shift
register 208. Mode information is received by the memory access control
functional block 207b from the video core 206 along lines 254. This mode
information indicates the selected display resolution and type and
frequency of memory access required for display refresh. Similarly,
control information from the video controller core 206 on lines 258
configure the video shift register for the correct pixel depth (number of
bits per pixel) according to the selected video display mode.
The video shift register 208 performs a parallel-to-serial conversion of
the video memory data at the displayed pixel rate such that new digital
pixel data is shifted on to digital video lines 242 for each pixel. The
digital video signal is provided to an external display device in a serial
video format. The video controller core generates one or more
synchronizing signals ("Sync") on line 246.
A key feature of the present inventive technique is the integration of the
video controller logic and the video frame buffer memory, permitting very
large video bus widths without increasing the number of printed circuit
board traces, package count or pin count. This also relaxes memory speed
requirements by eliminating signal delays due to parasitic capacitances,
wiring, and pin or pad drivers (pad buffer circuits).
Because of the elimination of extra packages and their attendant relatively
high-current pin drivers, a fringe benefit of significantly reduced power
consumption is realized by the technique of the present invention. This
makes bit-mapped graphics display controllers of this type particularly
applicable to battery-powered applications, such as laptop and notebook
computers.
Assuming that 8 external DRAM chips would be used in an equivalent
prior-art bit-mapped graphics display system, power savings for the
techniques of the present invention may be estimated as follows:
Based upon 100 pf (picofarads) per address pin (roughly 12.5 pf contributed
per DRAM chip) as seen at the video controller chip, with 12 active
address pins, operating at 33 MHz, with a 5 Volt power supply, current
saving are given approximately by: 100 pf.times.5 volts.times.33 MHz,
.times.12 pins=200 ma (milliamps). At 5 volts, this is a 1 watt savings by
the elimination of the address pins alone. The amount of power saved by
the elimination of the 32 DRAM data pins is also significant. Dynamic
current and static current contributions from these are also saved. A
conservative estimate is an additional savings of 400 ma, or another 2
watts of power dissipation.
Alternative approaches to the cache memory (207b) shown in FIG. 2 include
providing a FIFO buffer, such as that described with respect to FIG. 1,
between the video controller core and the video frame buffer memory in
place of the cache memory. Such an implementation 200a is shown in FIG. 3,
which is identical to the video controller chip of FIG. 2 except that the
cache memory 207b is replaced with a FIFO buffer 207c.
It is also an alternative, in some cases, not to provide any buffer between
the video controller 206 and the video frame buffer memory 230. In the
event that the frame buffer is busy, the video controller 206 simply waits
until the frame buffer becomes available. Such an alternative
implementation 200b is shown in FIG. 4, which is identical to the video
controller chip 200 of FIG. 2a except that no buffer or cache of any kind
is used between the video controller core 206 and the video frame buffer
memory 230. The 256 bit video memory bus 232 connects directly to the
video controller core 206, providing direct, unbuffered access from the
video controller core 206 to the video frame buffer memory 230. Control of
access to the video frame buffer memory 230 by the video controller core
206 is effected by the memory access control functional block 207b via
line 254.
The alternative implementations depicted in FIGS. 3 and 4 would be used
only in cases where video frame buffer memory is sufficiently available to
the host computer that any delays imposed by waiting for a display refresh
access to complete are minimal or tolerable.
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