In a recording apparatus for video signals, adjacent pixels in input image signals are collected as blocks and subjected to orthogonal transformation. Then, the dc component, control data, ac components, end-of-block signal and the like in a block after orthogonal transformation are coded and the codewords are arranged in prescribed record areas. One or a plurality of record areas forms a correction area, and error correction coding is performed and recorded on the data in a correction area. When record data are reproduced and recorded again, errors are detected in the unit of the error correction area. The dc component and the like in a record area wherein an error which cannot be corrected exists are replaced by a codeword which is not used ordinarily, and a codeword for the first ac component is replaced by an end-of-block codeword.
A method for decoding a video signal in which the decoding operation is completed within a predetermined time irrespective of the presence of an error which is generated on a bit strings. In the case where a bit strings formed by coding a video signal for each of predetermined blocks, the decoding operation is suspended upon the detection of the presence of an error in the bit strings followed by resuming the decoding operation from any of the synchronous codes present on the bit strings. At this time, it is judged on the basis of the position of the error detected from the bit strings as to from which synchronous code out of the synchronous codes present on the bit strings the decoding operation is resumed thereby completing within a predetermined time the decoding operation of a series of data groups including an error part of the bit strings.
A digital video signal processor for compressing a digital video signal and recording the compressed signal. The digital video signal processor includes a black-and-white signal detector which determines whether the digital video signal is a black-and-white signal and outputs a detection signal when it is determined that the digital video signal is a black-and-white signal. A block processor shuffles the digital video signal from the black-and-white signal detector by predetermined block units. A signal compressor compresses shuffled video signal output by the block processor. A modulator modulates compressed video signal output by the signal compressor and black-and-white signal information. A controller generates a compression control signal to be output to the signal compressor and outputs the black-and-white signal information to the modulator in response to the detection signal. When the compression control signal is received, the signal compressor transform-encodes the shuffled video signal such that a color component is encoded only with a DC coefficient. As a result, a black-and-white video signal can be recorded with higher-resolution.
The invention provides a data processing apparatus and method which processes data in which additional data is embedded and inhibits illegal accessing from the outside to prevent alteration of information. The data processing apparatus includes a coding section for coding the data, a detection section for detecting the additional data from the data, a processing section for processing the coded data coded by the coding section, and a control section for controlling operation of the processing section in response to the additional data detected by the detection section. The coding section controls an output thereof in response to the additional data detected by the detection section, and accessing to the additional data used to control the coding section is inhibited.
In a synchronous information reproduction apparatus, a receiving section sequentially receives a clock signal. A storing section stores object information to be sequentially reproduced from a series of reproduction points. A reproduction point generating section generates location information indicative of a reproduction point of the object information stored in the storing section. A reproducing section reads and reproduces the object information from the storing section based on the reproduction point generated by the reproduction point generating section. A synchronizing section synchronizes an incremental speed of the reproduction point generated by the reproduction point generating section with a reception timing of the clock signal based on a reception time interval of the clock signals. An outputting section outputs contents of the object information reproduced by the reproducing section.
In a coding system wherein an error correction/detection coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
