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BACKGROUND OF THE INVENTION
The invention relates to the field of televisions capable of displaying
side-by-side pictures of substantially equal size from different sources,
and in particular, to such televisions having a wide display format ratio
screen. Most televisions today have a format display ratio, horizontal
width to vertical height, of 4:3. A wide format display ratio corresponds
more closely to the display format ratio of movies, for example 16:9. The
invention is applicable to both direct view televisions and projection
televisions.
Televisions having a format display ratio of 4:3, often referred to as
4.times.3, are limited in the ways that single and multiple video signal
sources can be displayed. Television signal transmissions of commercial
broadcasters, except for experimental material, are broadcast with a
4.times.3 format display ratio. Many viewers find the 4.times.3 display
format less pleasing than the wider format display ratio associated with
the movies. Televisions with a wide format display ratio provide not only
a more pleasing display, but are capable of displaying wide display format
signal sources in a corresponding wide display format. Movies "look" like
movies, not cropped or distorted versions thereof. The video source need
not be cropped, either when converted from film to video, for example with
a telecine device, or by processors in the television.
Televisions with a wide display format ratio are also suited to a wide
variety of displays for both conventional and wide display format signals,
as well as combinations thereof in multiple picture displays. However, the
use of a wide display ratio screen entails numerous problems. Changing the
display format ratios of multiple signal sources, developing consistent
timing signals from asynchronous but simultaneously displayed sources,
switching between multiple sources to generate multiple picture displays,
and providing high resolution pictures from compressed data signals are
general categories of such problems. Such problems are solved in a wide
screen television according to this invention. A wide screen television
according to various inventive arrangements is capable of providing high
resolution, signal and multiple picture displays, from single and multiple
sources having similar or different format ratios, and with selectable
display format ratios.
Televisions with a wide display format ratio can be implemented in
television systems displaying video signals both at basic or standard
horizontal scanning rates and multiples thereof, as well as by both
interlaced and noninterlaced scanning. Standard NTSC video signals, for
example, are displayed by interlacing the successive fields of each video
frame, each field being generated by a raster scanning operation at a
basic or standard horizontal scanning rate of approximately 15,734 Hz. The
basic scanning rate for video signals is variously referred to as f.sub.H,
1f.sub.H, and 1H. The actual frequency of a 1f.sub.H signal will vary
according to different video standards. In accordance with efforts to
improve the picture quality of television apparatus, systems have been
developed for displaying video signals progressively, in a noninterlaced
fashion. Progressive scanning requires that each displayed frame must be
scanned in the same time period allotted for scanning one of the two
fields of the interlaced format. Flicker free AA-BB displays require that
each field be scanned twice, consecutively. In each case, the horizontal
scanning frequency must be twice that of the standard horizontal
frequency. The scanning rate for such progressively scanned or flicker
free displays is variously referred to as 2f.sub.H and 2H. A 2f.sub.H
scanning frequency according to standards in the U.S., for example, is
approximately 31,468 Hz.
Television apparatus with conventional format display ratios can be
equipped for displaying multiple pictures, for example from two video
sources. The video sources may be the tuner in the television, a tuner in
a video cassette recorder, a video camera, and others. In a mode often
referred to as picture-in-picture (PIP), the tuner in the television
provides a picture filling most of the screen, or display area, and an
auxiliary video source provides a small inset picture generally within the
boundaries of the larger picture. A PIP display mode in a wide screen
television apparatus is shown in FIG. 1(c). In many instances, the inset
picture can be positioned in a number of different locations. Another
display mode is often referred to as channel scan, wherein a large number
of small pictures, each from a different channel source, fill the screen
in a freeze frame montage. There is no main picture, at least in terms of
size. A channel scan display mode in a wide screen television apparatus is
shown in FIG. 1(i). In wide screen television apparatus, other display
modes are possible. One is referred to as picture-outside-picture (POP).
In this mode, several inset auxiliary pictures can share a common boundary
with a main picture. A POP display mode in a wide screen television
apparatus is shown in FIG. 1(f). Another mode particularly suited for a
wide screen television is side-by-side pictures of substantially the same
size, from different video sources, for example two different channels.
This mode is illustrated for a wide screen television in FIG. 1(d) for two
4:3 video sources. It will be appreciated that this mode can be considered
a special case of the POP mode.
Horizontal scanning is accomplished in the same amount of time in a wide
screen television apparatus as in a conventional television apparatus.
However, the distance of the horizontal scan is greater in the wide screen
television. This will stretch the picture horizontally, creating
significant aspect ratio distortion of the images in the displayed
picture. Accordingly, problems can be encountered when displaying a video
signal having a conventional 4:3 display format ratio on a wide screen
television apparatus, for example one having a 16:9 format display ratio.
These particular format display ratios would result in a horizontal
stretching or expansion by a factor of 4/3. This is a problem for
displaying pictures having a 4:3 display format ratio as a main picture
and as an auxiliary picture, such as a PIP or POP. This is also a problem
for PIP and POP modes even if the main picture originates from a video
source having a 16:9 format display ratio which matches the display means
of the television apparatus.
Certain digital circuits, sometimes referred to generally as
picture-in-picture processors, are available which can implement PIP and
channel scan modes in a conventional television apparatus. One such
picture-in-picture processor is designated as a CPIP chip and is available
from Thomson Consumer Electronics, Inc. The CPIP chip is described more
fully in a publication entitled The CTC 140 Picture in Picture (CPIP)
Technical Training Manual, available from Thomson Consumer Electronics,
Inc., Indianapolis, Ind. Such picture-in-picture processors are not
suitable for implementing special display modes, such as PIP, POP and
channel scan, in wide screen television apparatus. If an auxiliary picture
developed by such a picture-in-picture processor from an auxiliary video
source were displayed on a wide screen television apparatus without an
external speedup circuit, the auxiliary picture, or pictures, would be
geometrically distorted as described above. The auxiliary picture would
exhibit a horizontal expansion by a factor of 4/3 due to the wider
horizontal scanning of the wider picture tube, whether direct view or
projection. If an external speedup circuit were used, the auxiliary
picture would appear without aspect ratio distortion, but would not fill
the screen or fill the portion of the screen otherwise allotted for the
auxiliary display.
In order to display two pictures side-by-side, the display is locked to one
of two incoming signals, referred to as the first signal or first picture
for convenience. This can be the left picture or the right picture in the
side-by-side mode. However the first picture may become nonfunctional. For
example, the television receiver could be tuned to a blank channel, or the
television station could go off the air, or the video source could be
interrupted. If the first picture becomes nonfunctional, the
synchronization for the second picture is also lost. Without proper
synchronization, the second picture will jitter.
SUMMARY OF THE INVENTION
The first picture signal is monitored to prevent the loss of display
synchronization when the first picture signal is lost. A display system
for side-by-side pictures according to an inventive arrangement comprises
a first circuit for separating a first composite synchronizing signal from
a first video signal having a conventional format display ratio and a
second circuit for separating a second composite synchronizing signal from
a second video signal having the same conventional format display ratio. A
detecting circuit senses the presence of the first video signal, by
monitoring the horizontal synchronizing component thereof. A video display
control circuit has a mode of operation in which pictures representative
of the first and second video signals are displayed in side-by-side
relationship and substantially without image aspect ratio distortion. A
synchronization switch selects one of the first and second composite
synchronizing signals for synchronizing the video display. The second
composite synchronizing signal is automatically selected unless the
horizontal synchronizing component of the first video signal is detected.
The detecting circuit comprises a synchronizing component separator, a
bandpass filter, and a detector. When the first video signal is present,
the horizontal synchronizing signal is separated and monitored. The
detecting circuit generates an output signal indicating whether an
adequate horizontal synchronizing component is present. The invention
further comprises a microprocessor coupled to the detecting circuit and
the automatic synchronization switch. The microprocessor controls the
automatic synchronization switch output to be the second composite
synchronizing signal when the first video signal is not detected by the
detecting circuit.
The invention further comprises a first signal processing means for
speeding up the first video signal, a video display means synchronized
with the automatic synchronization switch output, means for vertically
synchronizing the second video signal with the first video signal and the
video display means, a second signal processing means for speeding up said
second video signal, and means for combining the first and second
processed video signals for side-by-side display. The first and second
signal processing means can crop and reduce picture size so that the first
and second pictures can be displayed on a wide screen display.
Thus, the second picture can be displayed in a side-by-side video display
system despite the loss of the first picture.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(a)-1(i) are useful for explaining different display formats of a
wide screen television.
FIG. 2 is a block diagram of a wide screen television in accordance with
aspects of this invention and adapted for operation at 2f.sub.H horizontal
scanning.
FIG. 3 is a block diagram of the wide screen processor shown in FIG. 2.
FIG. 4 is a block diagram of a wide screen television in accordance with
aspects of this invention and adapted for operation at 1f.sub.H horizontal
scanning.
FIG. 5 is a block diagram of the wide screen processor shown in FIG. 4.
FIG. 6 is a block diagram showing further details of the wide screen
processor common to FIGS. 3 and 5.
FIG. 7 is a block diagram of the picture-in-picture processor shown in FIG.
6.
FIG. 8 is a block diagram of the gate array shown in FIG. 6 and
illustrating the main, auxiliary and output signal paths.
FIGS. 9 and 10 are timing diagrams useful for explaining the generation of
the display format shown in FIG. 1(d), using fully cropped signals.
FIG. 11 is a block diagram showing the main signal path of FIG. 8 in more
detail.
FIG. 12 is a block diagram showing the auxiliary signal path of FIG. 8 in
more detail.
FIG. 13 is a block diagram of the timing and control section of the
picture-in-picture processor of FIG. 7.
FIG. 14 is a block diagram of a circuit for generating the internal
2f.sub.H signal in the 1f.sub.H to 2f.sub.H conversion.
FIG. 15 is a combination block and circuit diagram for the deflection
circuit shown in FIG. 2.
FIG. 16 is a block diagram of the RGB interface shown in FIG. 2.
FIG. 17 is a block diagram of a wide screen television adapted for
operation with an automatic synchronization switch.
FIG. 18 is a timing diagram of the composite video signal processed by the
detecting circuit.
FIG. 19 is a circuit diagram of a sync separator and bandpass filter
adapted to be used in the detecting circuit.
FIG. 20 is a circuit diagram of a detector with hysteresis adapted to be
used in the detecting circuit.
FIG. 21 is a block diagram of the bandpass filter adapted to be used in the
detecting circuit.
FIG. 22 illustrates the response of the bandpass filter of FIGS. 19 and 21.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The various parts of FIG. 1 illustrate some, but not all of the various
combinations of single and multiple picture display formats which can be
implemented according to different inventive arrangements. Those selected
for illustration are intended to facilitate the description of particular
circuits comprising wide screen televisions according to the inventive
arrangements. For purposes of convenience in illustration and discussion
herein, a conventional display format ratio of width to height for a video
source or signal is generally deemed to be 4.times.3, whereas a wide
screen display format ratio of width to height for a video source or
signal is generally deemed to be 16.times.9. The inventive arrangements
are not limited by these definitions.
FIG. 1(a) illustrates a television, direct view or projection, having a
conventional format display ratio of 4.times.3. When a 16.times.9 format
display ratio picture is transmitted, as a 4.times.3 format display ratio
signal, black bars appear at the top and at the bottom. This is commonly
referred to as letterbox format. In this instance, the viewed picture is
rather small with respect to the entire available display area.
Alternatively, the 16.times.9 format display ratio source is converted
prior to transmission, so that it will fill the vertical extent of a
viewing surface of 4.times.3 format display. However, much information
will be cropped from the left and/or right sides. As a further
alternative, the letterbox picture can be expanded vertically but not
horizontally, whereby the resulting picture will evidence distortion by
vertical elongation. None of the three alternatives is particularly
appealing.
FIG. 1(b) shows a 16.times.9 screen. A 16.times.9 format display ratio
video source would be fully displayed, without cropping and without
distortion. A 16.times.9 format display ratio letterbox picture, which is
itself in a 4.times.3 format display ratio signal, can be progressively
scanned by line doubling or line addition, so as to provide a larger
display with sufficient vertical resolution. A wide screen television in
accordance with this invention can display such a 16.times.9 format
display ratio signal whether the main source, the auxiliary source or an
external RGB source.
FIG. 1(c) illustrates a 16.times.9 format display ratio main signal in
which a 4.times.3 format display ratio inset picture is displayed. If both
the main and auxiliary video signals are 16.times.9 format display ratio
sources, the inset picture can also have a 16.times.9 format display
ratio. The inset picture can be displayed in many different positions.
FIG. 1(d) illustrates a display format, wherein the main and auxiliary
video signals are displayed with the same size picture. Each display area
has an format display ratio of 8.times.9, which is of course different
from both 16.times.9 and 4.times.3. In order to show a 4.times.3 format
display ratio source in such a display area, without horizontal or
vertical distortion, the signal must be cropped on the left and/or right
sides. More of the picture can be shown, with less cropping, if some
aspect ratio distortion by horizontal squeezing of the picture is
tolerated. Horizontal squeezing results in vertical elongation of objects
in the picture. The wide screen television according to this invention can
provide any mix of cropping and aspect ratio distortion from maximum
cropping with no aspect ratio distortion to no cropping with maximum
aspect ratio distortion.
Data sampling limitations in the auxiliary video signal processing path can
complicate the generation of a high resolution picture which is as large
in size as the display from the main video signal. Various methods can be
developed for overcoming these complications.
FIG. 1(e) is a display format wherein a 4.times.3 format display ratio
picture is displayed in the center of a 16.times.9 format display ratio
screen. Dark bars are evident on the right and left sides.
FIG. 1(f) illustrates a display format wherein one large 4.times.3 format
display ratio picture and three smaller 4.times.3 format display ratio
pictures are displayed simultaneously. A smaller picture outside the
perimeter of the large picture is sometimes referred to as a POP, that is
a picture-outside-picture, rather than a PIP, a picture-in-picture. The
terms PIP or picture-in-picture are used herein for both display formats.
In those circumstances where the wide screen television is provided with
two tuners, either both internal or one internal and one external, for
example in a video cassette recorder, two of the displayed pictures can
display movement in real time in accordance with the source. The remaining
pictures can be displayed in freeze frame format. It will be appreciated
that the addition of further tuners and additional auxiliary signal
processing paths can provide for more than two moving pictures. It will
also be appreciated that the large picture on the one hand, and the three
small pictures on the other hand, can be switched in position, as shown in
FIG. 1(g).
FIG. 1(h) illustrates an alternative wherein the 4.times.3 format display
ratio picture is centered, and six smaller 4.times.3 format display ratio
pictures are displayed in vertical columns on either side. As in the
previously described format, a wide screen television provided with two
tuners can provide two moving pictures. The remaining eleven pictures will
be in freeze frame format.
FIG. 1(i) shows a display format having a grid of twelve 4.times.3 format
display ratio pictures. Such a display format is particularly appropriate
for a channel selection guide, wherein each picture is at least a freeze
frame from a different channel. As before, the number of moving pictures
will depend upon the number of available tuners and signal processing
paths.
The various formats shown in FIG. 1 are illustrative, and not limiting, and
can be implemented by wide screen televisions shown in the remaining
drawings and described in detail below.
An overall block diagram for a wide screen television in accordance with
inventive arrangements, and adapted to operate with 2f.sub.H horizontal
scanning, is shown in FIG. 2 and generally designated 10. The television
10 generally comprises a video signals input section 20, a chassis or TV
microprocessor 216, a wide screen processor 30, a 1f.sub.H to 2f.sub.H
converter 40, a deflection circuit 50, an RGB interface 60, a YUV to RGB
converter 240, kine drivers 242, direct view or projection tubes 244 and a
power supply 70. The YUV to RGB converter 240 may be an industry type
TA7730. The grouping of various circuits into different functional blocks
is made for purposes of convenience in description, and is not intended as
limiting the physical position of such circuits relative to one another.
The video signals input section 20 is adapted for receiving a plurality of
composite video signals from different video sources. The video signals
may be selectively switched for display as main and auxiliary video
signals. An RF switch 204 has two antenna inputs ANT1 and ANT 2. These
represent inputs for both off-air antenna reception and cable reception.
The RF switch 204 controls which antenna input is supplied to a first
tuner 206 and to a second tuner 208. The output of first tuner 206 is an
input to a one-chip 202, which performs a number of functions related to
tuning, horizontal and vertical deflection and video controls. The
particular one-chip shown is industry designated type TA7777. The baseband
video signal VIDEO OUT developed in the one-chip and resulting from the
signal from first tuner 206 is an input to both video switch 200 and the
TV1 input of wide screen processor 30. Other baseband video inputs to
video switch 200 are designated AUX1 and AUX 2. These might be used for
video cameras, laser disc players, video tape players, video games and the
like. The output of the video switch 200, which is controlled by the
chassis or TV microprocessor 216 is designated SWITCHED VIDEO. The
SWITCHED VIDEO is another input to wide screen processor 30.
With further reference to FIG. 3, a switch SW1 wide screen processor
selects between the TV1 and SWITCHED VIDEO signals as a SEL COMP OUT video
signal which is an input to a Y/C decoder 210. The Y/C decoder 210 may be
implemented as an adaptive line comb filter. Two further video sources S1
and S2 are also inputs to the Y/C decoder 210. Each of S1 and S2 represent
different S-VHS sources, and each consists of separate luminance and
chrominance signals. A switch, which may be incorporated as part of the
Y/C decoder, as in some adaptive line comb filters, or which may be
implemented as a separate switch, is responsive to the TV microprocessor
216 for selecting one pair of luminance and chrominance signals as outputs
designated Y.sub.-- M and C.sub.-- IN respectively. The selected pair of
luminance and chrominance signals is thereafter considered the main signal
and is processed along a main signal path. Signal designations including
.sub.-- M or .sub.-- MN refer to the main signal path. The chrominance
signal C.sub.-- IN is redirected by the wide screen processor back to the
one-chip, for developing color difference signals U.sub.-- M and V.sub.--
M. In this regard, U is an equivalent designation for (R-Y) and V is an
equivalent designation for (B-Y). The Y.sub.-- M, U.sub.-- M, and V.sub.--
M signals are converted to digital form in the wide screen processor for
further signal processing.
The second tuner 208, functionally defined as part of the wide screen
processor 30, develops a baseband video signal TV2. A switch SW2 selects
between the TV2 and SWITCHED VIDEO signals as an input to a Y/C decoder
220. The Y/C decoder 220 may be implemented as an adaptive line comb
filter. Switches SW3 and SW4 select between the luminance and chrominance
outputs of Y/C decoder 220 and the luminance and chrominance signals of an
external video source, designated Y.sub.-- EXT and C.sub.-- EXT
respectively. The Y.sub.-- EXT and C.sub.-- EXT signals correspond to the
S-VHS input S1. The Y/C decoder 220 and switches SW3 and SW4 may be
combined, as in some adaptive line comb filters. The output of switches
SW3 and SW4 is thereafter considered the auxiliary signal and is processed
along an auxiliary signal path. The selected luminance output is
designated Y.sub.-- A. Signal designations including .sub.-- A, .sub.-- AX
and .sub.-- AUX refer to the auxiliary signal path. The selected
chrominance is converted to color difference signals U.sub.-- A and
V.sub.-- A. The Y.sub.-- A, U.sub.-- A and V.sub.-- A signals are
converted to digital form for further signal processing. The arrangement
of video signal source switching in the main and auxiliary signal paths
maximizes flexibility in managing the source selection for the different
parts of the different picture display formats.
A composite synchronizing signal COMP SYNC, corresponding to Y.sub.-- M is
provided by the wide screen processor to a sync separator 212. The
horizontal and vertical synchronizing components H and V respectively are
inputs to a vertical countdown circuit 214. The vertical countdown circuit
develops a VERTICAL RESET signal which is directed into the wide screen
processor 30. The wide screen processor generates an internal vertical
reset output signal INT VERT RST OUT directed to the RGB interface 60. A
switch in the RGB interface 60 selects between the internal vertical reset
output signal and the vertical synchronizing component of the external RGB
source. The output of this switch is a selected vertical synchronizing
component SEL.sub.-- VERT.sub.-- SYNC directed to the deflection circuit
50. Horizontal and vertical synchronizing signals of the auxiliary video
signal are developed by sync separator 250 in the wide screen processor.
The 1f.sub.H and 2f.sub.H converter 40 is responsible for converting
interlaced video signals to progressively scanned noninterlaced signals,
for example one wherein each horizontal line is displayed twice, or an
additional set of horizontal lines is generated by interpolating adjacent
horizontal lines of the same field. In some instances, the use of a
previous line or the use of an interpolated line will depend upon the
level of movement which is detected between adjacent fields or frames. The
converter circuit 40 operates in conjunction with a video RAM 420. The
video RAM may be used to store one or more fields of a frame, to enable
the progressive display. The converted video data as Y.sub.-- 2f.sub.H,
U.sub.-- 2f.sub.H and V.sub.-- 2f.sub.H signals is supplied to the RGB
interface 60.
The RGB interface 60, shown in more detail in FIG. 16, enables selection of
the converted video data or external RGB video data for display by the
video signals input section. The external RGB signal is deemed to be a
wide format display ratio signal adapted for 2f.sub.H scanning. The
vertical synchronizing component of the main signal is supplied to the RGB
interface by the wide screen processor an INT VERT RST OUT, enabling a
selected vertical sync (f.sub.Vm or f.sub.Vext) to be available to the
deflection circuit 50. Operation of the wide screen television enables
user selection of an external RGB signal, by generating an
internal/external control signal INT/EXT. However, the selection of an
external RGB signal input, in the absence of such a signal, can result in
vertical collapse of the raster, and damage to the cathode ray tube or
projection tubes. Accordingly, the RGB interface circuit detects an
external synchronizing signal, in order to override the selection of a
non-existent external RGB input. The WSP microprocessor 340 also supplies
color and tint controls for the external RGB signal.
The wide screen processor 30 comprises a picture in picture processor 320
for special signal processing of the auxiliary video signal. The term
picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. A gate
array 300 combines the main and auxiliary video signal data in a wide
variety of display formats, as shown by the examples of FIGS. 1(b) through
1(i). The picture-in-picture processor 320 and gate array 300 are under
the control of a wide screen microprocessor (WSP .mu.P) 340.
Microprocessor 340 is responsive to the TV microprocessor 216 over a
serial bus. The serial bus includes four signal lines, for data, clock
signals, enable signals and reset signals. The wide screen processor 30
also generates a composite vertical blanking/reset signal, as a three
level sandcastle signal. Alternatively, the vertical blanking and reset
signals can be generated as separate signals. A composite blanking signal
is supplied by the video signal input section to the RGB interface.
The deflection circuit 50, shown in more detail in FIG. 15, receives a
vertical reset signal from the wide screen processor, a selected 2f.sub.H
horizontal synchronizing signal from the RGB interface 60 and additional
control signals from the wide screen processor. These additional control
signals relate to horizontal phasing, vertical size adjustment and
east-west pin adjustment. The deflection circuit 50 supplies 2f.sub.H
flyback pulses to the wide screen processor 30, the 1f.sub.H to 2f.sub.H
converter 40 and the YUV to RGB converter 240.
Operating voltages for the entire wide screen television are generated by a
power supply 70 which can be energized by an AC mains supply.
The wide screen processor 30 is shown in more detail in FIG. 3. The
principal components of the wide screen processor are a gate array 300, a
picture-in-picture circuit 301, analog to digital and digital to analog
converters, the second tuner 208, a wide screen processor microprocessor
340 and a wide screen output encoder 227. Further details of the wide
screen processor, which are in common with both the 1f.sub.H and the
2f.sub.H chassis, for example the PIP circuit, are shown in FIG. 6. A
picture-in-picture processor 320, which forms a significant part of the
PIP circuit 301, is shown in more detail in FIG. 7. The gate array 300 is
shown in more detail in FIG. 8. A number of the components shown in FIG.
3, forming parts of the main and auxiliary signal paths, have already been
described in detail.
The second tuner 208 has associated therewith an IF stage 224 and an audio
stage 226. The second tuner 208 also operates in conjunction with the WSP
.mu.P 340. The WSP .mu.P 340 comprises an input output I/O section 340A
and an analog output section 340B. The I/O section 340A provides tint and
color control signals, the INT/EXT signal for selecting the external RGB
video source and control signals for the switches SW1 through SW6. The I/O
section also monitors the EXT SYNC DET signal from the RGB interface to
protect the deflection circuit and cathode ray tube(s). The analog output
section 340B provides control signals for vertical size, east-west adjust
and horizontal phase, through respective interface circuits 254, 256 and
258.
The gate array 300 is responsible for combining video information from the
main and auxiliary signal paths to implement a composite wide screen
display, for example one of those shown in the different parts of FIG. 1.
Clock information for the gate array is provided by phase locked loop 374,
which operates in conjunction with low pass filter 376. The main video
signal is supplied to the wide screen processor in analog form, and Y U V
format, as signals designated Y.sub.-- M, U.sub.-- M and V.sub.-- M. These
main signals are converted from analog to digital form by analog to
digital converters 342 and 346, shown in more detail in FIG. 4.
The color component signals are referred to by the generic designations U
and V, which may be assigned to either R-Y or B-Y signals, or I and Q
signals. The samples luminance bandwidth is limited to 8 MHz because the
system clock rate is 1024f.sub.H, which is approximately 16 MHz. A single
analog to digital converter and an analog switch can be used to sample the
color component data because the U and V signals are limited to 500 KHz,
or 1.5 MHz for wide I. The select line UV.sub.-- MUX for the analog
switch, or multiplexer 344, is an 8 MHz signal derived by dividing the
system clock by 2. A one clock wide start of line SOL pulse synchronously
resets this signal to zero at the beginning of each horizontal video line.
The UV.sub.-- MUX line than toggles in state each clock cycle through the
horizontal line. Since the line length is an even number of clock cycles,
the state of the UV.sub.-- MUX, once initialized, will consistently toggle
0, 1, 0, 1, . . . , without interruption. The Y and UV data streams out of
the analog to digital converters 342 and 346 are shifted because the
analog to digital converters each have 1 clock cycle of delay. In order to
accommodate for this data shift, the clock gating information from the
interpolator control 349 of main signal processing path 304 must be
similarly delayed. Were the clock gating information not delayed, the UV
data will not be correctly paired when deleted. This is important because
each UV pair represents one vector. A U element from one vector cannot be
paired with a V element from another vector without causing a color shift.
Instead, a V sample from a previous pair will be deleted along with the
current U sample. This method of UV multiplexing is referred to as 2:1:1,
as there are two luminance samples for every pair of color component (U,
V) samples. The Nyquist frequency for both U and V is effectively reduced
to one-half of the luminance Nyquist frequency. Accordingly, the Nyquist
frequency of the output of the analog to digital converter for the
luminance component is 8 MHz, whereas the Nyquist frequency of the output
of the analog to digital converter for the color components is 4 MHz.
The PIP circuit and/or the gate array may also includes means for enhancing
the resolution of the auxiliary data notwithstanding the data compression.
A number of data reduction and data restoration schemes have been
developed, including for example paired pixel compression and dithering
and dedithering. Moreover, different dithering sequences involving
different numbers of bits and different paired pixel compressions
involving different numbers of bits are contemplated. One of a number of
particular data reduction and restoration schemes can be selected by the
WSP .mu.P 340 in order to maximize resolution of the displayed video for
each particular kind of picture display format.
The gate array includes interpolators which operate in conjunction with
line memories, which may be implemented as FIFO's 356 and 358. The
interpolator and FIFO's are utilized to resample the main signal as
desired. An additional interpolator can resample the auxiliary signal.
Clock and synchronizing circuits in the gate array control the data
manipulation of both the main and auxiliary signals, including the
combination thereof into a single output video signal having Y.sub.-- MX,
U.sub.-- MX and V.sub.-- MX components. These output components are
converted to analog form by digital to analog converters 360, 362 and 364.
The analog form signals, designated Y, U and V, are supplied to the
1f.sub.H and 2f.sub.H converter 40 for conversion to noninterlaced
scanning. The Y, U and V signals are also encoded to Y/C format by encoder
227 to define a wide format ratio output signal Y.sub.-- OUT.sub.--
EXT/C.sub.-- OUT.sub.-- EXT available at panel jacks. Switch SW5 selects a
synchronizing signal for the encoder 227 from either the gate array,
C.sub.-- SYNC.sub.-- MN, or from the PIP circuit, C.sub.-- SYNC.sub.--
AUX. Switch SW6 selects between Y.sub.-- M and C.sub.-- SYNC.sub.-- AUX as
synchronizing signal for the wide screen panel output.
Portions of the horizontal synchronizing circuit are shown in more detail
in FIG. 14. Phase comparator 228 is part of a phase locked loop including
low pass filter 230, voltage controlled oscillator 232, divider 234 and
capacitor 236. The voltage controlled oscillator 232 operates at
32f.sub.H, responsive to a ceramic resonator or the like 238. The output
of the voltage controlled oscillator is divider by 32 to provide a proper
frequency second input signal to phase comparator 228. The output of the
divider 234 is a 1f.sub.H REF timing signal. The 32f.sub.H REF and
1f.sub.H REF timing signals are supplied to a divide by 16 counter 400. A
2f.sub.H output is supplied to a pulse width circuit 402. Presetting
divider 400 by the 1f.sub.H REF signal assures that the divider operates
synchronously with the phase locked loop of the video signals input
section. Pulse width circuit 402 assures that a 2f.sub.H -REF signal will
have an adequate pulse width to assure proper operation of the phase
comparator 404, for example a type CA1391, which forms part of a second
phase locked loop including low pass filter 406 and 2f.sub.H voltage
controlled oscillator 408. Voltage controlled oscillator 408 generates an
internal 2f.sub.H timing signal, which is used for driving the
progressively scanned display. The other input signal to phase comparator
404 is the 2f.sub.H flyback pulses or a timing signal related thereto. The
use of the second phase locked loop including phase comparator 404 is
useful for assuring that each 2f.sub.H scanning period is symmetric within
each 1f.sub.H period of the input signal. Otherwise, the display may
exhibit a raster split, for example, wherein half of the video lines are
shifted to the right and half of the video lines are shifted to the left.
The deflection circuit 50 is shown in more detail in FIG. 15. A circuit 500
is provided for adjusting the vertical size of the raster, in accordance
with a desired amount of vertical overscan necessary for implementing
different display formats. As illustrated diagrammatically, a constant
current source 502 provides a constant quantity of current I.sub.RAMP
which charges a vertical ramp capacitor 504. A transistor 506 is coupled
in parallel with the vertical ramp capacitor, and periodically discharges
the capacitor responsive to the vertical reset signal. In the absence of
any adjustment, current I.sub.RAMP provides the maximum available vertical
size for the raster. This might correspond to the extent of vertical
overscan needed to fill the wide screen display by an expanded 4.times.3
format display ratio signal source, as shown in FIG. 1(a). To the extent
that less vertical raster size is required, an adjustable current source
508 diverts a variable amount of current I.sub.ADJ from I.sub.RAMP, so
that vertical ramp capacitor 504 charges more slowly and to a smaller peak
value. Variable current source 508 is responsive to a vertical size adjust
signal, for example in analog form, generated by a vertical size control
circuit. Vertical size adjustment 500 is independent of a manual vertical
size adjustment 510, which may be implemented by a potentiometer or back
panel adjustment knob. In either event, the vertical deflection coil(s)
512 receive(s) driving current of the proper magnitude. Horizontal
deflection is provided b | | |
