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FIELD OF THE INVENTION
This invention relates to the manufacture of multi chip modules.
Specifically, this invention relates to an improved method for forming
multi chip modules and an improved multi chip module that includes an
interconnect having a substrate and self limiting contact members.
BACKGROUND OF THE INVENTION
Microelectronic packages called "multi chip modules" (MCMs) are constructed
with unpackaged semiconductor dice. With a multi chip module, a number of
dice are attached to a printed circuit board or other substrate and
electrically connected to form various circuits and electronic devices.
One reason for the increased use of multi chip modules is increased system
performance. In particular integrated circuits on multi chip modules can
be operated with lower resistance and parasitic capacitances. This is
largely a result of decreasing the interconnection length between the dice
included in the multi chip module. In addition overall system performance
is improved because the input/output ports can be configured to access the
whose module, which can be organized to reduce signal delays and access
times. The power requirements are also reduced due to a reduction in the
driver requirements.
Typically the dice are mounted on a substrate having an interconnect
pattern formed using a process such as screen printing. Different
techniques are used for mounting the dice to the substrate and for
providing interconnection and termination of the unpackaged dice. These
techniques include wirebonding, tape automated bonding (TAB), micro-bump
bonding and flip chip bonding.
With flip chip bonding, each die is mounted circuit side down, and bond
pads on the die are bonded to corresponding connection points on the
substrate. Flip chips are formed similarly to conventional dice but
require an additional process step to form solder bumps on the bond pads.
The solder bumps are typically formed with a height of 25 .mu.m to 75
.mu.m. The solder bumps separate the dice from the substrate and minimize
the actual contact between the dice and substrate.
One important consideration in constructing multi chip modules is the
electrical connection between the bond pads of the unpackaged dice and the
connection points on the substrate. It is important that these electrical
connections provide a low resistance or ohmic contact. Additionally, it is
preferable that each electrical connection be established with a minimum
amount of trauma to the dice and particularly to the bond pads of the
dice. The integrated circuits within a die can also be adversely affected
if heat or thermal cycling is used to make an electrical connection.
Another important consideration in fabricating multi chip modules is the
effect of thermal expansion on the electrical connections. If the dice and
substrate expand by a different amount, stress may develop at the
connection points and adversely effect the electrical connections.
Stresses from thermal expansion can also lead to damage of the dice and
substrate. For this reason silicon substrates are often used to construct
multi chip modules.
Another problem in the manufacture of multi chip modules is that the size
of semiconductor dice and the size and spacing of the bond pads on the
dice have become smaller. This makes mounting and interconnecting of the
dice on a substrate more difficult. In some electronic devices, such as
computers, it is often necessary to integrate a large number of dice into
an assembly to provide an extended memory or other component. This
compounds the problems outlined above. The present invention recognizes
that it is advantageous to construct multi chip modules using fabrication
techniques employed in semiconductor manufacture.
OBJECTS OF THE INVENTION
In view of the foregoing, it is an object of the present invention to
provide an improved method for forming multi chip modules and an improved
multi chip module.
It is another object of the present invention to provide an improved
interconnect for multi chip modules.
It is yet another object of the present invention to provide an improved
interconnect for multi chip modules having a contact structure with a self
limiting silicon tip.
It is a further object of the present invention to provide an improved
multi chip module in which dice are densely mounted to reduce the length
of the interconnect lines between dice.
Other objects, advantages and capabilities of the present invention will
become more apparent as the description proceeds.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method for forming a
multi chip module and an improved multi chip module are provided. The
multi chip module includes an interconnect for mounting one or more
singularized dice or dice contained on a semiconductor wafer. The
interconnect establishes an electrical connection to the dice and supports
the dice or wafer. In addition, the interconnect and dice can be packaged
together to provide a packaged assembly.
The interconnect includes a substrate and contact members formed on the
substrate. The substrate is formed of a semiconductor material, such as
silicon, having a thermal expansion coefficient that matches that of a
silicon die. The substrate and contact members are formed using
semiconductor fabrication techniques. The contact members are formed in a
pattern that matches the size and spacing of contact locations (e.g., bond
pads) on the dice. The contact members include one or more projections
adapted to penetrate the contact locations on the dice to establish an
electrical connection. The projections are formed with a size and shape
that permits penetration into the contact locations on the dice but with a
self-limiting penetration depth. In an illustrative embodiment, the
penetrating projections are formed as elongated blades with a flat tip.
The penetrating projections can also be formed as sharpened points and
other penetrating shapes.
The contact members and penetrating projections are formed integrally with
the interconnect substrate using an etching process or using an oxidation
growth process. The contact members are covered with a conductive layer.
The conductive layer can be formed as an inert metal, as a stack of
metals, as a metal silicide, or as a layer of polysilicon. The conductive
layer is in electrical communication with conductive traces formed on a
front side of the interconnect which terminate in contact pads along an
edge of the interconnect. The contact pads are connectable to bond wires
or other electrical connectors, which provide a conductive path to the
contact members.
The interconnect can be used to electrically interconnect, or integrate, a
large number of dice for use in various applications (e.g., electronics,
memory). With such an interconnect each die can be accessed separately
through a particular group of contact members. In addition, select contact
locations and dice can be included or excluded from an integration using a
particular conductive path or programmable links, such as fuses or anti
fuses, formed in a conductive path to the contact members.
One advantage of the interconnect is that high temperature processing steps
can be used on the interconnect because it is processed separately from
the dice or wafer containing the integrated circuitry. Low resistivity
materials, such as copper, can be used in forming the interconnect without
detriment to the integrated circuits formed on the dice. In addition, the
contact members can be formed with a size and density to accommodate a
dense arrangement of dice. This permits the multi chip module to be formed
with a reduced interconnection length between dice and a high ratio of
dice surface area to substrate area.
A method for forming a multi chip module, in accordance with the invention,
includes the steps of: forming an interconnect substrate; forming a
pattern of contact members on the substrate, the contact members including
one or more projections adapted to penetrate contact locations on a
semiconductor die to a limited penetration depth; forming an insulating
layer (e.g., SiO.sub.2, Si.sub.3 N.sub.4) on the substrate, contact
members and projections; forming a conductive layer on the contact
members; forming a conductive path on the substrate to the conductive
layer; assembling the interconnect with the contact members in permanent
mating engagement with contact locations on singulated dice or dice
contained on a wafer; and then optionally packaging the interconnect and
dice or wafer.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A shows a silicon substrate for the interconnect and a mask layer
formed on the substrate;
FIG. 1B shows a layer of photoresist deposited on the mask layer;
FIG. 1C shows the layer of photoresist after exposure and development;
FIG. 1D shows the mask layer after etching using the patterned layer
photoresist;
FIG. 1E shows the substrate after etching using the mask layer to form
projections having various profiles;
FIG. 1F shows the substrate and projections after stripping of the mask
layer;
FIG. 1G shows another mask layer formed on the etched substrate;
FIG. 1H shows a layer of photoresist formed on the mask layer;
FIG. lI shows the layer of photoresist and the mask layer after patterning
and etching;
FIG. 1J shows the substrate and mask layer over the projections following
removal of the layer of photoresist;
FIG. 1K shows the substrate etched using the mask layer to form a contact
member;
FIG. 1L shows the contact member following removal of the mask layer;
FIG. 1M shows the formation of an insulating layer on the contact member
and projection;
FIG. 1N shows the formation of a conductive layer on the contact member and
a conductive trace in electrical communication with the conductive layer;
FIG. 2 shows an alternate embodiment interconnect wherein a conductive
layer is formed as a metal silicide;
FIG. 3 shows an alternate embodiment interconnect wherein a conductive
layer is formed as a bi-metal stack;
FIG. 4A is a perspective view of a contact member formed in accordance with
the invention with an arrangement of projections;
FIGS. 4B-4F are plan views illustrating various other pattern arrangements
for the projections;
FIG. 5 is a schematic perspective view of a completed interconnect formed
in accordance with the invention;
FIG. 6 is a schematic perspective view, with parts removed, showing a multi
chip module formed in accordance with the invention and including an
interconnect and singularized dice attached to the interconnect;
FIG. 7 is an enlarged cross sectional view showing engagement of a contact
member on the interconnect with a bond pad on a die;
FIG. 8 is a plan view showing a multi chip module formed with a complete
semiconductor wafer;
FIG. 9 is a cross sectional view taken along section line 9--9 of FIG. 8;
FIG. 10 is an electrical schematic illustrating a programmable link in a
conductive path to the contact tips;
FIG. 11 is an exploded perspective view, with parts removed, of a multi
chip module formed in accordance with the invention and including a
ceramic base; and
FIG. 12 is a schematic cross sectional view of the multi chip module shown
in FIG. 11.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIGS. 1A-1N, a process for forming an interconnect 10 for
forming a multi chip module is shown. Initially, as shown in FIG. 1A, a
substrate 12 is formed of a material having a thermal expansion
coefficient that closely matches that of a silicon die. Suitable materials
for the substrate 12 include monocrystalline silicon, silicon-on-glass,
silicon-on-sapphire, germanium or ceramic.
The substrate 12 includes a planar outer surface 14. A mask layer 16 is
formed on the outer surface 14 of the substrate 12. The mask layer 16 can
be formed of a material, such as silicon nitride (Si.sub.3 N.sub.4), using
a suitable deposition process such as CVD. A typical thickness for the
mask layer 16 is about 500 .ANG. to 3000 .ANG..
Next, as shown in FIG. 1B, a layer of photoresist 18 is formed on the mask
layer 16. The layer of photoresist 18 can be deposited using a spin-on
process and then soft baked to drive out solvents. A typical thickness for
the layer of photoresist is about 10,000 .ANG. to 15,000 .ANG.. Following
the softbake, the layer of photoresist 18 is aligned with a mask and
exposed using collimated UV light.
Next, as shown in FIG. 1C, the layer of photoresist 18 is developed to form
a photoresist mask 20. For a positive resist, the development results in
the dissolution of the exposed photoresist but does not affect the
unexposed regions. For a negative resist, the development results in the
dissolution of the unexposed resist.
Next, as shown in FIG. 1D, the mask layer 16 is etched selective to the
substrate 12 to form a hard mask that includes masking blocks 22 and
openings 24 therebetween. Depending on the materials used for the mask
layer 16, this etch step may be performed using a wet or dry etch.
The photoresist mask 20 is removed using a suitable chemical solvent. For a
positive resist a solvent such as acetone, methylethylketone or
1-methylethylketone can be used. For a negative resist a solution of
concentrated H.sub.2 SO.sub.4 and H.sub.2 O.sub.2 at about 150.degree. C.
can be used. Such an etch is referred to in the art as a "piranha" etch.
Viewed from above the masking blocks 22 are elongated rectangular blocks
formed in a parallel spaced pattern. The peripheral dimensions of the
pattern of masking blocks 22 are selected to fall within the peripheral
area of a contact location on a semiconductor die. As an example, the
contact location on the die can be a polygonal shaped bond pad (e.g.,
rectangular or triangular shaped pad) that is about 50-100 .mu.m on a
side. However, as will be more fully explained, such a parallel spaced
pattern of masking blocks 22 is merely exemplary and other patterns or
configurations are possible.
Next, as shown in FIG. 1E, penetrating projections 26 are formed on the
substrate 12 by etching the exposed substrate 12 between the masking
blocks 22. With etching, a dry or wet isotropic, or anisotropic, etch
process is used to form the projections 26 as the material under the
masking blocks 22 is undercut by the etchant reacting with the substrate
12. In other words, the exposed substrate 12 between the masking blocks 22
etches faster than the covered substrate 12 under the blocks 22.
For a wet anisotropic etch, in which the etch rate is different in
different directions, an etchant solution containing a mixture of KOH and
H.sub.2 O can be utilized. This results in the projections 26 having
sidewalls 28 that are sloped at an angle of approximately 54.degree. with
the horizontal. The slope of the sidewalls 28 is a function of the
different etch rates of monocrystalline silicon along the different
crystalline orientations. The surface of the substrate 12 represents the
(100) planes of the silicon which etches faster than the sloped sidewalls
28 that represent the (111) plane.
In addition to sloped sidewalls 28, the projections 26 include a flat tip
portion 30 (FIG. 1F). The width of the tip portion 30 is determined by the
width of the masking blocks 22 and by the parameters of the etch process.
As also shown by the lower left hand portion of FIG. 1E, the width of the
masking blocks 22A and etch parameters can also be controlled to form
projections 26A having a pointed tip.
As also shown in FIG. 1E, a wet isotropic etch can be used to form
projections 26B having radiused sidewalls 28B. For an isotropic etch in
which the etch rate is the same in all directions, an etchant solution
containing a mixture of HF, HNO.sub.3 and H.sub.2 O can be utilized. This
results in projections 26B having a pointed tip and a rounded sidewall
contour. In this embodiment the sidewalls 28B of the projections 26B are
undercut below the masking blocks 22B with a radius "r". The value of the
radius "r" is controlled by the etch parameters (i.e., time, temperature,
concentration of etchant) and by the width of the masking blocks 22B.
In addition, FIG. 1E illustrates another embodiment wherein the projections
26C are formed in a saw tooth array with no spaces between the base
portions. In this embodiment a wet anisotropic etch is used and the
process parameters, including the etch time and width of the masking
blocks 22C, are controlled to provide a desired height and tip to tip
spacing.
Alternately, in place of an isotropic or anisotropic etch process, the
projections can be formed using an oxidizing process. This is also shown
in FIG. 1E at the lower right hand corner. With an oxidizing process the
substrate 12 may be subjected to an oxidizing atmosphere to oxidize
exposed portions of the substrate 12 not covered by the masking blocks 22.
As an example, the oxidizing atmosphere may comprise steam and O.sub.2 at
an elevated temperature (e.g., 950.degree. C.). The oxidizing atmosphere
oxidizes the exposed portions of the substrate 12 and forms an oxide layer
27 (e.g., silicon dioxide). When the oxide layer 27 is stripped the
resultant structure includes projections 26. With an oxidizing process,
the grown oxide layer can be stripped using a suitable wet etchant such as
HF.
The projections 26 can also be formed by a deposition process out of a
different material than the substrate 12. As an example, a CVD process can
be used to form the projections out of a deposited metal.
Following formation of the projections 26, and as shown in FIG. 1F, the
masking blocks 22 are stripped. Masking blocks 22 formed of silicon
nitride can be stripped using a wet etchant such as H.sub.3 PO.sub.4 that
is selective to the substrate 12. The projections 26 project from a
surface 32 of the substrate 12 and include flat tips 30 and bases 34. The
bases 34 of adjacent projections 26 are spaced from one another a distance
sufficient to define a penetration stop plane 36 there between. The
function of the penetration stop plane 36 will be apparent from the
continuing discussion. Example spacing between bases 34 would be about 10
.mu.m, while an example length of the projections 26 (i.e., dimension
perpendicular to the cross section shown) would be from 3 to 10 .mu.m. The
height of each projection 26 is preferably about 1/10 to 1/2 the thickness
of a bond pad on a semiconductor die. The projection 26 will therefore not
completely penetrate the full thickness of the bond pad. In addition, this
height is selected to allow good electrical contact but at the same time
to minimally damage the bond pad. As an example, the height of each
projection 26 measured from the top of the substrate 12 to the tip of the
projection 26 will be on the order of 2000-5000 .ANG.. This compares to
the thickness of a bond pad that is typically on the order of 6000 to
10,000 .ANG..
Following the formation of the projections 26 and as shown in FIG. 1G, a
mask layer 38 is formed on the substrate 12 and projections 26. The mask
layer 38 can be formed of a material, such as silicon nitride (Si.sub.3
N.sub.4), using a suitable deposition process such as CVD. A typical
thickness for the mask layer 38 is about 500 .ANG. to 3000 .ANG..
Next, as shown in FIG. 1H, a layer of photoresist 40 is formed on the mask
layer 38. The layer of photoresist 40 is baked, aligned and developed as
previously described to form a photomask 42 (FIG. 1I).
Next, as shown in FIG. 1I and 1J, the mask layer 38 is etched and the
photomask 42 is stripped to form a hard mask 44. The mask layer 44 is laid
out to form contact members that correspond to the placement of contact
locations (e.g., bond pads) on a semiconductor die. For a mask layer 38
formed of silicon nitride a dry etch process can be used to etch the mask
layer 38 to form the hard mask 44. Suitable dry etchant species include a
CL and NF.sub.3 mixture. A wet etchant can also be utilized to remove the
mask layer 44. The resist photomask 42 can be removed using a piranha etch
as previously described.
Next, as shown in FIG. 1K, the substrate 12 is etched around the hard mask
44 to form contact members 46. Typical etching techniques comprise wet
anisotropic etching with a mixture of KOH:H.sub.2 O. This type of etching
is also known in the art as bulk micro-machining. With an anisotropic etch
the sidewalls 48 of the contact members 46 will be sloped at an angle of
about 54.degree. with the horizontal. This forms a the contact member 46,
which is generally pyramidally shaped with a truncated tip.
The contact members 46 are sized and shaped to contact a bond pad of a
semiconductor die. Each contact member 46 viewed from above has a
generally square rectangular peripheral configuration and is dimensioned
to fall within the perimeter of a bond pad. The contact members 46 can
also be formed in other cross sectional configurations such as triangular,
polygonal or circular. The height of each contact member 46 can be varied
dependent on the application. One factor is the cleanliness of the
environment. The height of the contact member can be selected to provide
clearance for particulate contaminates from coming between the die and
interconnect. By way of example and not limitation the height of the
contact members 46 can be on the order of 0.5-100 .mu.m and the width on
each side about 40-80 .mu.m. The spacing of adjacent contact members 46
matches the spacing of adjacent bond pads on a semiconductor die (e.g., 50
to 100 .mu.m).
Next, as shown in FIG. 1L, the hard mask 44 is removed using a wet etch.
For a hard mask 44 formed of silicon nitride, an etchant, such as H.sub.3
PO.sub.4, that is selective to the substrate 12 can be used.
Next, as shown in FIG. 1M, an insulating layer 50 is formed on the
substrate 12 and over the projections 26 and sidewalls 48 thereof. The
insulating layer 50 is formed by oxidation of the substrate 12 and may be
accomplished by exposing the substrate 12 to an oxidizing atmosphere in a
reaction chamber. Silicon dioxide can also be deposited using CVD. TEOS
(tetraethylorthosilane) can be injected into the reaction chamber to grow
silicon dioxide (SiO.sub.2) at a temperature of about 400.degree. C. A
representative thickness for the insulating layer 50 is from about 500
.ANG. to 8000 .ANG.. Another commonly used insulator suitable for this
purpose is Si.sub.3 N.sub.4.
Next, as shown in FIG. 1N, a conductive layer 52 is formed on the contact
members 46 and over the projections 26. The conductive layer 52 can be
formed of a highly conductive metal such as aluminum (Al), copper (Cu) or
alloys of these metals. Other suitable metals include the refractory
metals, such as titanium (Ti), tungsten (W), tantalum (Ta), platinum (Pt)
and molybdenum (Mo). Other suitable metals include cobalt (Co), nickel
(Ni), molybdenum (Mo), gold (Au) and iridium (Ir).
The conductive layer 52 can be formed using a metallization process
including deposition (e.g., CVD), followed by photopatterning and etching.
Conductive traces 80 can also be formed at the same time, of the same
metal, and using the same metallization process. Alternately, the metal
conductive layer 52 and conductive traces 80 can be formed of different
(or the same) metals using separate metallization processes (e.g., CVD
deposition, photopatterning, etching). The conductive layer 52 and
conductive traces 80 establish an electrical path from the outside world
to the bond pads subsequently placed into contact with the contact members
46. This conductive path will come through the input/output ports of the
subsequently formed multi chip module.
The photopatterning process for forming the conductive layer 52 and
conductive traces 80 can be a standard process in which the photoresist
layer is spun on, soft baked and then patterned with UV energy.
Electrophoretic deposition processes wherein photoresist formulations are
deposited by electrodeposition can also be employed. With such a process,
a thin metal layer is blanket deposited on the substrate to be
photopatterned and then biased with a potential in an electrolytic bath.
The electrolytic bath includes a solution of photoresist formulated to
deposit onto the metal layer.
The conductive layer 52 can also be formed of polysilicon. As an example,
an LPCVD process can be used to form a conductive layer 52 out of
polysilicon doped with phosphorus.
Alternately, as shown in FIG. 2, an interconnect 10S can be formed with a
metal silicide conductive layer 52S. The metal silicide conductive layer
52S can be formed by depositing a silicon containing layer 58 (e.g.,
polysilicon, amorphous silicon) and a metal layer 60, and reacting these
layers to form a metal silicide. A typical thickness of the silicon
containing layer 58 would be from about 500 .ANG. to 3000 .ANG..
The metal layer 60 is formed of a metal that will react with the silicon
containing layer 58 to form a metal silicide. Suitable metals include the
refractory metals, such as titanium (Ti), tungsten (W), tantalum (Ta),
platinum (Pt) and molybdenum (Mo). In general, silicides of these metals
(WSi.sub.2, TaSi.sub.2, MoSi.sub.2, PtSi.sub.2 and TiSi.sub.2) are formed
by alloying with a silicon surface. Other suitable metals include cobalt
(Co), nickel (Ni), molybdenum (Mo), copper (Cu), gold (Au) and iridium
(Ir).
Following deposition of the metal layer 60, a sintering process is
performed in which the metal layer 60 is heated and reacts with the
silicon containing layer 58 to form the metal silicide layer 52S. This
type of sintering process is also known in the art as silicide or salicide
sintering. Such a sintering step can be performed by heating the silicon
containing layer 58 and metal layer 60 to a temperature of about
650.degree. to 820.degree. C. for typical thicknesses in thousands of
angstroms (e.g., 2000 .ANG.-3000 .ANG.). This sintering process can be
performed in one single step or using multiple temperature steps. The
metal silicide layer 52S forms at the interface of the metal layer 60 and
the silicon containing layer 58.
The unreacted portions of the metal layer 60 and the silicon containing
layer 58 are removed while the metal silicide layer 52S is left intact.
This can be done by etching the metal layer 60 and silicon containing
layer 58 selective to the metal silicide layer 52S. By way of example, for
a TiSi.sub.2 silicide layer, the unreacted titanium can be removed with a
wet etchant such as a solution of ammonia and hydrogen peroxide, or a
H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 mixture, that will attack the metal
layer 60 and not the metal silicide layer 52S. Alternately, a dry etch
process with an etchant species such as Cl.sub.2 or BCl.sub.3 can be used
to etch the metal layer 60 selective to the metal silicide layer 52S.
For etching the unreacted portion of the silicon containing layer 58
selective to the metal silicide layer 52S, a wet etchant such as an
HF:HNO.sub.3 :H.sub.2 O acid mixture (typical ratios of 1:10:10) can be
used to remove the unreacted silicon. A wet isotropic etchant can also be
used for this purpose. Alternately, the silicon containing layer 58 can be
etched selective to the metal silicide layer 52S using a dry etch process
and an etchant such as NF.sub.3 at low pressures (typically 30 m torr) or
CL.sub.2 and HBr at 130 m torr.
Following formation of the metal silicide layer 52S, the resistivity of the
metal silicide layer 52S can be lowered using an annealing process. This
can be accomplished by heating the substrate 10 and metal silicide layer
52S to a temperature of between about 780.degree. C. to 850.degree. C. for
several minutes. Conductive traces 80S are formed in contact with the
metal silicide layer 52S using a suitable deposition process. Co-pending
application Ser. No. (92-680.1) incorporated herein by reference describes
such a metal silicide layer 52S in greater detail.
Alternately, as shown in FIG. 3, an interconnect 10B can be formed with a
bi-metal conductive layer 52B. The bi-metal conductive layer 52B includes
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