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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to picture processing systems and more
particularly to a system for decoding pictures encoded in accordance with
an MPEG standard.
2. Discussion of the Related Art
FIG. 1 represents the main elements of an MPEG decoder 8. All MPEG
decoders, especially for the MPEG-2 standard, generally include a variable
length decoder (VLD) 10, a run-level decoder (RLD) 11, an inverse
quantizer circuit (Q.sup.-1) 12, an inverse discrete cosine transform
circuit (DCT.sup.-1) 13, a half-pixel filter 14, and a memory 15. The
encoded data are provided to the decoder via a bus CDin and the decoded
data are output via a bus VIDout. Between the input and the output, the
data pass through processing circuits 10-13 in the order indicated above,
which is illustrated by arrows in dashed lines. The decoder output is
provided by an adder 16 that sums the outputs of filter 14 and of the
cosine transform circuit 13. The filter 14 needs a portion of a previously
decoded picture stored in memory 15.
FIG. 2A illustrates a decoding step of a portion of a currently
reconstructed picture IM1. Picture decoding is carried out one macro-block
at a time. A macro-block generally corresponds to one 16.times.16-pixel
picture block.
FIG. 2B illustrates an exemplary format, noted 4:2:0, of a macro-block MB.
The macro-block MB includes a luminance block formed by four
8.times.8-pixel blocks Y1-Y4 and by one chrominance block formed by two
8.times.8-pixel blocks U and V. An alternative format is the 4:2:2 format
where the chrominance block includes two 8.times.16-pixel blocks.
In the current picture IM1 of FIG. 2A, a current macro-block MBc is being
decoded, the macro-blocks that were previously decoded being represented
by hatched lines. Generally, macro-block MBc is reconstructed by using a
predictor macro-block MBp fetched in a previously decoded picture IM0. To
find the predictor macro-block MBp, the data that serve to decode
macro-block MBc provide a movement compensation vector V that defines the
position of the predictor macro-block MBp with respect to the position P
of macro-block MBc in the picture.
The predictor macro-block MBp is fetched in the memory 15 that stores the
previously decoded picture IM0, and is provided to filter 14 while the
cosine transform circuit 13 processes data corresponding to the
macro-block MBc.
The decoding described above is a so-called "predicted" decoding. The
decoded macro-block is also referred to as being of predicted type. In
accordance with MPEG standards, there are three main types of decoding,
referred to as "intra", "predicted", and "bidirectional".
An intra macro-block directly corresponds to a picture block, that is, the
intra macro-block is not combined with a predictor macro-block when it is
output from the cosine transform circuit 13.
A predictor macro-block, as described above, is combined with one
macro-block of a previously decoded picture, and that comes, in the
display order, before the currently reconstructed picture.
A bidirectional macro-block is combined with two predictor macro-blocks of
two previously decoded pictures, respectively. These two pictures are
respectively former (forward) and subsequent (backward) pictures, in the
display order, with respect to the currently reconstructed picture. Thus,
encoded pictures arrive in an order different from the display order.
In addition, each predicted or bidirectional macroblock is of a progressive
or an interlaced type. When the macro-block is progressive, the DCT.sup.-1
circuit provides the lines of the macro-block in successive order. When
the macro-block is interlaced, the DCT.sup.-1 circuit first provides the
even lines of the macro-block, then the odd lines. In addition, the
predictor macro-block that serves to decode a predicted or bidirectional
macro-block is also of the progressive or interlaced-type. When the
predictor macro-block is of the interlaced-type, it is partitioned into
two half-macro-blocks; one half macro-block corresponds to even lines, and
the other half macro-block corresponds to odd lines, each half macro-block
being fetched at different positions in a same previously decoded picture.
A picture is also of the intra, predicted or bidirectional type. An intra
picture contains only intra macro-blocks; a predicted picture contains
intra or predicted macro-blocks; and a bidirectional picture contains
intra, predicted or bidirectional macro-blocks.
To provide the various decoding parameters to the various circuits of the
decoder, especially vectors V and the macro-block types, the flow of
encoded data includes headers. There are several types of headers:
a picture sequence header that includes in particular two quantizer tables
to provide to the inverse quantizer circuit 12, one serving for the intra
macro-blocks of the sequence, and the second serving for the predicted or
bidirectional macro-blocks;
a group of picture header, that does not include useful data for decoding;
a picture header that includes the type (predicted, intra, bidirectional)
of the picture and information on the use of the movement compensation
vectors;
a picture slice header including error correction information; and
a macro-block header including the macro-block's type, a quantizer scale to
be provided to the inverse quantizer circuit 12, and the components of the
movement compensation vectors. Up to four vectors are provided when
processing an interlaced bidirectional macro-block.
In addition, the high hierarchy headers (picture, group, sequence) can
include private data serving, for example, for on-screen display. Some
private data can also be used by components external to the decoder.
The various processing circuits of an MPEG decoder are frequently arranged
in a pipeline architecture which can process high data flow rates but
which is very complex and inflexible, that is, which is difficult to adapt
to modifications of the standards and which is inadequate to exploit
on-screen display and private data.
The simplest and most inexpensive solution is to couple the various
processing circuits to the memory through a common bus that is controlled
by a multi-task processor.
Patent application EP-A-0,503,956 (C-Cube) describes such a system
including a processor that controls transfers of data on the bus and three
coprocessors that execute the processing steps corresponding to circuits
10-14. Each type of transfer to be achieved via the bus corresponds to a
task carried out by the processor. All tasks are concurrent and are
executed at processor interrupts generated by the coprocessors. The
coprocessors exchange the data to be processed and receive the
instructions provided by the processor via the bus.
This system is simple, but it is incapable of handling the high data flow
rates needed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a particularly fast
picture decompression system with a relatively simple structure.
Another object of the invention is to provide such a decompression system
that can be easily connected in parallel with identical decompression
systems in order to process very high data flow rates.
To achieve these objects, the invention provides a decoder of composite
architecture, that is, some of the processing elements are connected
together and to a picture memory through a first bus, and some other
elements are connected in a pipeline architecture. These other elements
are referred to hereinafter as a "pipeline circuit". A second bus is
provided to supply data to be processed to the first element of the
pipeline circuit as well as the required decoding parameters to the
elements of the system.
With this structure, the pipeline circuit processes data serially without
it being necessary to exchange them with the memory through the first bus.
In addition, the first bus is relieved of the transmission of decoding
parameters, these parameters being transmitted by the second bus. Thus,
the number of exchanges on the first bus corresponding to a given decoding
step is substantially reduced, which increases the system's performance.
The system has a high flexibility resulting from the use of a bus system.
This flexibility is increased by an optimal choice of the elements to be
included in the pipeline circuit.
The present invention more particularly addresses a system for processing
compressed data arriving in packets corresponding to picture blocks, these
packets being separated by headers containing decoding parameters of the
packets. The system includes a plurality of processing elements using said
decoding parameters, and a memory bus controlled by a memory controller to
exchange data between the processing elements at rates adapted to the
processing rates of these elements, and to store in a picture memory data
to be processed or re-used. The system includes a pipeline circuit
containing a plurality of processing elements connected to process packets
serially, and a parameter bus to provide packets to be processed to the
pipeline circuit, as well as the decoding parameters to elements of the
system. The parameter bus is controlled by a master processing element
that receives the compressed data from the memory bus and that extracts
the packets and the decoding parameters therefrom.
According to an embodiment of the invention, each packet of compressed data
is preceded by a block header, and the packets come in successive groups,
each group of packets being preceded by a group header containing group
decoding parameters as well as, possibly, private and on-screen display
information. The system further includes a processor bus controlled by a
microprocessor to supply the group decoding parameters and the private and
on-screen display information to the system elements requiring them; a
buffer memory accessible by the processor bus, receiving the compressed
data through the memory bus; and a group header detector cooperating with
this buffer memory to generate interrupts of the microprocessor.
According to an embodiment of the invention, a transfer of data between two
elements connected to the memory bus corresponds to a specific task that
is initiated or continued when one of the two elements issues a request to
provide or to receive data, all the possible tasks being concurrent tasks
that are carried out by the memory controller according to a task priority
management.
According to an embodiment of the invention, the elements which exchange
data with the picture memory are connected to the memory bus through
respective write- or read-only buffer memories. A write-only buffer memory
is emptied by the associated element and issues a request to receive data
through the memory bus when its content reaches a lower limit. A read-only
buffer memory is filled by the associated element and issues a request to
provide data on the memory bus when its content reaches an upper limit.
According to an embodiment of the invention, the system includes a variable
length decoder (VLD) forming the master processing element; a run-level
decoder (RLD) forming a first element of the pipeline circuit and
receiving through the parameter bus the packets processed by the VLD; an
inverse quantizer circuit forming a second element of the pipeline circuit
and receiving quantizer scale coefficients through the parameter bus; an
inverse cosine transform circuit forming a third element of the pipeline
circuit; the memory controller receiving movement compensation vectors
through the parameter bus; a filter receiving block types through the
parameter bus, this filter issuing distinct requests, according to the
block types, to receive corresponding data provided on the memory bus as a
function of the vectors received by the memory controller; and an adder to
provide on the memory bus the sum of the outputs of the filter and of the
cosine transform circuit.
According to an embodiment of the invention, the group header detector
generates interruptions of the microprocessor when the associated buffer
memory contains a picture sequence header or a picture header, the
microprocessor being programmed to respond to these interruptions by
reading, in the buffer memory associated with the group header detector,
quantizer tables that the microprocessor provides to the inverse quantizer
circuit, information on the picture type and on the amplitude of the
movement compensation vectors that the microprocessor provides to the VLD,
and information on the display configuration that the microprocessor
provides to a display controller which receives the decoded data through
the memory bus.
According to an embodiment of the invention, the memory controller includes
an instruction memory (independent of the memory bus), in which are stored
the program instructions corresponding respectively to transfer tasks on
the memory bus; an instruction processing unit that is connected to the
instruction memory in order to receive therefrom successive instructions
to be executed, and that is connected to act on the memory bus in response
to these instructions; a plurality of instruction pointers associated
respectively to possible tasks and each including the current instruction
address to be executed of the associated task, one only of these pointers
is enabled at a time to provide its content as an instruction address to
the instruction memory; a priority decoder assigning a predetermined
priority level to each request and enabling the instruction pointer
associated with the active request having the highest priority level; and
means for incrementing the content of the enabled instruction pointer and
for reinitializing it at the address of the associated program start when
its content reaches the end address of the associated program.
According to an embodiment of the invention, each instruction includes a
command field that is provided to the processing unit and a feature field
provided to a prefix decoder that includes means for authorizing the
enabling of a new instruction pointer by the priority decoder if the
feature field of the current instruction is at a first predetermined
value, and means for initializing the content of the enabled instruction
pointer to the start address of the current program if the feature field
of the current instruction is at a second predetermined value.
According to an embodiment of the invention, the prefix decoder includes
means for inhibiting the incrementation of the enabled instruction pointer
if the feature field is at a third predetermined value, so that the
current instruction is executed consecutively several times, the number of
executions being determined by this third value.
According to an embodiment of the invention, each instruction includes a
command field that is provided to the instruction processing unit and an
acknowledge field that is provided to means for, when the instruction is
being executed, enabling at least one buffer memory connected to the
memory bus.
According to an embodiment of the invention, the processing unit includes a
plurality of hard wired functions for the calculation of addresses, each
function being selected by a field of a read or write instruction that is
being executed.
According to an embodiment of the invention, with each hard wired function
is associated an address register connected to the memory bus; the hard
wired function suitably modifies the content of its address register each
time an instruction is executed in the processing unit.
The present invention also addresses a system for processing compressed
data corresponding to pictures, including decoding means that provide
decoded picture data to a picture memory, these means requiring, for
decoding a current block of a picture being reconstructed, a predictor
block of a previously decoded picture. In fact, the processing system
includes a plurality of decoders associated with respective picture
memories, each storing a specific slice of corresponding blocks of a
plurality of pictures, as well as at least one margin in which is liable
to be a predictor block used for reconstructing a block of the specific
slice.
According to an embodiment of the invention, each considered decoder
includes means for storing in its picture memory, as a margin, a boundary
area of at least one additional specific slice and for providing to at
least one second decoder, as a margin, a boundary area of the specific
slice associated with the considered decoder.
According to an embodiment of the invention, each considered decoder
includes a first buffer memory receiving picture blocks from the specific
slice; at least one second buffer memory receiving picture blocks from an
adjacent area of another specific slice; a terminal processing circuit
providing the blocks of the specific slice to the first buffer memory of
the considered decoder and to the second buffer memory of another decoder;
and a memory controller to read the blocks in the first buffer memory and
to write them in the picture memory at addresses corresponding to the
specific slice, and to read the blocks in the second buffer memory and to
write them at addresses corresponding to a margin.
According to an embodiment of the invention, each second buffer memory is
preceded by a barrier circuit in order to store in the second buffer
memory only the data corresponding to the desired margin.
According to an embodiment of the invention, the pictures to be processed
are high definition television pictures that are partitioned in horizontal
slices of equal height.
The foregoing and other objects, features, aspects and advantages of the
invention will become apparent from the following detailed description of
the present invention which should be read in conjunction with the
accompanying drawings.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1, above described, shows the main elements of an MPEG decompression
system;
FIG. 2A illustrates a decoding step of a macro-block;
FIG. 2B represents an exemplary macro-block structure;
FIG. 3 represents an embodiment of a decompression system architecture, or
MPEG decoder, according to the invention;
FIG. 4 is a timing diagram illustrating the operation of the decompression
system of FIG. 3;
FIG. 5 represents an advantageous embodiment of a memory controller
according to the invention;
FIG. 6 represents another embodiment of a decompression system architecture
according to the invention;
FIG. 7 illustrates a high definition television picture that is to be
processed by slices by a plurality of parallel decompression systems;
FIG. 8 represents a plurality of decompression systems connected in
parallel to process a high definition picture; and
FIG. 9 partially represents an embodiment of an internal structure of a
decoder according to the invention that allows an easy parallel connection
.
GENERAL ARCHITECTURE OF THE MPEG DECODER
In FIG. 3, the elements already shown in FIG. 1 are designated with the
same reference numerals.
A bus, hereinafter memory bus MBUS, couples the picture memory 15 to the
compressed data input bus CDin, to the input of the variable length
decoder (VLD) 10, to the input of the half-pixel filter 14, and to the
input of a display controller 18. Bus CDin, decoder 10 and display
controller 18 are connected to the memory bus MBUS through respective
buffer memories (FIFOs) 20, 21, and 22. The half-pixel filter 14 includes
two internal FIFOs that are connected to the memory bus MBUS. Exchanges on
the memory bus MBUS are controlled by a memory controller (MCU) 24 that
serves to carry out, upon request of the FIFOs, transfer operations
between these FIFOs and the picture memory. To achieve this purpose, the
memory controller 24 receives a plurality of requests RQ and provides
corresponding acknowledgements ACK. The memory controller 24 can be such
as the one described in the above patent application EP-A-0,503,956. A
more advantageous embodiment of this memory controller will be described
hereinafter.
According to the invention, the run-level decoder (RLD) 11, the inverse
quantizer circuit (Q.sup.-1) 12, and the inverse discrete cosine transform
circuit (DCT.sup.-1) 13 are connected according to a pipeline
architecture, that is, these circuits 11-13 successively process data to
decode, without these data temporarily transitting through a memory 15.
The set of circuits 11-13 is referred to as a pipeline circuit
hereinafter. The output of the half-pixel filter 14 is summed to the
output of the DCT.sup.-1 circuit 13 by an adder 16 that is coupled to the
bus MBUS through a FIFO 26 controlled by the memory controller 24.
Hand-shake lines HS1 and HS2 connect the adder 16 to the VLD circuit and
to the DCT.sup.-1 circuit, respectively.
According to an aspect of the invention, the VLD circuit 10 controls a bus
VLDBUS intended to provide to the RLD circuit 11 data to be processed by
the pipeline circuit 11-13, as well as parameters to the half-pixel filter
14, to the inverse quantizer circuit 12, to the display controller 18, and
to the memory controller 24. A VLD circuit generally decodes the headers
of the compressed data that it receives. As mentioned above, these headers
include decoding parameters to be provided to the various elements of the
system.
A macro-block header includes a quantizer scale to provide to the inverse
quantizer circuit 12, a macro-block type parameter, and the components of
the movement compensation vectors. These decoding parameters are decoded
by the VLD circuit and respectively written in specific registers of the
inverse quantizer circuit 12, of the half-pixel filter 14, and of the
memory controller 24.
A picture header includes, as mentioned above, a picture type parameter and
information on the use of the movement compensation vectors. These
parameters are used by the VLD circuit itself to decode the vectors and
data of the macro-blocks.
A sequence header includes two quantizer tables that are extracted by the
VLD circuit and provided to two respective registers of the inverse
quantizer circuit 12. The picture headers contain scaling or truncating
parameters concerning the displayed picture, that are decoded by the VLD
circuit and provided to the display controller 18.
The VLD circuit executes write operations on the bus VLDBUS as it decodes
the headers. The write operations of the VLD circuit on bus VLDBUS can be
interrupted by the RLD circuit 11 when the latter can no longer receive
data to be processed. This is represented by a hand-shake connection HS3.
A sequencer 28 provides an enable signal EN of the VLD circuit. Sequencer
28 receives display (horizontal, vertical) synchronization signals H/VSYNC
through the display controller 18, a macro-block synchronization signal
MBS from the half-pixel filter 14, and an end of picture signal EOP from
the VLD circuit 10. The sequencer 28 provides the memory controller 24
with a picture synchronization signal ISYNC that is active when the end of
picture signal EOP and the vertical synchronization signal VSYNC are both
active. The role of sequencer 28 will be explained subsequently.
As previously indicated, to reconstruct a picture, it is often necessary to
use picture portions of two previously decoded pictures. To achieve this
purpose, memory 15 must include three picture areas IM1, IM2, and IM3 to
store the currently reconstructed picture and two previously decoded
pictures. Memory 15 further includes an area CD to temporarily store
compressed data arriving on bus CDin prior to being processed.
Control of the picture memory areas
To know in which memory areas IM1-IM3 the memory controller 24 must write,
the latter uses four picture pointers ImPt provided by the VLD circuit.
The VLD circuit includes a unit for calculating the picture pointers from
the picture type parameters that are provided by the picture headers.
Hereinafter, an exemplary picture succession and the method for
calculating the picture pointers are described.
Consider the following succession of compressed pictures arriving on bus
CDin:
I0, P1, B2, B3, P4, B5, B6
where letters I, P and B respectively designate an intra picture, a
predicted picture, and a bidirectional picture. According to MPEG
standards, a bidirectional picture cannot be used to calculate another
picture. Thus, the reconstruction of picture P1 requires picture I0, the
reconstruction of pictures B2 and B3 requires pictures I0 and P1, the
reconstruction of picture P4 requires picture P1, and the reconstruction
of pictures B5 and B6 requires pictures P4 and P1.
These pictures are displayed in the following order:
I0, B2, B3, P1, B5, P4, B6
since a predicted picture P is reconstructed from a former picture in the
display order, and since a bidirectional picture B is reconstructed from
two pictures, one former and the other subsequent in the display order.
To determine the memory area IM1-IM3 which the memory controller 24 must
access, four picture pointers RP, FP, BP, and DP are used, respectively
indicating the locations of the currently reconstructed picture, of the
former (forward) picture, of the subsequent (backward) picture, and of the
currently displayed picture. The following table sums up the values of the
picture pointers during the decoding of the above succession.
______________________________________
Decode I0 P1 B2 B3 P4 B5
Display -- I0 B2 B3 P1 B5
______________________________________
RP IM1 IM2 IM3 IM3 IM1 IM3
FP -- IM1 IM1 IM1 IM2 IM2
BP -- -- IM2 IM2 -- IM1
DP -- IM1 IM3 IM3 IM2 IM3
______________________________________
When the first picture I0 is decoded, no picture is displayed yet. The
reconstructed picture pointer RP indicates an empty area, for example area
IM1, to store picture I0.
When picture P1 is decoded, picture I0 must be displayed. The reconstructed
picture pointer RP indicates for example area IM2, and the displayed
picture pointer DP indicates the area IM1 in which picture I0 is located.
Since the predicted picture P1 needs the forward picture I0 in its
reconstruction, the forward picture pointer FP also indicates area IM1.
When the bidirectional picture B2 is decoded, this picture B2 is also the
picture to be displayed, The reconstructed picture pointer RP and the
displayed picture DP both indicate the area IM3 that is still free. In its
decoding, picture B2 needs the forward picture I0 and the backward picture
P1; the forward picture pointer FP and the backward picture BP indicate
areas IM1 and IM2, respectively.
To be able to display a picture as it is being decoded, the effective
display is generally delayed by approximately one half picture; the area
IM3 is sufficiently filled when picture B2 starts to be displayed.
When picture B3 is decoded, it is also the picture to be displayed. Since
picture B3 also needs pictures I0 and P1 in its decoding, pictures I0 and
P1 remain stored in the areas IM1 and IM2 that are still indicated by of
the forward picture FP and backward picture BP pointers. Picture B3 can
only be stored in area IM3, that is indicated by the reconstructed picture
RP and the displayed picture DP pointers.
However, when picture B3 sharks to be reconstructed in area IM3, the
picture B2, that is also stored in area IM3, is being displayed. If the
displayed picture B2 is liable to be overwritten by the reconstructed
picture B3, the VLD circuit that is providing the data of picture B3 is
stopped. The role of the above sequencer 28 is to stop the VLD circuit by
disabling the enable signal EN when the number of decoded macro-blocks
corresponds to a picture fraction greater than the displayed picture
fraction. The size of this fraction is determined by counting the number
of horizontal synchronization pulses HSYNC and the number of decoded
macro-blocks is determined by counting the number of macro-block
synchronization pulses MBS.
When picture P4 is being decoded, picture P1 must be displayed. Picture P4
is stored in area IM1 that is then free; the reconstructed picture pointer
RP indicates area IM1; the displayed picture pointer DP indicates area IM2
where picture P1 is stored. Picture P4 needs the forward picture P1 in its
decoding; the forward picture pointer FP indicates area IM2.
When picture B5 is decoded, it must also be displayed. Picture B5 is stored
in the area IM3 that is freed; the reconstructed picture RP and the
displayed picture DP pointers indicate the area IM3. Picture B5 needs the
forward picture P7 and the backward picture P4 that were previously
decoded; the forward picture FP and backward picture BP pointers indicate
the areas IM2 and IMP, respectively, and so on.
Operation of the MPEG decoder
FIG. 4 is a timing-diagram schematically illustrating an exemplary
operation of the system of FIG. 3. FIG. 4 represents request signals RQ
and corresponding acknowledge signals ACK of the various elements of the
system, according to a decreasing level of priority from top to bottom.
Hatched areas represent operations on the memory bus MBUS and on the
parameter bus VLDBUS.
The first pair of request and acknowledge signals RQVID, ACKVID corresponds
to the FIFO 22 of the display controller 18. The second pair of signals
RQCD, ACKCD, corresponds to the FIFO 20 of the compressed data input bus
CDin. The pair of signals RQVLD, ACKVLD corresponds to the FIFO 21 of the
VLD circuit 10.
The pair of signals RQFILT(1), ACKFILT(1) corresponds to one of six
possible requests generated by the half-pixel filter 14. The pair RQSUM,
ACKSUM corresponds to the FIFO 26 that provides the reconstructed
macro-blocks. FIG. 4 also shows the waveforms of a signal FILTRDY that
indicates to adder 16 that the half-pixel filter 14 is ready to provide
data; of a signal DCTRDY that indicates to adder 16 that the DCT.sup.-1
circuit 13 is ready to provide data; and of a signal SUMEN that enables
stacking the sums provided by adder 16 in the FIFO 26. The macro-block
synchronization signal MBS provided by the half-pixel filter 14 to the
memory controller 24 and to the sequencer 28 is also shown.
FIG. 4 is described in an example where the memory bus MBUS includes a
64-bit data bus and where the size of the FIFOs is two packets of data,
one packet of data corresponding to a macro-block fraction. The FIFOs (20
and 26) which write on the bus MBUS issue a request when their content
exceeds one half of their capacity, and the FIFOs (21, 22, of filter 14)
which read on the bus issue a request when their content is lower than one
half of their capacity.
At time t.sub.0, requests RQVID, RQCD and RQVLD are issued; the FIFOs 22,
20, and 21 are practically empty. Since the request RQVID has the highest
priority, it is acknowledged by the signal ACKVID shortly after time
t.sub.0. When signal ACKVID is active, the memory controller 24 reads in
the adequate area of memory 15 (indicated by the displayed picture pointer
DP) pixels to be displayed and stacks them in the FIFO 22. When the
content of the FIFO 22 exceeds one half of its capacity, the request RQVID
is disabled. However, the task continues (the signal ACKVID remains
active) as long as a full packet, of predetermined size exploitable by the
display controller 18, has not been transferred. (In fact, as will be seen
hereinafter, to improve the efficiency of the system, a transfer task is
partitioned into several non-interruptible transfer sub-tasks).
The memory 15 contains pictures that are stored in macro-block order, but
these pictures must be provided to the display controller 18 in line
order. Thus, the transfer task of the memory controller 24 is also to
calculate adequate addresses to read the data in line order.
At time t.sub.1, immediately after the disabling of the acknowledge signal
ACKVID, the request RQCD is acknowledged by issuing signal ACKCD. The
memory controller 24 then transfers the compressed data of the FIFO 20 to
the area CD of memory 15. When the content of the FIFO 20 is lower than
one half of its capacity, the request RQCD is disabled but, as above, the
transfer of data continues until a full packet of data is transferred. The
compressed data are written in the memory 15 in the order they arrived.
At time t.sub.2, immediately after the acknowledge signal ACKCD is
disabled, the request RQVLD is acknowledged by the issue of signal ACKVLD.
The memory controller 24 then transfers the compressed data from memory 15
to the FIFO 21, in the order they were written. When the content of FIFO
21 is higher than one half of its capacity, its request RQVLD is disabled,
but transfer continues until a full packet of data is transferred.
Then, the VLD circuit starts to unstack and to process the data contained
in the FIFO 21. At time t.sub.3, the VLD circuit decodes a macro-block
header and provides the decoded parameters through bus VLDBUS to the
elements that require them. Especially, a macro-block type is provided to
the half-pixel filter 14, a quantizer scale is provided to the inverse
quantizer circuit 12, and vectors are provided to the memory controller 24
as well as to the half-pixel filter 14.
At time t.sub.4, all the parameters have been provided and the VLD circuit
starts to provide picture data to be decoded to the RLD circuit 11 . Once
it has received the macro-block type and the vectors, the filter 14 is
ready to receive a predictor macro-block. The filter 14 issues one RQFILT
request according to the macro-block type it received. The filter 14 can
issue up to six different requests on three request lines RQFILT, these
different requests corresponding to the six different types of macro-block
(intra, predicted, bidirectional; each macro-block being interlaced or
progressive). In the present example, the request RQFILT(1) corresponds to
a progressive predicted macro-block.
Since no request of higher priority is active, the request RQFILT(1) is
acknowledged by issuing signal ACKFILT(1). The synchronization signal MBS
is pulsed as the filter request is activated, which allows sequencer 28 to
increment a macro-block counter for reasons mentioned previously, and
allows the memory controller 24 to validate one or more vectors that it
received through the VLD circuit.
Thus, shortly after time t.sub.4, the acknowledge signal ACKFILT(1) is
issued and the transfer to filter 14 of a predictor macro-block starts
from a suitable area of memory 15 (indicated by the forward picture
pointer FP). The filter 14 includes two FIFOs; one FIFO is intended to
receive forward macro-blocks (of a forward picture); the other FIFO is
intended to receive backward macro-blocks (of a backward picture). In the
present example, the memory controller 24 receives a request corresponding
to a predicted macro-block and issues an acknowledge signal ACKFILT(1)
that selects the forward macro-block FIFO of filter 14. Depending on the
filter request received by the memory controller 24, the latter issues one
of three possible acknowledgements, for respectively selecting, in the
filter 14, the forward macro-block FIFO, the backward macro-block FIFO, or
indicating to the memory controller 24 that it must remain inactive (intra
macro-block).
If data are transferred on 64 bits of the bus MBUS and if the macro-blocks
correspond to portions of 16.times.16-pixel pictures, the transfer of a
4:2:0-format macro-block (FIG. 2B) is carried out, in a simplified case,
in three phases numbered from 1 to 3 in FIG. 4. The luminance and
chrominance pixels are coded on 8 bits. Thus, one word transferred on bus
MBUS corresponds to 8 pixels. Each transfer phase is carried out in 16
cycles to successively transfer the two luminance blocks Y1 and Y2, the
two luminance blocks Y3 and Y4, and then the two chrominance blocks U and
V. The capacity of the FIFOs of filter 14 is of four 8.times.8-pixel
blocks. The filter 14 issues one of the six possible requests when the
content of the corresponding FIFO is lower than one half of its capacity.
In practice, which is not described in relation with FIG. 4, a predictor
macro-block provided to the filter includes a 17.times.17-pixel luminance
block (Y1-Y4), and a 9.times.18-pixel chrominance block U and V. In
addition, the pairs of blocks to be transferred (Y1, Y2; Y3, Y4; U, V) are
not necessarily "aligned" with the 64 data bits of bus MBUS, which
involves that a luminance block (136 bits wide) must be transferred in
three phases of 17 read cycl | | |
