Semiconductor memory device and defect remedying method thereof

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and its defect remedying method and, more particularly, to a technology which is effective if applied to a dynamic RAM (Random Access Memory) having a storage capacity as large as about 16 Mbits.

2. Description of the Prior Art

The development of the dynamic RAM having the large storage capacity of about 16 Mbits is being advanced. An example of the dynamic RAM is described on pp. 67 to 81 of "Nikkei Microdevice" issued on Mar. 1, 1988 by NIKKEI McGRAW-HILL. In accordance with the increase in the storage capacity, the memory chip necessarily has its size enlarged. Accordingly, special considerations have to be taken into the drop of the operation speed, which is caused by making the elements finer and by handling the wiring lines. In other words, the realization of the high storage capacity of about 16 Mbits requires development of a new technology which is different from that used for the dynamic RAM of about 1 or 4 Mbits.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device which aims at having a large storage capacity.

Another object of the present invention is to provide a semiconductor storage device which realizes the large storage capacity while speeding up the operations.

Still another object of the present invention is to provide a rational defect remedying method for the memory device aiming at the large storage capacity.

The aforementioned and other objects and novel features of the present invention will become apparent from the descriptions to be made in the following with reference to the accompanying drawings.

The representatives of the invention to be disclosed hereinafter will be briefly described in the following.

There is provided a semiconductor memory device having a large storage capacity, in which a semiconductor chip is bisected by its longitudinal center line to form two regions, in which peripheral circuits are arranged in a cross area composed of the longitudinal center portions and the transverse center portions of said two regions, and in which memory arrays are arranged in the four regions which are divided by said cross area. In the cross area, the edges contacting with the memory arrays are arranged with X-decoders and Y-decoders, and the regions of the longitudinal or transverse center portion, which are interposed between the X-decoders, are arranged with a main amplifier, a common source switch circuit, a sense amplifier control signal generator and a mat selection control circuit. Those circuits of the peripheral circuits, which may probably inject minority carriers into a substrate on principle, are arranged on two center lines of the cross area or their vicinities. The memory arrays formed in the four quartered areas of said cross area are constructed of a block of plural memory mats as a unit having the same size as includes the sense amplifiers. The unit memory mat includes a control circuit for generating a variety of timing signals for the memory cell selections on the basis of a mat selection signal. The control circuit is activated by the mat selection signal. The memory mat selection signal is prepared by decoding the address signal inputted through a specific address buffer. Bonding pads are partially or wholly arranged in the regions of said cross area. The bonding pads are bonded to LOC lead frame. Of these bonding pads, a plurality of pads for applying the power voltage of the circuit and the ground potential are arranged at a suitable spacing according to circuit blocks requiring them and are connected to the common LOC lead frame to be fed with the power voltage of the circuit and the ground potential. The four regions quartered by the cross area are arranged with the memory arrays, and the semiconductor chip has its four corners stepped. There is provided an internal drop voltage generator which is made operative in response to the power voltage fed from an external terminal and which includes one or more impedance converting output buffers made receptive of a reference voltage prepared by a reference voltage generator. The internal drop voltage generator is provided for each of the memory array operating voltage and the peripheral circuit operating voltage. The internal drop voltage generator drives an output MOSFET of source-follower type having its gate fed with the signal to be outputted through a level converter for converting the signal to be fed and formed by the internal circuit into a signal level corresponding to the power voltage fed from the external terminal. The drop voltage generated by the internal drop voltage generator is selectively outputted, in the output high impedance state of a data output buffer in a test mode, from the output terminal of the data output buffer through a switch MOSFET to be switched by a signal at the bootstrap voltage or external power voltage level. The selection signal of the word lines or the shared sense amplifiers is prepared by a selector which has its operations controlled by a high voltage prepared by boosting the internal drop voltage. At least one pair of memory cell arrays are arranged symmetrically with respect to the main amplifier, and the main amplifier is selectively connected with the input/output lines of the paired memory cell arrays through a switch circuit to be switched in accordance with the selections of the paired memory cell arrays. The shared sense amplifier is given an operation mode for connecting both the data lines at the selected and unselected sides. The pull-up MOSFET of CMOS structure composed of the sense amplifier, the initial-step circuit of the main amplifier and the input/output lines, the short MOSFET composed of the complementary data lines and the complementary input/output lines, and the MOSFET of diode mode constituting the charge pump circuit are caused to have a low threshold voltage. A pair of parallel bit lines are constructed of the bit line cross type, in which the bit lines are interchanged by using a first metal wiring layer formed over the wiring layer forming the bit lines. The first metal wiring layer also forms the column selection lines, one of which is formed to correspond two pairs of bit lines and folded to overlap from one to other bit line pair at portion different from the cross portion of the bit lines. A step damping region made of a dummy wiring layer is formed between a memory cell array of laminated type and a peripheral circuit.

There is also provided a defect remedying method comprising the steps of: constructing a memory array of a block composed of plurality units of memory mats having the same size and including sense amplifiers; forming redundancy word lines and/or redundancy data lines for each of said memory mats; forming redundancy decoders of a number smaller than the total number of the redundancy word and/or data lines of all of said memory mats and larger than the total number of the redundancy word and/or data lines of each of said memory mats so that said redundancy decoders may be used for each of said memory mats or commonly for said memory mats. Preparatory word lines and/or preparatory column selection lines wired to intersect a plurality of word lines and/or column selection lines, respectively, are formed at the output of a word line or column selector, and the word lines and/or the output lines of the column selector are cut by physical means, when a word line and/or a data line are defective, from the column selection lines corresponding to the defective word line and/or the defective data line and are connected with the preparatory word lines and/or the preparatory column selection lines. When in the multi-bit simultaneous testing mode by the multiplex selection of the column system, only the defective data or column selection line of the data lines or column selection lines is switched to a redundancy data line or a redundancy column selection in a manner to correspond to the memory cell array divided into a plurality of memory blocks. The data lines are divided into a plurality of blocks by one of a specific-bit of the address signals of the row and/or column systems, a block address prepared inside, or the combination of the address signal and the block address, and a defective data line in a defective block only is switched to a redundancy data line by making use of a signal designating the block.

Since the major timing signals are propagated four ways from the center of the chip, according to the means specified above, the lengths of the signal wiring lines, which might otherwise accompany the size-up of the chip, can be substantially shortened to realize the large capacity and the speed-up of the DRAM. The influences to be exerted upon the memory arrays can be minimized by arranging a circuit capable of generating minority carriers on or in the vicinity of the two center lines of the aforementioned cross area. The design and control can be simplified by making a block of the unit memory mats of the same size containing sense amplifiers. The bonding pads are connected with the LOC lead frame so that their arrangement can be optimized. Thanks to the provision of the pads for establishing the circuit power voltage and the ground potential, the power impedance can be dropped. The stress from the resin mold can be dispersed by the steps formed in the corners. Thanks to the provision of the internal drop voltage generator, it is possible to prevent the electrostatic breakdown which might otherwise be caused as a result of the low power consumption and the finer element. Since the voltage is dropped in a manner to correspond to the memory array operating voltage and the peripheral circuit operating voltage, it is possible to increase the power noise margin. The output level is retained and speeded up by driving the output MOSFET with the level change. The internal voltage can be monitored by bringing the data output buffer to the output high-impedance state. The speed-up and the stabilization can be achieved by causing the boost power to form the selection signals for selecting the word lines and the shared sense amplifiers. The circuit can be simplified by causing the main amplifiers to correspond to the plural memory cell arrays. The margin test of the sense amplifiers can be executed by connecting the shared sense amplifiers with the two data lines. The speed-up and the level drop can be minimized by using the MOSFET having a low threshold voltage. The high integration can be attained by interchanging the bit lines using the metal wiring layer formed over the bit lines. The metal wiring layer can also be used as the column selection line. The stepped shock absorbing region can prevent the shortage of the steps in the wiring lines.

As the defect remedying method, the redundancy circuit can be simplified by utilizing the redundancy decoder as the multiple memory mats. The circuit can be simplified and speeded up by switching the defective data line or word line directly to the preparatory data line or word line. The preparatory circuit can be simplified by interchanging only the defective circuit when in the multi-bit simultaneous test most by the multiplex selection of the Y-system. Thus, the defect remedy can be achieved with the simple structure by utilizing the block designating signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fundamental layout showing one embodiment of the dynamic RAM, to which is applied the present invention;

FIG. 2 is an overall layout showing one embodiment of the DRAM according to the present invention;

FIG. 3 is a layout showing the detailed arrangement of bonding pads of the DRAM;

FIG. 4 is a block diagram showing one embodiment of the address assignment of the same;

FIG. 5 is a block diagram noting the control signals of the dynamic RAM according to the present invention;

FIG. 6 is a block diagram showing the operation sequence of the dynamic RAM according to the present invention;

FIG. 7 is a layout for specifically explaining the power supply lines and the relations between the associated power circuits and the pads;

FIG. 8 is a layout for specifically explaining the ground lines and the relations between the associated internal power circuits and the pads;

FIGS. 9(A) and 9(B) are a specific layout and a section showing one embodiment of an input protection circuit according to the present invention;

FIG. 10 is a specific layout showing one embodiment of the input protection circuit mounted in the external power source voltage pad;

FIG. 11 is a layout showing one embodiment of the peripheral portion of a semiconductor chip;

FIG. 12 is a schematic section showing the corner of the peripheral portion;

FIG. 13 is a schematic section showing the outermost periphery;

FIG. 14 is a fundamental layout showing another embodiment of the dynamic RAM according to the present invention;

FIG. 15 is a fundamental layout showing still another embodiment of the dynamic RAM;

FIG. 16 is a fundamental layout showing a further embodiment of the dynamic RAM;

FIGS. 17(A) to 17(C) are layouts showing the fundamental structure of another embodiment of the memory mat and another embodiment of the memory block constructed by combining the former;

FIGS. 18(A) to 18(C) are layouts showing the fundamental structure of another embodiment of the aforementioned memory mat and another embodiment of the memory block constructed by combining the former;

FIGS. 19(A) to 19(C) are layouts showing the fundamental structure of another embodiment of the aforementioned memory mat and another embodiment of the memory block constructed by combining the former;

FIGS. 20(A) to 20(C) are layouts showing the fundamental structure of still another embodiment of the aforementioned memory mat and another embodiment of the memory block constructed by combining the former;

FIGS. 21(A) and 21(B) are layouts showing the fundamental structure of another embodiment of the aforementioned memory mat and another embodiment of the memory block constructed by combining the former;

FIG. 22 is a top plan view showing one embodiment of the lead frame to be used in the dynamic RAM according to the present invention;

FIGS. 23(A) to 23(C) are schematic side elevations showing examples of connection between the lead frame and the semiconductor chip;

FIGS. 24(A) and 24(B) are external views and an internal perspective view showing one embodiment of the dynamic RAM according to the present invention;

FIGS. 25(A) to 25(C) are views showing the pin arrangements of external terminals according to one embodiment of the dynamic RAM of the present invention;

FIG. 26 is a layout showing the pin arrangement of the external terminals according to one embodiment in case a ZIP package is used;

FIG. 27 is a layout showing the pin arrangement of the external terminals according to one embodiment in case an SOJ package is used;

FIG. 28 presents diagrams showing portions of the circuit according to one embodiment of the RAS control circuit of the dynamic RAM of the present invention;

FIG. 29 presents diagrams showing portions of the circuit according to one embodiment of the aforementioned control circuit;

FIG. 30 presents diagrams showing other portions of the circuit according to one embodiment of the aforementioned control circuit;

FIG. 31 is a circuit diagram showing one embodiment of the X-address buffer of the dynamic RAM according to the present invention;

FIG. 32 is a circuit diagram showing one embodiment of the address buffer corresponding to the X-address signals A9 and A10;

FIG. 33 is a circuit diagram showing one embodiment of the address buffer corresponding to the X-address signal A11;

FIG. 34 is a circuit diagram showing one embodiment of the address buffer corresponding to the X-address signal A8;

FIG. 35 presents circuit diagrams showing portions of one embodiment of a predecoder of a row system;

FIG. 36 is a circuit diagram showing one embodiment of a redundancy circuit of an X-system;

FIG. 37 presents circuit diagrams showing portions of one embodiment of a decoder circuit for selecting the word lines;

FIG. 38 presents circuit diagrams showing portions of one embodiment of a decoder circuit for selecting the redundant word lines;

FIG. 39 is a circuit diagram showing one embodiment of a timing generator for activating the sense amplifier;

FIG. 40 presents circuit diagrams showing portions of one embodiment of a control circuit disposed in the memory mat;

FIG. 41 is a circuit diagram showing one embodiment of an X-decoder, a word line driver and a shared control line driver;

FIG. 42 is a circuit diagram showing one embodiment of a memory cell array;

FIG. 43 is a circuit diagram showing one embodiment of a refresh address counter;

FIG. 44 presents circuit diagrams showing portions of one embodiment of a control circuit of the CAS system;

FIG. 45 is a circuit diagram showing one embodiment of a Y-address buffer;

FIG. 46 presents circuit diagrams showing portions of one embodiment of a Y-redundancy circuit;

FIG. 47 presents circuit diagrams showing other portions of one embodiment of a Y-redundancy circuit;

FIG. 48 presents circuit diagrams showing portions of one embodiment of a Y-redundancy circuit;

FIG. 49 is a circuit diagram showing one embodiment of the predecoder of a Y-address signal;

FIG. 50 is a circuit diagram showing one embodiment of the Y-decoder for generating a column selection signal;

FIG. 51 is a circuit diagram showing one embodiment a nibble counter;

FIG. 52 presents circuit diagrams showing portions of one embodiment of a control circuit for generating a Y-control signal;

FIG. 53 is a circuit diagram showing one embodiment of the operation mode decoder;

FIG. 54 presents circuit diagrams showing portions of one embodiment of a Y-control circuit;

FIG. 55 presents circuit diagrams showing portions of one embodiment of a WE-control circuit;

FIG. 56 presents circuit diagrams showing other portions of one embodiment of a WE-control circuit;

FIG. 57 is a circuit diagram showing one embodiment of the data input buffer;

FIG. 58 is a circuit diagram showing one embodiment of the main amplifier control circuit;

FIG. 59 is a circuit diagram showing one embodiment of the main amplifier;

FIG. 60 is a circuit diagram showing one embodiment of the output control circuit of the data of the main amplifier;

FIG. 61 is a circuit diagram showing one embodiment of the output control circuit of the main amplifier;

FIG. 62 is a circuit diagram showing one embodiment of the data output buffer;

FIG. 63 presents circuit diagrams showing portions of one embodiment of the test circuit;

FIG. 64 presents circuit diagrams showing other portions of one embodiment of the test circuit;

FIG. 65 is a circuit diagram showing one embodiment of the control circuit for designating the operation mode;

FIG. 66 is a circuit diagram showing one embodiment of another control circuit;

FIG. 67 is a circuit diagram showing one embodiment of the substrate back bias voltage generator;

FIG. 68 is a circuit diagram showing one embodiment of the internal boost voltage generator;

FIG. 69 is a circuit diagram showing one embodiment of the internal drop voltage generator;

FIG. 70 is a timing chart showing one example of the operations of the RAS system;

FIG. 71 is a timing chart showing one example of the operations of the RAS system;

FIG. 72 is a timing chart showing one example of the operations of the RAS system;

FIG. 73 is a timing chart showing one example of the operations of the X-address buffer;

FIG. 74 is a timing chart showing one example of the operations of the CAS system;

FIG. 75 is a timing chart showing one example of the address selecting operations of the CAS system;

FIG. 76 is a timing chart showing one example of the writing operations;

FIG. 77 is a timing chart showing one example of the operations of the Y-address buffer;

FIG. 78 is a timing chart showing one example of the operations of the test mode;

FIG. 79 is a timing chart showing one example of the operations of the CAS system;

FIG. 80 is a timing chart showing one example of the operations of the CAS system;

FIG. 81 is a timing chart showing one example of the operations of the CAS system;

FIG. 82 is a block diagram showing another embodiment of the defect remedying method according to the present invention;

FIG. 83 is a block diagram showing another embodiment of the defect remedying method according to the present invention;

FIGS. 84(A) to 84(C) are waveform charts and a circuit diagram of one embodiment for explaining a word line testing method;

FIGS. 85(A) to 85(D) are waveform charts and circuit diagrams of one embodiment for explaining a signal amount margin testing method;

FIG. 86 is a block diagram showing another embodiment of the function set mode;

FIGS. 87(A) to 87(C) are waveform charts and a circuit diagram of one embodiment showing another embodiment of the refresh address counter;

FIGS. 88(A) and 88(B) a block diagram showing another embodiment of the internal power monitor method and a waveform chart for explaining the same;

FIGS. 89(A) and 89(B) are a circuit diagram and a waveform chart for explaining the principle of the multi-bit testing method;

FIG. 90 is a section showing an element structure taken in the bit line direction according to one embodiment of the present invention;

FIGS. 91(A) to 91(C) are conceptional diagrams for explaining the defect remedying method according to the present invention;

FIG. 92 is a block diagram showing one embodiment of the layout of the main amplifier and the memory cell array according to the present invention;

FIG. 93 is a block diagram showing another embodiment of the layout of the main amplifier and the memory cell array according to the present invention;

FIG. 94 is a fundamental layout showing another embodiment of the semiconductor chip according to the present invention;

FIG. 95 is a pattern diagram showing one embodiment of the memory cell array according to the present invention;

FIGS. 96(A) and 96(B) are a section and a schematic diagram for explaining the bit line cross portion of the memory cell array;

FIGS. 97 to 99 are pattern diagrams showing one embodiment of the shared sense amplifier column portion in the bit line direction and the corresponding memory cell array portion;

FIG. 100 is a section showing the step damping region;

FIG. 101 is a pattern diagram showing one embodiment of the memory cell array in the word line direction and the corresponding word driver;

FIGS. 102 to 105 are pattern diagrams each showing one embodiment of the corresponding word drivers;

FIGS. 106 and 107 are pattern diagrams each showing one embodiment of the corresponding X-decoder;

FIG. 108 is a pattern diagram showing one embodiment of the memory cell array in the word line direction and the word clear circuit;

FIG. 109 is a diagram showing one embodiment of the present invention, in which the number of resresh cycles is Vn whereas the number of sense amplifiers to be simultaneously activated is Vn for a capacity of n bits;

FIG. 110 is a diagram showing the system of the prior art, in which the number of resresh cycles is 1/2.multidot.Vn whereas the number of sense amplifiers to be simultaneously activated is 2Vn for a capacity of n bits;

FIG. 111 is a diagram showing one embodiment of the DRAM having the structure of 1/4.multidot.n words.times.4 bits according to the present invention;

FIG. 112 is a diagram showing the DRAM having the structure of 1/4.multidot.n words.times.4 bits of the prior art;

FIG. 113 is a diagram showing the structure of the nibble mode according to the present invention;

FIG. 114 is a diagram showing the structure of the nibble mode of the prior art;

FIG. 115(a) is a diagram comparing the address systems having the structure of n words.times.1 bit of the prior art and according to the embodiment of the present invention;

FIG. 115(b) is a diagram comparing the address systems having the structure of 1/4.multidot.n words.times.4 bits of the prior art and according to the embodiment of the present invention;

FIG. 116(a) is a diagram showing the package contour and pin arrangements of the DRAM of 16 Mbits according to one embodiment of the present invention;

FIG. 116(b) is a diagram showing the package contour and pin arrangements of the DRAM of 4 Mbits according to one embodiment of the present invention;

FIG. 117(a) is a diagram showing the memory cell structure using the stacked capacitor STC adopted in one embodiment of the present invention;

FIG. 117(b) is a diagram showing the memory cell structure using the high-speed plate capacitor HSPC adopted in one embodiment of the present invention;

FIG. 118(a) is a diagram combining the refresh system using the present invention and the in-chip voltage converter;

FIG. 118(b) is a diagram showing the method for the in-chip voltage V.sub.CL to charge the bit lines through the sense amplifier;

FIG. 119 is a diagram showing the DRAM of the prior art using no voltage converter;

FIGS. 120(a) and 120(b) are a diagram and a time chart showing the DRAM having a Vn refresh.times.4 structure for introducing the A.sub.i-1 address from the I/O pins;

FIG. 121(a) is a diagram showing another embodiment of the present invention;

FIG. 121(b) is a circuit diagram for changes to the 1/2.multidot.Vn refresh cycle only for the column address signal CAS and the before row address signal RAS;

FIG. 122 is a circuit diagram for forming a sense amplifier activation signal from the refresh cycle switching address signals A.sub.xi-1 and A.sub.xi-1 shown in FIG. 121(b);

FIG. 123(a) is a diagram showing a peak current increase preventing circuit of single-phase drive type;

FIG. 123(b) is a diagram showing a peak current increase preventing circuit of two-phase drive type;

FIGS. 124(a) and 124(b) are diagrams showing another embodiment of the present invention;

FIG. 125 is a chip layout of the DRAM using one embodiment of the present invention;

FIG. 126(a) is a diagram showing the case in which the number of the refresh cycles is 2 Vn in the present embodiment;

FIG. 126(b) is a diagram showing the case in which the number of the refresh cycles is 4 Vn in the present embodiment;

FIG. 127 is a circuit diagram showing one embodiment of the voltage drop circuit of the dynamic RAM to which is applied the present invention; and

FIG. 128 is a block diagram showing one embodiment of the dynamic RAM containing the voltage drop circuit of FIG. 127.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a fundamental layout showing one embodiment of a dynamic RAM to which is applied the present invention.

The RAM will have its operating speed dropped, as the various wiring lengths of control signals or memory array drive signals are elongated as a result of an increase in the chip size accompanying an increase in the memory capacity. In order to prevent this speed drop, the present device has made the following devices in the arrangement of memory arrays composing the RAM and peripheral portions for address selections.

In FIG. 1, there is provided a cross area which is formed in the chip with a longitudinal center portion and a transverse center portion. This cross area is mainly arranged with peripheral circuits, and the four areas divided by the cross area are arranged with memory arrays.

The cross area is divided, as shown in FIG. 1, into areas A to D. Specifically, the area A is located at the lefthand side of the transverse center of the chip, and the area A is located at the righthand side of the transverse center of the chip. The area C is located at the upper side of the longitudinal center of the chip, and the area D is located at the lower side of the longitudinal center of the chip. Moreover, an area E is located at the center of the chip, in which the vertical center portion and the longitudinal center portion of the chip intersect each other.

In the memory chip of this embodiment, the four areas divided by the cross areas A to E are constructed of memory arrays. Each of these four memory arrays is made to have a memory capacity of about 4 Mbits, although not limitative, as will be especially limitative. Accordingly, the four memory arrays totally have a memory capacity as high as about 16 Mbits.

Of the cross areas, the peripheral portions adjoining each of the memory arrays is arranged with a decoder and a driver for selecting the memory arrays. Specifically, the two memory arrays divided longitudinally by the areas A and B are corresponded to by Y (Column) decoders (Ydec) and Y select (Column select) drivers (YS drivers). the two memory arrays divided transversely by the areas C and D are corresponded to by X (Row) decoders (Xdec) and word line drivers (WL drivers). As a result, the four memory arrays are arranged by extending the word lines transversely and the data lines (bit lines or digit lines) longitudinally. Since, however, one memory array has a capacity as large as about 4 Mbits, the number of the memory cells to be connected with one data line is impractically enlarged. As a result, each memory array is composed of such a plurality of memory mats as will be described hereinafter.

The remaining portions of the cross areas A to E are arranged with the following major circuit blocks. The areas A and B are arranged with address buffers, address comparators (redundancy decoders), control clock generators, data input buffers and so on. The areas C and D are arranged with common source switch circuits, sense amplifier control signal circuits, mat selection control circuits, main amplifiers and so on. And, the center area E is arranged with X-decoder and Y-decoder address signal generators, an internal voltage-drop power circuit and so on.

FIG. 2 is an overall layout showing one embodiment of the dynamic RAM according to the present invention. Specifically, the portion corresponding to the aforementioned area A is arranged with Y-circuits-including a Y-address buffer, a Y-redundancy circuit and a Y-address driver (logical step), a test function circuit and a CAS control signal circuit. Closer from the area A to the center, there are arranged an internal voltage-drop VDL limiter circuit for transforming an external power voltage VCCE such as about 5 V to a voltage such as about 3.3 V to be fed to a memory array, and a Y-address driver, an X-address driver and a mat selection driver DV1 to DV3.

The portion corresponding to the aforementioned area B is arranged with X-circuits including an X-address buffer, an X-redundancy circuit and an X-address driver (logical step), a RAS control signal circuit, a WE control signal circuit and a data input buffer. Closer from the area B to the center, there are arranged an internal voltage-drop VCC limiter circuit for transforming an external power voltage VCCE such as about 5 V to a voltage such as about 3.3 V to be fed to a peripheral circuit, and a Y-address driver, an X-address driver and a mat selection driver DV1 to DV3.

If, as in the areas A and B, the address buffers, the redundancy circuits containing the address comparators corresponding to the address-buffers, and CAS and RAS control signal circuits for generating control clocks are concentrated in one position, a high integration can be achieved by distributing the clock generators and other circuits across the wiring channel, namely, by sharing the wiring channels. At the same time, the signals can be transmitted at the shortest equal distance so that the operations can be speeded up.

The portion corresponding to the aforementioned area C is arranged with four main amplifiers corresponding to totally eight memory mats arranged symmetrically with respect to the center axis of the area C, an internal boost voltage circuit VCHG, a substrate voltage generator VBBG, and four main amplifiers corresponding to the remaining totally eight memory mats arranged symmetrically with respect to the center axis of the area C. Thus, in this embodiment, one memory array is arranged with eight memory mats, and two memory arrays are arranged symmetrically with respect to the area C so that totally sixteen memory mats are provided. Thanks to this arrangement, the main amplifiers can have their number decreased and their signal propagation distances shortened to speed up the operations.

The portion corresponding to the aforementioned area D is arranged with four main amplifiers-corresponding to totally eight memory mats arranged symmetrically with respect to the center axis of the area D, four data output buffers, and four main amplifiers corresponding to the remaining totally eight memory mats arranged symmetrically with respect to the center axis of the area D. Thus, this embodiment is constructed of four memory arrays, as described above, so that the memory mats are thirty two in total number.

In this embodiment, the aforementioned longitudinal center area is arranged with bonding pads indicated by small square symbols, although not especially limitative. The detail arrangement of these bonding pads is specifically shown in the layout of FIG. 3. In FIG. 3, the bonding pads indicated by solid squares are those for external power supply. In order to increase the input level margin, i.e., to decrease the power impedance, totally thirteen pads VSS for supplying the ground potential of the circuit are arranged on one line. These pads VSS are connected with longitudinally extending ground potential leads which are formed by the LOC technology. Of these pads VSS, the pad disposed in each of the areas C and D is used as a ground potential for preventing the floating due to the clearing of the word lines and the coupling of the non-selected word lines of word drivers. Two pads disposed in each of the areas C and D are provided for the common source VSS of a sense amplifier to drop the wiring resistance of the common source there by to speed up the operations. The area D is further arranged with two pads for the data output buffer, and the area E is arranged with pads which are operative to supply the ground potential to the X-address buffer and the Y-address buffer and which correspond to the power generator. Moreover, one pad of each of the areas C and D and two pads of the area E correspond to other peripheral circuits. As a result, the ground potential of the circuit has a lower power impedance for the operations of the internal circuit, and the VSS wires between five kinds of internal circuits thus divided are connected th