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Claims  |
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What is claimed is:
1. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, at least one second region and a pair of
third regions, said first region functioning as a channel and said pair of
third regions functioning as source and drain regions;
a gate insulating layer located adjacent to said semiconductor layer; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first and second regions extend between said pair of third
regions and said at least one second region extends between said first
region and at least one of said third regions, and
wherein a total concentration of oxygen, carbon and nitrogen in said at
least one second region is higher than a total concentration of oxygen,
carbon and nitrogen in said first region.
2. The semiconductor device of claim 1 wherein said semiconductor layer is
crystalline.
3. The semiconductor device of claim 1 wherein the total concentration of
oxygen, carbon and nitrogen in said at least one second region is the same
as a total concentration of oxygen, carbon and nitrogen in said pair of
third regions.
4. The semiconductor device of claim 1 wherein said gate electrode is
provided with an anodic oxide thereof on its surface.
5. The semiconductor device of claim 1 wherein said semiconductor layer
comprises silicon.
6. The semiconductor device of claim 5 wherein said source and drain
regions comprise a metal silicide.
7. The semiconductor device of claim 6 wherein said metal silicide contains
a metal selected from the group consisting of titanium, tungsten,
platinum, palladium and nickel.
8. The semiconductor device of claim 1 wherein said semiconductor layer
contains a crystallization promoting metal element.
9. The semiconductor device of claim 4 wherein each boundary between said
at least one second region and said pair of third regions is aligned with
an outer edge of said anodic oxide.
10. The semiconductor device of claim 1 wherein said pair of third regions
is doped with one conductivity type impurity at a first concentration.
11. The semiconductor device of claim 10 wherein said at least one second
region is doped with said one conductivity type impurity at a second
concentration which is smaller than said first concentration.
12. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, a pair of second regions between which
said first region extends, and a pair of third regions between which said
first and second regions extend;
a gate insulating layer located adjacent to the first region of said
semiconductor layer;
a pair of metal silicide layers contacting said pair of third regions; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first region and said pair of second regions have an intrinsic
or substantially intrinsic conductivity type, said pair of third regions
are doped with one conductivity type impurity and have one conductivity
type, a concentration of carbon, oxygen or nitrogen contained in said
pairs of second and third regions is higher than that in said first
region.
13. The semiconductor device of claim 12 wherein said semiconductor layer
is crystalline.
14. The semiconductor device of claim 12 wherein said metal silicide layers
are doped with carbon, nitrogen or oxygen at the same concentration as
said pair of third regions.
15. The semiconductor device of claim 12 wherein said gate electrode is
provided with an anodic oxide thereof on its surface.
16. The semiconductor device of claim 12 wherein said semiconductor layer
comprises silicon.
17. The semiconductor device of claim 12 wherein said pair of metal
silicide layers are doped with said one conductivity type impurity at a
concentration higher than that contained in said pair of third regions.
18. The semiconductor device of claim 12 wherein said pair of metal
silicide layers contain a metal selected from the group consisting of
titanium, tungsten, platinum, palladium and nickel.
19. The semiconductor device of claim 12 wherein said semiconductor layer
contains a crystallization promoting metal element.
20. The semiconductor device of claim 15 wherein each boundary between said
pair of second regions and said pair of third regions is aligned with an
outer edge of said anodic oxide.
21. A thin film semiconductor integrated circuit comprising:
a substrate having an insulating surface, said substrate having an active
matrix circuit portion and a peripheral circuit portion;
a plurality of electrodes formed in the active matrix circuit portion;
a plurality of first thin film transistors connected to said electrodes in
the active matrix circuit portion;
a plurality of second thin film transistors formed in said peripheral
circuit portion, said second thin film transistors constituting at least
an X-decoder/driver, a Y-decoder/driver, a memory circuit and a CPU
circuit,
wherein a concentration of carbon, nitrogen or oxygen contained in an
active semiconductor layer of said first thin film transistors is higher
than a concentration of carbon, nitrogen or oxygen contained in an active
semiconductor layer of said second thin film transistors.
22. The integrated circuit of claim 21 wherein the concentration of carbon,
nitrogen or oxygen in the active semiconductor layer of said first thin
film transistor is not lower than 5.times.10.sup.19 atoms/cm.sup.3.
23. The integrated circuit of claim 22 wherein the concentration of carbon,
nitrogen or oxygen in the active semiconductor layer of said second thin
film transistor is not higher than 1 .times.10.sup.19 atoms/cm.sup.3.
24. The integrated circuit of claim 21 further comprising a correction
memory formed in said peripheral circuit portion and connected to said CPU
circuit, wherein said correction memory is constituted by TFTs formed on
said substrate.
25. The integrated circuit of claim 21 wherein each of said first thin film
transistors is provided with a metal silicide layer within or in contact
with source and drain regions thereof.
26. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, at least one second region and a pair of
third regions, said first region functioning as a channel and said pair of
third regions functioning as source and drain regions;
a gate insulating layer located adjacent to said semiconductor layer; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first and second regions extend between said pair of third
regions and said at least one second region extends between said first
region and at least one of said third regions, and
wherein a total concentration of oxygen, carbon and nitrogen in said pair
of third regions is higher than a total concentration of oxygen, carbon
and nitrogen in said at least one second region.
27. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, at least one second region and a pair of
third regions, said first region functioning as a channel and said pair of
third regions functioning as source and drain regions;
a gate insulating layer located adjacent to said semiconductor layer; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first and second regions extend between said pair of third
regions and said at least one second region extends between said first
region and at least one of said third regions,
wherein a total concentration of oxygen, carbon and nitrogen in said at
least one second region is higher than a total concentration of oxygen,
carbon and nitrogen in said first region, and
wherein a total concentration of oxygen, carbon and nitrogen in said pair
of third regions is higher than a total concentration of oxygen, carbon
and nitrogen in said second at least one region.
28. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, at least one second region and a pair of
third regions, said first region functioning as a channel and said pair of
third regions functioning as source and drain regions;
a gate insulating layer located adjacent to said semiconductor layer; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first and second regions extend between said pair of third
regions and said at least one second region extends between said first
region and at least one of said third regions, and
wherein a band gap of said at least one second region is higher than a band
gap of said first region.
29. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, at least one second region and a pair of
third regions, said first region functioning as a channel and said pair of
third regions functioning as source and drain regions;
a gate insulating layer located adjacent to said semiconductor layer; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first and second regions extend between said pair of third
regions and said at least one second region extends between said first
region and at least one of third regions, and
wherein band gaps of said pair of third regions are higher than a band gap
of said at least one second region.
30. A semiconductor device comprising:
a substrate having an insulating surface;
a semiconductor layer formed on said insulating surface, said semiconductor
layer comprising a first region, at least one second region and a pair of
third regions, said first region functioning as a channel and said pair of
third regions functioning as source and drain regions;
a gate insulating layer located adjacent to said semiconductor layer; and
a gate electrode located adjacent to said gate insulating layer,
wherein said first and second regions extend between said pair of third
regions and said at least one second region extends between said first
region and at least one of said third regions,
wherein a band gap of said at least one second region is higher than a band
gap of said first region, and
wherein band gaps of said pair of third regions are higher than a band gap
of said at least one second region. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
The present invention relates to a thin film transistor (hereinafter
referred to as a TFT) having a non-single crystalline silicon film and
provided on an insulating film formed on an insulating substrate like
glass or other various types of substrates, or a thin film integrated
circuit as an application thereof, in particular, for an active type
liquid crystal display (LCD), and a manufacturing method thereof.
The Si TFTs can be classified into amorphous silicon TFTs and polysilicon
(or polycrystalline silicon) TFTs depending on the type and
crystallization conditions of the semiconductor material thereof.
Meanwhile, there has also been made research into those semiconductor
materials which have crystallization conditions intermediate between
amorphous silicon and polysilicon. Although there is an argument as to the
intermediate crystallization conditions, any silicon which is crystallized
more or less by any method such as thermal annealing at temperatures
exceeding 450.degree. C. or irradiation with laser beams, high intensity
light beams, and other high energies will be referred to as polysilicon in
the present specification.
Further, polysilicon TFTs are also applied as to so called SOI
(semiconductor on insulation) technique for monocrystalline silicon
integrated circuits and used as load transistors, for example, in highly
integrated static random access memories (SRAMs). It should be noted here
that amorphous TFT is hardly used for this purpose.
Since a semiconductor circuit having a TFT on an insulating substrate has
no capacity coupling between the substrate and wiring thereof, it allows
high operational speeds, thus realizing ultra fast microprocessors and
memories.
Generally, amorphous semiconductor has a small electric field mobility and
cannot therefore be used for TFTs required of high operational speeds.
Also, P-type amorphous silicon has too small an electric field mobility to
produce P-channel TFTs (PMOS TFTs) and therefore form complementary MOS
(CMOS) circuits in combination with N-channel TFTs (NMOS TFTs).
However, TFTs formed of an amorphous semiconductor can have a smaller Ioff
current. Accordingly, an amorphous channel TFT can be applied to those
devices in which a high operation speed is not so required for TFTs, and
TFTs of only one conductivity type are enough and a large charge retention
capability is required, for example, an active matrix circuit for an LCD
device of a small matrix size.
On the other hand, a polycrystalline semiconductor has a larger electric
field mobility and therefore allows higher operational speeds than an
amorphous semiconductor. For example, a TFT using a silicon film
recrystallized through laser annealing has an electric field mobility as
high as 300 cm.sup.2 /Vs. This value is extremely large considering that a
MOS transistor formed on an ordinary monocrystal silicon substrate has an
electric field mobility in the order of 500 cm.sup.2 /Vs. While a MOS
circuit formed on a monocrystalline silicon substrate allows only limited
operational speeds due to parasitic capacity present between substrate and
wiring thereof, a TFT mounted on an insulating substrate is free from
those limitations and expected to allow considerably high operational
speeds.
Further, polysilicon can be used not only for NMOS TFTs but also for PMOS
TFTs and can therefore form CMOS circuits, thus realizing a so called
monolithic structure as in active matrix type liquid crystal displays
wherein polycrystalline CMOS TFTs constitute not only the active matrix
portion but also peripheral circuits thereof (drivers, etc.). A pMOS TFT
as a load transistor is constituted by polysilicon also in the SRAM
mentioned before.
In amorphous TFTs, it is difficult to form the source and drain regions
through a self-aligning process which is used for a monocrystalline IC
technology so that parasitic capacity resulting from the geometrical
overlapping of the gate electrode with the source and drain electrodes
undesirably occurs. On the contrary, polysilicon TFTs are more
advantageous in that the self-aligning process can be employed, thus
suppressing the parasitic capacity.
However, polysilicon TFTs suffer from larger more leakage current (also
called off-state current) in the absence of voltage to the gate electrode
thereof (in the off-state thereof) than amorphous TFTs. Consequently, when
polysilicon TFTs are used at pixel electrodes of liquid crystal displays,
measures have been implemented to provide auxiliary capacity to compensate
for the leakage current and further connect two polysilicon TFTs in series
to reduce leakage current.
Also, it is known to take advantage of the high off-state resistance of
amorphous silicon TFTs and further form the peripheral circuits with
polysilicon TFTs having a high electric field mobility on the same
substrate. This can be realized by forming amorphous silicon and
irradiating it selectively with laser beams to crystallize only the
peripheral circuits.
At present, however, the production yield of the above method is low due to
low reliability of the laser irradiation process (e.g. poor uniformity of
irradiated energy per unit area). Also, since amorphous silicon TFTs with
a low electric field mobility are used in the active matrix region, it is
difficult to use this method for higher level applications. Instead of the
laser irradiation process, a thermal annealing of a higher reliability and
lower cost is desired. Also, it is desired that TFTs have an electric
field mobility of at least 5 cm.sup.2 /Vs to enhance added product values.
In conventional liquid crystal displays, it is known that TFTs constituting
decoder/driver circuit and TFTs provided at pixel electrodes arranged in a
matrix form are formed on the same substrate. It is not, however, that
liquid crystal displays operate only with the decoder and driver circuits
and pixel electrodes; they also require CPU and memory circuits, which
have conventionally been provided externally and connected with the
decoder and driver circuits formed on the glass substrate through such
means as wire bonding. This configuration causes the problems of increased
manufacturing processes and reduced reliability.
Meanwhile, these amorphous or polycrystalline silicon (collectively
referred to as non single crystalline silicon) causes much greater grain
boundary effects than monocrystalline silicon used in monocrystalline
semiconductor integrated circuits. The typical example is a leakage
current between source and drain regions. In particular, leakage current
(also-called off current) when applying a reverse bias voltage (negative
for N-channel transistors and positive for P-channel transistors) to a
gate electrode is caused by the existence of grain boundaries and known to
deteriorate the operating characteristics of transistors.
The off-state current is caused by abrupt variations in the electric field
at the boundary between the impurity region (N-type or P-type region) of
source and drain regions and the channel forming region (substantially
intrinsic). While this does not cause a problem in monocrystalline
silicon, in the case of a non single crystalline silicon, carriers hop
from the conduction band (valence electron band) of the impurity diffused
region to the conduction band (valence electron band) of the channel
forming region through grain boundaries.
As in monocrystalline MOS devices, an attempt has been made to solve this
problem by providing an offset region for relieving the electric field or
a low doped drain (LDD) structure for lowering the impurity density of the
impurity diffused region.
Referring to FIG. 2 (A), there is shown a conceptual diagram illustrating a
conventional offset gate type TFT. Its active layer is roughly divided
into three regions. The first region is an impurity region with a high
impurity concentration (source and drain regions), designated by 13 and 17
in FIG. 2 (A). The second region is called an offset region or an LDD
region, designated by reference numerals 14 and 16. The second region has
a high resistance while it is substantially intrinsic or has the same
conduction type as the source and drain regions in such a degree that the
parasitic channel is suppressed. There is no gate electrode overlapping
the second region. The third region is a channel forming region,
designated by reference numeral 15. This region is capable of varying the
conductivity type and controlling the flow of carriers under the influence
of the gate electrode 11 through the gate insulating film 12.
FIG. 2B shows an energy band diagram with respect to an active layer in the
vicinity of a gate insulating layer in an N channel TFT when there is no
voltage applied to a gate electrode and a voltage between source and drain
regions is enough small. Here, E.sub.F is a Fermi level, E.sub.1 and
E.sub.N is a band gap of the channel forming region and the impurity
region, respectively. Normally, E.sub.1 =E.sub.N. Also, a band gap of an
offset region is the same as E.sub.1. The band gap diagram when applying a
reverse bias voltage (i.e. negative voltage) to the gate electrode with
the source/drain voltage unchanged is shown in FIG. 2C. As can been seen,
the potential of the channel region adjacent to the gate electrode is
changed by "E.sub.G ".
It should be noted that the electric field in a boundary region between the
channel forming region and the impurity region is varied moderately
because of the existence of the offset regions 14 and 16, resulting in a
decrease in a leak current in this region. However, when the source/drain
voltage (forward bias voltage) is increased, the band in the drain region
17 shifts to a lower portion than that shown in FIG. 2C with the
continuous line. As a result, the electric field across the channel
forming region 15 and the drain region 17 becomes steep, causing a leak
current through grain boundaries.
The above analysis can be proved by experiments where a leak current is not
so remarkable when the voltage V.sub.D between the source and drain region
is small, it increases as the V.sub.D increases, and it becomes more
larger when the reverse bias voltage (i.e. a negative voltage in the case
of a NTFT) increases. See FIG. 2D.
Accordingly, the electric field in a region between the channel and drain
regions has to change moderately even when the source/drain voltage
V.sub.D is large in order to reduce the leak current.
In particular, the foregoing problem is more significant when the active
layer contains a metallic element for promoting a crystallization thereof
even though the concentration of the element is very small. Examples of
the metallic element are Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V,
Cr, Mn, Cu, Zn, Au, and Ag. These elements are added in a silicon
semiconductor in order that a crystallization temperature of the
non-crystalline silicon is lowered and the time for crystallization can be
reduced. However, these elements tend to form intermediate levels within
the band gap and have a same function as grain boundaries, resulting in an
increase of a leak current.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to solve the foregoing problems and
provide an excellent TFT or semiconductor integrated circuits employing
those TFTs. Specifically, an object of the invention is to minimize a leak
current of a TFT when applying a reverse bias voltage thereto.
In accordance with a first aspect of the invention, an active layer of a
TFT is provided with a region having a larger band gap (Eg) by adding
thereto an appropriate impurity such as oxygen, nitrogen or carbon. Also,
a similar effect can be obtained by irradiating a portion of an active
layer in an amorphous state or polycrystalline state with high speed ions
which are accelerated with an acceleration voltage of 30 eV, for example.
The portion of the semiconductor layer is damaged by the bombardment with
the ions, and the crystallinity of this portion is not completely cured
even with a subsequent crystallization step such as a heat annealing step.
As a result, the leak current can be lowered because of the existence of
this lower crystallinity region. The ions to be utilized are preferably
those of oxygen, carbon, nitrogen or silicon. It is also preferable that
hydrogen ions are mixed with these ions.
It is another object of the invention to provide an integrated circuit for
an electro-optical device such as a liquid crystal device by forming on a
same substrate a first group of TFTs for driving pixels (pixel TFTs), a
second group of TFTs for constituting decoder or driver circuits and a
third group of TFTs for constituting a memory or CPU.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing objects and features of the invention will be explained in
more detail in preferred embodiments of the invention with reference to
the attached drawings in which:
FIG. 1A is a cross sectional view showing a TFT in accordance with the
present invention;
FIG. 1B is a band gap diagram of the TFT shown in FIG. 1A;
FIG. 1C is a band gap diagram of the TFT shown in FIG. 1A in a reverse bias
condition;
FIG. 1D shows a voltage-current characteristics of a TFT in accordance with
the present invention;
FIG. 2A is a cross sectional view showing a TFT of a prior art;
FIG. 2B is a band gap diagram of the TFT shown in FIG. 2A;
FIG. 2C is a band gap diagram of the TFT shown in FIG. 2A in a reverse bias
condition;
FIG. 2D shows a voltage-current characteristics of a TFT of a prior art;
FIGS. 3A-3E are cross sectional views showing a manufacturing method of a
TFT in accordance with the first example of the invention;
FIGS. 4A-4E are cross sectional views showing a manufacturing method of a
TFT in accordance with the second example of the invention;
FIGS. 5A-5E are cross sectional views showing a manufacturing method of a
TFT in accordance with the third example of the invention;
FIGS. 6A-6E are cross sectional views showing a manufacturing method of a
TFT in accordance with the fourth example of the invention;
FIG. 7 is a block diagram showing a thin film semiconductor integrated
circuit in accordance with the second preferred embodiment of the
invention;
FIGS. 8A-8D are cross sectional views showing a manufacturing method of a
thin film semiconductor integrated circuit in accordance with the fifth
example of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
A first preferred embodiment of the invention relates to a method in which
a leak current is reduced by increasing a band gap of an active layer of a
TFT. In an offset gate type TFT such as shown in FIG. 2A, if the band gap
increases, even though the steepness of the electric field between the
channel region and the drain region is unchanged, the hopping conduction
of the carriers from the valence band (or conduction band) of the channel
region to a conduction band (or a valence band) of the drain region can be
suppressed because the gap between the conduction band and the valence
band is increased and the effect of the offset-gate area increases. The
band gap of a silicon semiconductor can be increased by adding impurities
such as carbon, nitrogen or oxygen. As the increase in the concentration
of the impurity, it is possible to increase the band gap, however, the
characteristics of the semiconductor tends to degrade.
Accordingly, the concentration of these impurities in total should be
within a range of 1.times.10.sup.19 atoms/cm.sup.3 to 2.times.10.sup.21
atoms/cm.sup.3, preferably, 5.times.10.sup.19 to 7.times.10.sup.20
atoms/cm.sup.3. In the meantime, the concentration of these impurities is
a minimum value in a secondary ion mass spectroscopy (SIMS).
In the above method, however, there is a drawback that the ON current when
applying a forward bias voltage to the gate electrode is undesirably
reduced because the channel region is also added with the above
impurities. In order to solve such a drawback, this inventor proposes to
provide regions 4 and 6 in a semiconductor layer as shown in FIG. 1A. That
is, the regions 4 and 6 are located between the impurity regions 3, 7 and
the channel 5 and have a larger band gap and resistivity than the channel
region 5. The regions 4 and 6 may be substantially intrinsic or have the
same conductivity type which is the same as the impurity regions 3 and 7
in such a degree that a parasitic channel can be suppressed. FIG. 1B shows
an energy band diagram of a portion of an NTFT close to a gate electrode.
As can been seen, E.sub.1 is smaller than E.sub.0, and generally, E.sub.1
is smaller than E.sub.N. Accordingly, the TFT has such a configuration in
which E.sub.1 <E.sub.0 .ltoreq.E.sub.N, alternatively, N.sub.1 <N.sub.0
.ltoreq.N.sub.N where N is a concentration of the added impurities carbon,
oxygen and/or nitrogen.
Also, FIG. 1C shows an energy band diagram in the case that a negative
(reverse) bias voltage is applied to a gate electrode. As is clear from
the diagram, the regions 4 and 6 significantly prevent carriers from
flowing between the conduction (valence) band of the impurity region and
the valence (conduction) band of the channel region. As a result, as shown
in FIG. 1D, the off current reduces, especially, and even when the
source/drain voltage V.sub.D is relatively large, the off current can be
stabilized as compared with a conventional offset gate TFT.
At the same time when the regions 4 and 6 are doped with C, N and O
impurities, the impurity regions 3 and 7 may also be doped with the same
impurities at the same concentration. At this time, the energy band gap
E.sub.0 of the regions 4 and 6 equals the energy band gap EN of the
impurity regions 3 and 7.
The foregoing impurities may be added by ion doping or ion injection
method. A thermal annealing, laser annealing or a lump annealing should be
performed after the doping in order to cure the semiconductor film which
is damaged during the addition of the impurity. Thus, the added impurities
can uniformly combine with silicon atoms and grain boundaries can be
neutralized. In particular, in the case of the configuration shown in FIG.
1A, it is desirable that the P-type or N-type impurity in the impurity
regions is simultaneously activated. In the alternative, when the entire
region of the semiconductor layer is doped with the impurity as explained
above, the impurity may be added simultaneously during the deposition of
the semiconductor layer. In such a case, the concentration of the impurity
is of course uniform throughout the semiconductor layer. The followings
are examples of the manufacture of TFTs in accordance with the foregoing
method.
[EXAMPLE 1]
FIGS. 3A-3E are cross sectional views showing a manufacturing method of a
TFT. Initially, referring to FIG. 3A, silicon oxide is deposited onto a
substrate 101 (Corning 7059) by sputtering to a thickness 2000 .ANG. to
form an underlying layer 102. The substrate is preferably heated at a
temperature higher than a distortion point of the substrate and then
gradually cooled at a cooling rate of 0.1.degree. to 1.0.degree. C./minute
to a temperature less than the distortion point. Thereby, it is possible
to reduce the contraction of the substrate due to heating in subsequent
steps, resulting in an improvement of the accuracy of the mask alignment.
In the case of a Corning 7059, the substrate is heated at
620.degree.-660.degree. C. for 1-4 hours, then cooled at a rate
0.01.degree. to 1.0.degree. C./minute, preferably,
0.03.degree.-0.3.degree. C./minute to 400.degree.-500.degree. C., at which
temperature the substrate is taken out from a furnace. (This step is
called "preheating" hereinafter.) The preheating may be performed either
before or after the formation of the underlying film.
Then, an intrinsic amorphous silicon film 103 is formed by a plasma CVD to
a thickness 200-2000 .ANG., preferably, 300-1500 .ANG., for example 1200
.ANG. on the underlying film 102. Further, a silicon oxide film 104 is
formed thereon by plasma CVD to a thickness of 100-800 .ANG., for example,
200 .ANG.. The silicon oxide film 104 functions as a blocking layer in
order to prevent the surface of the silicon film from being damaged during
subsequent heating step.
Further, oxygen ions are introduced into the semiconductor film 103 at a
dose 1.times.10.sup.14 -3.times.10.sup.16 atoms/cm.sup.2, for example at
2.times.10.sup.15 atoms/cm.sup.2 through an ion injection method. The
injection is carried out in such a manner that injection energy is
selected so that a peak of the concentration locates at the boundary
between the amorphous silicon film 103 and the underlying film 102. As a
result, the amorphous silicon film 103 is added with oxygen at
5.times.10.sup.19 to 2.times.10.sup.21 atoms/cm.sup.3 (the concentration
depends upon the deepness). This can be measured through SIMS analysis.
The addition of the oxygen may be ,carried out at the same as the
deposition of the silicon film. Subsequently, the silicon film is
crystallized through a heat annealing at 600.degree. C. for 48 hours in a
nitrogen gas (atmospheric pressure). After the crystallization, the
silicon oxide film 104 is removed. The crystallized silicon film is
patterned into an island form comprising an intrinsic or substantially
intrinsic polycrystalline silicon to become an active layer 105 of a TFT
as shown in FIG. 3B. Here, the term "substantially intrinsic" implies that
the semiconductor may be slightly inclined to N- or P-. The active layer
105 has a dimension from 50 .mu.m.times.20 .mu.m to 100 .mu.m.times.1000
.mu.m, which is determined considering the channel length and the channel
width of the TFT. It should be noted that while only one silicon island is
shown in the figure, a number of silicon islands are to be formed
simultaneously on the substrate.
Then, a silicon oxide film 106 is formed through a plasma CVD over the
silicon island 105 as a gate insulating film. TEOS [tetra-ethoxy-silane,
Si(OC.sub.2 H.sub.5)] and oxygen are used as a starting gas for the CVD.
The substrate temperature is in the range of 300.degree. to 550.degree.
C., for example, 400.degree. C. A thermal oxidation may be employed
instead of the plasma CVD.
Then, a gate electrode 107 is formed on the gate insulating layer 106 by
depositing aluminum through sputtering to a thickness of 3000-8000 .ANG.,
for example, 6000 .ANG. and patterning it. The aluminum may contain
scandium or other IIIa group element (i.e. rare earth element) therein at
0.01-0.25%. It is also possible to use another metal such as tantalum,
titanium, or a semiconductor material doped with phosphorous in place of
aluminum.
Referring to FIG. 3C, an oxide layer 108 is formed by anodically oxidizing
the surface of the aluminum electrode. The anodic oxidation may be carried
out using an ethylene glycol solvent in which a tartar acid is added at
1-5%. The thickness of the oxide layer is 2000 .ANG., for example. Since
source and drain regions are to be defined in approximately alignment with
the outer edge of the oxide layer, it is possible to determine the
thickness of an offset gate area by the anodic oxidation step.
Then, N-type impurity is introduced into the silicon island 105 by using
the gate electrode portion (including the gate electrode 107 and the
surrounding oxide layer 108) as a mask in a self-aligning manner through
an ion doping method (also called as plasma doping method). Phosphine gas
(PH.sub.3) is used as a doping gas. The accelerating voltage is 60-90 kv,
for example, 80 kV. The dose is in the range of 1.times.10.sup.15
atoms/cm.sup.2 to 8.times.10.sup.15 atoms/cm.sup.2, for example,
5.times.10.sup.15 atoms/cm.sup.2. As a result, N-type impurity regions 109
and 110 are formed as source and drain regions. (FIG. 3D).
Then, as shown in the drawing, a laser irradiation is carried out from an
upper portion of the gate electrode in order to activate the added
impurity. A KrF excimer laser (wavelength: 248 nm, pulse duration: 20
nsec.) or other lasers may be used as a light source. The energy density
is 200-400 mJ/cm.sup.2, for example, 250 mJ/cm.sup.2 ; and 2 to 10 shots,
e.g. 2 shots are used per one site. Also, the substrate may be heated at
200.degree.-450.degree. C. during the laser irradiation in order to
enhance the effect of the irradiation.
Alternatively, a lump anneal (also called rapid thermal anneal, RTA) with a
visible or near IR light may be used instead of the laser. The visible or
near IR light is easy to be absorbed by a crystalline silicon or an
amorphous silicon added with phosphorous or boron at 10.sup.19 to
10.sup.21 atoms/cm.sup.3 and can achieve an effect comparable with that
obtained through a heat annealing at 1000.degree. C. or higher. This can
be understandable because these silicon films are observed as a black
color by the eye. On the other hand, since the visible or near IR light is
not absorbed by a glass substrate so much, the substrate is not so heated
and the heating time may be shorter. Accordingly, this method is desirable
when a contraction of the glass substrate by heat is problematic.
Referring to FIG. 3E, after the activation of the impurity, a silicon oxide
film 111 of a thickness 6000 .ANG. is formed as an interlayer insulator
through a plasma CVD. A multilayer film of polyimide and silicon oxide, or
a single layer of polyimide | | |
