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Description  |
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FIELD OF USE
This invention relates to semiconductor devices. More particularly, this
invention relates to bipolar transistors, including structures and methods
for manufacturing high-frequency bipolar transistors.
BACKGROUND
Bipolar transistors are used in digital applications where the transistors
must be capable of switching between different states very rapidly.
Bipolar transistors also provide gain in high-frequency analog
applications. Accordingly, the transistor cutoff frequency f.sub.T is an
important parameter in designing a bipolar transistor for such a
high-frequency digital or analog application. Cutoff frequency f.sub.T is
the frequency at which the small-signal current gain drops to 1. Another
important transistor design parameter is the collector saturation current
I.sub.S per unit area.
Reducing transistor size in order to increase the number of bipolar
transistors that can be packed in a given lateral area is a common
transistor design objective. As the transistor lateral dimensions are
scaled down, the vertical dimensions are also often scaled down, with the
result that the base becomes thinner. In scaling down the base, both
cutoff frequency f.sub.T and collector saturation current I.sub.S normally
increase. This is advantageous.
In a simplified one-dimensional analysis, the increase in parameters
f.sub.T and I.sub.S with decreasing metallurgical base thickness t.sub.B
can be seen from the following equations that apply to a single-emitter
npn transistor:
##EQU1##
where:
.alpha..sub.O is the static common-base current gain (nearly 1),
D.sub.n is the average electron diffusivity in the base,
t.sub.BEFF is the effective electrical thickness of the base--i.e., the
distance between the boundaries of the emitter-base and collector-base
depletion regions,
q is the electronic charge,
n.sub.i is the intrinsic electron density (approximately
1.4.times.10.sup.10 electrons/cm.sup.3 in silicon at room temperature),
N.sub.A is the base (acceptor) dopant concentration, and
x is an integrating variable in the base along the direction of main
current flow.
Effective base thickness t.sub.BEFF decreases as metallurgical base
thickness t.sub.B --i.e., the distance between the emitter-base and
collector-base junctions--decreases. Since t.sub.BEFF is in the
denominator of Eq. 1, cutoff frequency f.sub.T increases with decreasing
t.sub.BEFF. Use of t.sub.BEFF in the dopant integral of Eq. 2 indicates
that this integral, commonly referred to as the base Gummel number, is
taken across the quasi-neutral region of the base--i.e., the region
extending between the two depletion regions. The base Gummel number
generally decreases as t.sub.BEFF, and thus t.sub.B, decrease. As a
result, collector saturation current I.sub.S increases with decreasing
t.sub.B.
The collector current I.sub.C per unit area is determined from saturation
current I.sub.S according to the following approximate relationship:
I.sub.C =I.sub.S exp (q V.sub.BE /k T) (3)
where:
V.sub.BE is the base-to-emitter voltage,
k is Boltzmann's constant, and
T is the absolute temperature.
Since saturation current I.sub.S increases with decreasing base thickness
t.sub.B, collector current I.sub.C advantageously increases as t.sub.B is
down-scaled.
The current gain .beta. is also an important factor in designing a
high-frequency bipolar transistor. Current gain .beta. is defined as
I.sub.C /I.sub.B where I.sub.B is the base current per unit area. For
highly simplified conditions (i.e., uniform, abrupt-junction dopant
profiles with ideal emitter efficiency), current gain .beta. is given
approximately as:
##EQU2##
where L.sub.n is the minority carrier diffusion length in the base.
Although Eq. 4 is a rough approximation, it reflects the fact that .beta.
increases as metallurgical base thickness t.sub.B is reduced. The net
result is that parameters f.sub.T, I.sub.S, I.sub.C, and .beta. all
increase when the base is made thinner.
Eqs. 1-4 are available in prior art semiconductor literature. See: Philips,
Transistor Engineering (McGraw-Hill; reprinted: Robert E. Krieger Pub.
Co., 1981), 1962, pages 298-304; Warner et al, Transistor Fundamentals for
the Integrated-Circuit Engineer (John Wiley & Sons), 1983, pages 559-562;
and Grove, Physics and Technology of Semiconductor Devices (John Wiley &
Sons), 1967, pages 219-222.
In a vertical bipolar transistor, the emitter adjoins a surface, referred
to here as the upper surface, of a semiconductor body. The base consists
of an intrinsic part (commonly termed the "intrinsic base") and one or
more laterally adjoining extrinsic parts (commonly termed "extrinsic
bases"). The intrinsic base lies directly below the emitter. Each
extrinsic base includes a heavily doped base contact zone which extends to
the upper surface of the semiconductor body and to which electrical
contact is made at a location spaced laterally apart from the emitter.
The collector typically includes a lightly to moderately doped main
collector region situated directly below the intrinsic base. The collector
further includes a heavily doped buried layer that lies below the main
collector region and extends laterally beyond the intrinsic base to a
heavily doped collector contact zone which typically extends to the upper
semiconductor surface to provide electrical access to the collector.
Overlying electrical contacts to the emitter and to the contact zones
complete the basic transistor. Additionally, a field-isolation region
typically surrounds the emitter and base to separate the base from the
collector contact zone and from other device elements in the semiconductor
body.
The field-isolation region in many high-frequency bipolar transistors is
formed with electrically insulating material, typically silicon oxide,
whose sidewalls terminate the base. As used here, "terminate" means that
the terminated item extends to the item which performs the termination.
FIGS. 1a and 1b, which are taken at vertical cross sections perpendicular
to each other, illustrate a typical prior art npn transistor whose base is
terminated at an oxide-isolation region of the LOCOS type. For example,
see Alvarez, BiCMOS Technology and Applications (Kluwer Acad. Pub., 2d
ed.), 1993, pages 96-100, in regard to the cross section of FIG. 1a.
The transistor in FIGS. 1a and 1b is fabricated from a semiconductor body
consisting of p-silicon substrate 20 and overlying n-silicon epitaxial
layer 22. N+buried collector layer 24 lies along the metallurgical
interface between substrate 20 and epitaxial layer 22. Field oxide 26
serves as the oxide-isolation region. N+emitter 28 is created in a
self-aligned manner by out-diffusion from n+emitter contact 30. The
remaining transistor elements are p-base layer 32, a pair of p+base
contact zones 34, n-main collector region 36, and n+collector contact zone
38. The intrinsic base consists of the portion of base layer 32 underlying
emitter 30.
In transistor structures of the foregoing type, the emitter is typically
configured as a finger (or stripe) which is terminated at both ends by
sidewalls of the field-isolation region. See FIG. 1b. This configuration
is referred to here as a "walled-emitter" structure. Walled-emitter
transistors are advantageous because they make highly efficient use of the
active area. The parasitic collector-base capacitance is quite low for a
given active area, thereby improving performance.
Ratnam et al, "The Effect of Isolation Edge Profile on the Leakage and
Breakdown Characteristics of Advanced Bipolar Transistors," IEEE Bipolar
Cirs. & Tech. Meeting, 7-8 Oct. 1992, pages 117-120, deals with
walled-emitter bipolar transistors. Ratnam et al observed that the emitter
termination regions of a walled-emitter vertical bipolar transistor
typically cannot accommodate the same degree of down-scaling as the
intrinsic transistor region without adversely affecting the
collector-to-emitter leakage current and the collector-to-emitter
breakdown voltage of the entire transistor. In particular, the high values
of local current gain that can be obtained by vertically down-scaling the
intrinsic base are not desirable at the emitter termination regions where
two-dimensional doping effects can readily cause premature
collector-to-emitter avalanche breakdown to occur.
The influence of the emitter termination regions on collector-to-emitter
leakage current and breakdown voltage is difficult to express in simple
first-order equations because of the two-dimensional nature of the dopant
profiles in the termination regions. Nonetheless, a rough approximation of
breakdown voltage BV.sub.CEO and the collector-to-emitter leakage current
I.sub.CEO per unit area can be obtained from the following equations:
##EQU3##
where:
I.sub.CBO is the leakage current per unit area of the collector-base
junction,
BV.sub.CBO is the breakdown voltage of the collector-base junction,
n, typically in the range of 4-8, is an empirically determined coefficient,
X.sub.CB is the thickness of the collector-base depletion region at a given
value of collector-to-emitter voltage V.sub.CE, and
.tau..sub.O is the carrier generation lifetime in the vicinity of the
collector-base junction.
As with Eqs. 1-4, Eqs. 5 and 6 are available in prior art semiconductor
literature. See: Grove, cited above, pages 230-234; and Muller et al,
Device Electronics for Integrated Circuits (John Wiley & Sons), 1977,
pages 174-179.
Leakage current I.sub.CBO approaches infinity at a value of
collector-to-emitter voltage V.sub.CE equal to collector-to-emitter
breakdown voltage BV.sub.CEO. Accordingly:
##EQU4##
Eqs. 5-7 can be separately applied to the intrinsic and emitter-termination
regions of the transistor. Regardless of how accurate Eqs. 5-7 are, they
reflect the fact that high local values of current gain .beta. caused by
down-scaling the intrinsic base or by two-dimensional doping effects
reduce breakdown voltage BV.sub.CEO and increase leakage current
I.sub.CEO. Such two-dimensional effects occur in advanced BiCMOS processes
where the intrinsic base is doped from overlying polysilicon as observed
in Ratnam et al, cited above.
Ratnam et al also observed that the two-dimensional doping effects are
strongly dependent on the slope of the isolation-oxide sidewalls,
especially those having the "bird's beak" shape characteristic of
fabrication processes in which the field-isolation region consists
primarily of thermally grown silicon oxide. This dependency can be
attributed to the combined effects of (a) impurity segregation into the
oxide-isolation region and (b) base diffusion blocking by the "bird's
beak" portion of the isolation oxide. It would be desirable to reduce
current gain .beta. at the emitter termination regions so as to preserve
or increase breakdown voltage BV.sub.CEO for the entire transistor.
Independent of avalanche-caused collector-to-emitter breakdown,
down-scaling of the intrinsic base can cause punch-through to occur at the
emitter termination regions. At punch-through, the depletion region of the
collector-base junction reaches the depletion region of the emitter-base
junction so as to eliminate the normally intervening quasi-neutral base
region in which diffusion limits the current flow. The number of electrons
passing through the base thereby increases rapidly in a generally
undesirable manner as collector-to-emitter voltage V.sub.CE is increased.
Breakdown voltage BV.sub.CEO is again impaired.
Ratnam, U.S. Pat. No. 5,338,695, describes a technique for improving
parameters BV.sub.CEO and I.sub.CEO in a walled-emitter vertical bipolar
transistor. The edges of the intrinsic base below the emitter termination
regions are selectively provided with additional base dopant, typically by
outdiffusion from overlying polysilicon. The thickness of the intrinsic
base is thereby increased below the emitter termination regions. This
typically produces an increase in breakdown voltage V.sub.CEO and a
decrease in leakage current I.sub.CEO. While Ratnam mentions the
transistor current gain and the cutoff frequency f.sub.T, Ratnam does not
actively address improving these parameters.
Konaka et al, "A 20 ps/G Si Bipolar IC Using Advanced SST with Collector
Ion Implantation," Procs. Solid State Devs. & Mats. Conf., 1987, pages
331-334, describes a vertical bipolar transistor that utilizes a selective
collector implant to improve cutoff frequency f.sub.T and the maximum
collector current density. FIG. 2 illustrates part of the transistor in
Konaka et al. The transistor includes p-silicon semiconductor substrate
40, overlying n-epitaxial silicon collector portion 42, buried n+collector
layer 44 along the substrate/epi interface, and field-isolation region 46
of the trench type. N+polysilicon emitter contact 48 contacts n+emitter 50
in a self-aligned manner. The transistor further includes p base layer 52,
a pair of laterally separated p base contact zones 54, and p+polysilicon
base contact 56.
Konaka et al performs a selective ion implantation to increase the net
collector doping below the emitter and intrinsic base. Item 58 in FIG. 2
is the resulting selectively ion-implanted collector ("SIC") zone. The
increased collector doping in SIC zone 58 shallows up the base thickness
beyond the limits imposed by the base ion-implantation profile. SIC
collector zone 58 causes the base push-out (Kirk) effect to occur at a
higher value of the collector current density. The maximum
collector-current density thus occurs at a greater value of cutoff
frequency f.sub.T. Metallurgical base thickness t.sub.S decreases as the
doping level of collector zone 58 increases. Reducing the base thickness
and the base push-out effect thereby improves the cutoff frequency f.sub.T
and the maximum collector-current density.
In the cross section of FIG. 2, emitter 50 does not terminate at the
sidewalls of field-isolation region 46. Konaka et al does not provide a
vertical device cross section perpendicular to the cross section of FIG.
2. Nonetheless, Konaka et al employs a double-polysilicon self-aligned
fabrication process which is generally understood to produce bipolar
transistors whose emitters do not terminate at the isolation-oxide
sidewalls. Although Konaka et al can improve cutoff frequency f.sub.T,
their utilization of the active transistor area is relatively inefficient.
It is desirable to have a bipolar transistor that efficiently utilizes the
active area while improving cutoff frequency f.sub.T, the overall
transistor current gain, breakdown voltage BV.sub.CEO, and leakage current
I.sub.CEO.
GENERAL DISCLOSURE OF THE INVENTION
The present invention utilizes selective doping to increase the cutoff
frequency and current gain of a vertical bipolar transistor suitable for
high-frequency operation. The present transistor is of the walled-emitter
type in that the emitter and underlying portion of the base adjoin a
field-isolation region. The selective doping of the invention is provided
in the collector and, optionally, in one or more parts of the base. When
the base is selectively doped according to the invention, the
collector-to-emitter leakage current and collector-to-emitter breakdown
voltage are typically improved without adversely affecting other
transistor performance characteristics.
The bipolar transistor of the invention is provided with an emitter,
collector, and intervening base situated in a vertical arrangement in a
semiconductor body. The emitter overlies an intrinsic portion of the base.
The emitter and base are situated in a semiconductor device region. The
field-isolation region, typically formed with electrically insulating
material such as semiconductor oxide, laterally surrounds the
semiconductor device region and is sunk into the semiconductor body along
its upper surface. Parts of the emitter and the intrinsic portion of the
base adjoin the field-isolation region, typically along a pair of
laterally separated opposing internal sidewalls of the field-isolation
region. The emitter parts which adjoin the field-isolation region
constitute a pair of emitter-termination regions.
A main region of the collector forms a collector-base junction with the
base. The main collector region includes a special collector zone situated
along the collector-base junction in the semiconductor device region below
the intrinsic base portion. The special collector zone has a greater net
doping than directly underlying material of the collector.
The presence of the special collector zone causes the intrinsic base
portion to be thinner, thereby raising the cutoff frequency and overall
current gain. At the same time, the usage of active area is very efficient
because the transistor is a walled-emitter device. In addition to a low
parasitic collector-base capacitance, the walled-emitter nature of the
present transistor enables the first level of interconnection to be done
with doped polycrystalline semiconductor material so as to increase device
packing density.
Importantly, the special collector zone is spaced laterally apart from the
field-isolation region. Accordingly, the special collector zone is
laterally separated from the emitter termination regions along the
field-isolation region. The lateral separation of the special collector
zone from the emitter termination regions provides a degree of freedom in
controlling the transistor characteristics. In particular, a design margin
is provided for adjusting the base doping to improve the leakage current
and breakdown voltage characteristics of the emitter termination regions.
Additional doping of the base is preferably done in semiconductor material
situated below one or both emitter termination regions. The intrinsic base
portion then constitutes a main intrinsic base segment and one or two side
intrinsic base segments continuous with the main intrinsic base segment.
Each side intrinsic base segment has a greater net doping, and/or a
greater minimum base thickness, than the main intrinsic base segment. The
doping of each side intrinsic base segment can be readily adjusted to
substantially avoid premature avalanche charge multiplication and
punch-through at that side intrinsic base segment.
In particular, increasing the doping at the longitudinal sides of the base
below the emitter termination regions causes the portions of the
collector-base junction along the longitudinal sides of the base to move
further down into the device region, thus increasing both the
metallurgical base thickness and the effective base thickness at the
longitudinal sides. Also, the increased doping at the longitudinal sides
of the base reduces the minority carrier diffusion length there under
forward bias. This causes increased recombination of charge carriers to
occur at the longitudinal sides of the base.
Due to the preceding effects, the local current gain is reduced at the
longitudinal sides of the base below the emitter termination regions.
Likewise, the local collector-to-emitter breakdown voltage is increased at
the longitudinal sides of the base, thereby raising the overall
collector-to-emitter breakdown voltage to at least the level of the
intrinsic portion of the transistor. The overall collector-to-emitter
leakage current is simultaneously reduced.
The selective doping of the intrinsic base at each side intrinsic base
segment is decoupled from the selective doping used to create the special
collector zone. Accordingly, the characteristics of the side intrinsic
base segments can be optimized according to the details of the isolation
and impurity profiles in the vicinity of the field-isolation region.
In manufacturing the present bipolar transistor, the following steps are
performed on a semiconductor body provided with a patterned
field-isolation region sunk into the body along its upper surface so as to
laterally surround a semiconductor device region. A primary base dopant is
introduced into the device region to define a base layer. An emitter
dopant is selectively introduced generally shallower into the device
region than the primary dopant to define the emitter in part of the base
layer. A collector dopant is selectively introduced, typically by ion
implantation, generally deeper into the device region than the primary
dopant to define the special collector zone. The three doping steps can be
initiated in various orders. The emitter and collector dopants are of a
first conductivity type, while the base dopant is of a second conductivity
type opposite to the first conductivity type.
Each side intrinsic base segment is formed by selectively introducing an
additional base dopant into the device region through an upper surface
portion that overlies part of the intrinsic base portion and extends to
the field-isolation region. This doping is performed as a separate step
from the doping typically employed to form a heavily doped contact zone
for the base. Furthermore, the doping utilized to form the side intrinsic
base segments is preferably done by ion implantation. Consequently, the
spatial resolution is greater than that which would occur if the doping
were done by out-diffusion from overlying material such as polysilicon.
The present invention is especially useful where the sidewalls of the
field-isolation region are highly sloped. The implant energy for the ions
that form the side intrinsic base segments can be set at a level
sufficiently high that the ions pass through the upper ends of the
field-isolation region--e.g., the top of the "bird's beak" in the LOCOS
structure--and into the underlying semiconductor material. The leakage
current and breakdown voltage characteristics at the slanted sidewalls are
improved without having to perform additional processing to make the
sidewalls more vertical. The net result is that the invention provides a
significantly better bipolar transistor than that attainable in the prior
art.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a and 1b are cross-sectional transverse (front) and longitudinal
(side) views of a prior art vertical bipolar transistor. The cross section
of FIG. 1a is taken through plane 1a--1a in FIG. 1b. The cross section of
FIG. 1b is taken through plane 1b--1b in FIG. 1a.
FIG. 2 is a cross-sectional view of another prior art vertical bipolar
transistor.
FIGS. 3a and 3b are cross-sectional transverse and longitudinal views of a
walled-emitter vertical bipolar transistor provided with special collector
doping in accordance with the invention.
FIG. 4 is a partial layout view of the transistor in FIGS. 3a and 3b. The
cross section of FIG. 3a is taken through plane 3a--3a in FIGS. 3b and 4.
The cross section of FIG. 3b is taken through plane 3b--3b in FIGS. 3a and
4.
FIGS. 5a and 5b are cross-sectional transverse and longitudinal views of a
walled-emitter bipolar transistor provided with special collector doping
and base side doping in accordance with the invention.
FIG. 6 is a partial layout view of the transistor in FIGS. 5a and 5b. The
cross section of FIG. 5a is taken through plane 5a--5a in FIGS. 5b and 6.
The cross section of FIG. 5b is taken through plane 5b--5b in FIGS. 5a and
6.
FIGS. 7.1-7.8 are cross-sectional transverse views representing steps in a
process for manufacturing the transistor of FIGS. 5a, 5b, and 6 in
accordance with the invention.
FIGS. 8.1-8.3 are cross-sectional longitudinal views respectively
corresponding to FIGS. 7.3-7.5. The cross sections of FIGS. 7.3-7.5 are
taken respectively through planes 7.3--7.3, 7.4--7.4, and 7.5--7.5 in
FIGS. 8.1-8.3. The cross sections of FIGS. 8.1-8.3 are taken respectively
through planes 8.1--8.1, 8.2--8.2, and 8.3--8.3 in FIGS. 7.3-7.5.
FIGS. 9 and 10 are graphs for dopant concentration as a function of depth
for computer simulations of two baseline transistors.
FIGS. 11 and 12 are profile graphs illustrating lines of constant net
dopant concentration for computer simulations of the transistor in FIGS.
3a and 3b and a baseline transistor for the case in which the sidewalls of
the field-isolation regions are largely vertical.
FIGS. 13 and 14 are profile graphs for lines of constant net dopant
concentration for computer simulations of the transistor in FIGS. 5a and
5b and a baseline transistor for the case in which the sidewalls of the
field-isolation regions are in the "bird's beak" shape.
FIGS. 15 and 16 are graphs for linear open-base collector current as a
function of collector-to-emitter voltage for computer simulations of
transistors respectively having the profiles of FIGS. 11 and 12.
FIGS. 17 and 18 are graphs for linear open-base collector current as a
function of collector-to-emitter voltage for computer simulations of
transistors respectively having the profiles of FIGS. 13 and 14.
Like reference symbols are employed in the drawings and in the description
of the preferred embodiments to represent the same or very similar item or
items.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIGS. 3a and 3b illustrate a walled-emitter npn transistor configured
according to the teachings of the invention. FIG. 4 shows a layout for the
transistor in FIGS. 3a and 3b. The transistor of FIGS. 3a, 3b, and 4
(collectively "FIG. 3-4") has an emitter, a collector, and an intervening
base. As described further below, the collector is provided with increased
doping along part of the collector-base junction so as to increase the
cutoff frequency f.sub.T and the collector saturation current I.sub.S per
unit area. The collector current I.sub.C per unit area and the overall
transistor current gain are thereby increased. Furthermore, the collector
doping is provided in such a way as to enable the transistor's overall
breakdown voltage and leakage current characteristics to be improved. The
transistor is suitable for high-frequency digital and analog applications.
The npn transistor in FIG. 3-4 is created from a semiconductor body
consisting of a (100) lightly doped p-type monocrystalline silicon
substrate 60 and an overlying lightly doped n-type epitaxial silicon layer
62. P-substrate 60 typically has a net dopant concentration of
1.times.10.sup.15 atoms/cm.sup.3. N-epitaxial layer 62 typically has a net
dopant concentration of 1.times.10.sup.16 atoms/cm.sup.3. The thickness of
epitaxial layer 62 typically is 1.1 .mu.m.
A patterned electrically insulating field region 64 of silicon oxide is
sunk into the semiconductor body along the upper surface of n-epitaxial
layer 62. Field-oxide region 64 extends fully through epitaxial layer 62
and slightly into p-substrate 60 to divide epitaxial layer 62 into a group
of laterally separated semiconductor device regions. Two such device
regions are shown in FIG. 3a. The lateral dimension of the portion of
field oxide 64 lying between these two device regions is not drawn to
scale in FIGS. 3a and 4. Alternatively, field-oxide region 64 could extend
only partway through epitaxial layer 62. An upper portion of layer 62
would then be divided into a group of laterally separated semiconductor
device regions such as the two depicted in FIG. 3a.
For ease in illustration, the sidewalls of oxide-isolation region 64 have
been represented in FIGS. 3a and 3b as extending generally vertical with a
slight curving at the upper edges. Nonetheless, the isolation-oxide
sidewalls can be curved much more drastically than shown in FIGS. 3a and
3b. In fact, as discussed below, the invention is particularly useful in
applications where the upper edges of field-isolation region 34 generally
have the "bird's beak" profile characteristic of thermally grown silicon
oxide.
A heavily doped n-type buried collector layer 66 situated along the
metallurgical interface between substrate 60 and epitaxial layer 62
electrically interconnects the two semiconductor device regions in FIG.
3a. Buried n+layer 66 typically has a maximum net dopant concentration of
2.times.10.sup.19 atoms/cm.sup.3. An annular heavily doped p-type buried
channel-stop region 68 also lies along the metallurgical interface between
substrate 60 and layer 62. P+channel-stop region 68 laterally surrounds
n+collector layer 66 and extends upward to meet field-oxide region 64. The
maximum net dopant concentration in channel stop 68 typically is
8.times.10.sup.17 atoms/cm.sup.3.
The transistor's emitter is a heavily doped n-type zone 70 situated in the
left-hand device region (FIG. 3a) along the upper surface of the
semiconductor body. The maximum net dopant concentration in N+emitter 70
occurs at the upper semiconductor surface and typically is
1.times.10.sup.20 atoms/cm.sup.3. Emitter 70 typically extends to a depth
of 0.07 .mu.m into epitaxial layer 62.
FIG. 3-4 shows that, as viewed in a direction generally perpendicular to
the upper semiconductor surface, emitter 70 is in the shape of a finger.
Both ends of emitter finger 70 adjoin the sidewalls of oxide-isolation
region 64 in the longitudinal direction. See FIG. 3b. Items 70A are the
two emitter termination regions at the ends of emitter finger 70.
An overlying heavily doped n-type polysilicon emitter contact 72 contacts
emitter 70 in a self-aligned manner. N+emitter contact 72 is covered with
a thin metal silicide cap 74.
The base of the transistor consists of a moderately doped p-type base layer
76 and a pair of heavily doped p-type base contact zones 78 located on
opposite sides of emitter 70. The combination of p base layer 76 and
p+base contact zones 78 extends fully across the left-hand semiconductor
device region in FIG. 3a to adjoin the sidewalls of field oxide 64 in the
transverse direction. Base layer 76 also adjoins field oxide 64 in the
longitudinal direction as shown in FIG. 3b. The maximum net dopant
concentration in base layer 76 occurs at the upper semiconductor surface
at a value in the range of 1.times.10.sup.17 -5.times.10.sup.18
atoms/cm.sup.3, typically 1.times.10.sup.18 atoms/cm.sup.3. P+base contact
zones 78 typically reach a maximum net dopant concentration of
1.times.10.sup.19 atoms/cm.sup.3.
Components 76 and 78 are divided into an intrinsic base and a pair of
extrinsic bases situated symmetrically on opposite sides of the intrinsic
base. The portion of p base layer 76 located directed below emitter 70
constitutes the intrinsic base. Its thickness typically is 0.1 .mu.m. Each
extrinsic base consists of one base contact zone 78 in combination with
the adjoining part of base layer 76 outside the intrinsic base.
Each base contact zone 78 contacts an overlying heavily doped p-type
polysilicon base contact 80. In the illustrated example, parts of p base
layer 76 situated in the extrinsic bases also make contact with p+base
contact 80. A thin metal silicide cap 82 extends from contact zone 78 to
base contact 80 to reduce the base resistance. Although not shown in FIG.
4, base contact 80 and cap 82 are typically in the shape of a "U" that
extends from one of the extrinsic bases to the other.
A pair of electrically insulating spacers 84 consisting of silicon oxide
are situated along the sidewalls of polysilicon emitter contact 72. Oxide
sidewall spacers 84 laterally separate metal silicide cap 82 from emitter
contact 72 and metal silicide cap 74 so as to avoid short circuiting the
base to emitter 70.
The transistor's collector includes a main collector region formed with the
epitaxial material situated between n+buried layer 66 and p base layer 76.
The main collector region consists of a lightly doped n-type epitaxial
portion 86 and a moderately doped n-type special collector zone 88
situated along the collector-base junction. The maximum net dopant
concentration in n special collector zone 88 is in the range of
1.times.10.sup.16 -5.times.10.sup.17 atoms/cm.sup.3, typically
7.times.10.sup.16 atoms/cm.sup.3.
Special collector zone 88 lies below the intrinsic base and emitter 70.
However, as shown in FIG. 4, collector zone 88 is in the shape of a
rectangle spaced laterally apart from the sidewalls of field oxide 64 in
both the transverse (FIG. 3a) and longitudinal (FIG. 3b) directions.
Collector zone 88 is thus a "non-walled" region. For an emitter length of
1.2-2.4 .mu.m, typically 1.6 .mu.m, the distance between field oxide 64
and each nearest end of collector zone 88 in the longitudinal direction
(FIG. 3b) is 0.2-0.6 .mu.m, typically 0.4 .mu.m.
The collector also includes n+buried layer 66 and a heavily doped n-type
collector contact region 90 that provides buried layer 66 with an
electrical path to the upper semiconductor surface through the right-hand
semiconductor device region in FIG. 3a. An overlying very heavily doped
n-type polysilicon collector contact 92 covered with a thin metal silicide
cap 94 contacts n+collector contact 90 to complete the transistor
structure.
During transistor operation, electrons in emitter 70 move generally
downward through the intrinsic base, special collector zone 88, and
epitaxial portion 86 to buried layer 66. The electrons then flow laterally
along buried layer 66 to collector contact zone 90 from where the
electrons move upward to the upper semiconductor surface.
Special collector zone 88 provides the transistor of FIG. 3-4 with improved
performance characteristics. In particular, the central part of the
intrinsic transistor--i.e., the part encompassed by the vertical
projection (both upward and downward) of collector zone 88--has higher
values of cutoff frequency f.sub.T and overall current gain then an
otherwise similar transistor that lacks collector zone 88. This occurs
because the additional doping along the collector-base junction causes
metallurgical base thickness t.sub.B to be reduced. Since effective
electrical base thickness t.sub.BEFF (between the depletion regions of the
collector-base and emitter-base junctions) is thereby also reduced, cutoff
frequency f.sub.T and saturation current I.sub.S per unit area increase,
consistent with Eqs. 1 and 2. In accordance with Eqs. 3 and 4, collector
current I.sub.C per unit area and the overall current gain of the
transistor likewise increase.
Inasmuch as special collector zone 88 is spaced apart from the sidewalls of
field ox | | |
