 |
Claims  |
|
|
We claim:
1. A field programmable logic device comprising:
a plurality of logic units, each logic unit connecting to:
a plurality of output lines extending from said logic unit comprising at
least a first output line and a second output line, said first output line
being shorter than said second output line; and
a plurality of input lines extending into said logic unit, each input line
connected to said logic unit so as to provide an input signal to said
logic unit; and
a plurality of programmable interconnection points (PIPs), each PIP being
programmable to connect one of said output lines to one of said input
lines; and
a multiplexer receiving input signals from a plurality of said output lines
and placing a signal from a selected one of said output lines onto an
extension line extending in the same direction as one of said output
lines, said extension line serving as a further input line to one of said
logic units.
2. A field programmable logic device as in claim 1 in which one of said
PIPs connects an output line from a first logic unit to an input line of a
second logic unit.
3. A field programmable logic device as in claim 1 in which one of said
PIPs connects an output line from a first logic unit to an input line of
said first logic unit.
4. A field programmable logic device as in claim 1 in which said logic
unit, output lines, input lines and PIPs are laid out in repeatable tiles,
each tile including output lines, input lines, PIPs, and all portions of
said logic unit, such that when a plurality of tiles is placed adjacent to
each other, said field programmable logic device is formed.
5. A field programmable logic device as in claim 1 in which said first and
second output lines include one output line two tiles long and one output
line four tiles long.
6. A field programmable logic device as in claim 1 in which said input
lines are two tiles long.
7. A field programmable logic device as in claim 1 in which said output
lines comprise at least two output lines extending in each of a plurality
of compass directions, the two lines in one compass direction being of
unequal lengths.
8. A field programmable logic device as in claim 1 in which said first and
second output lines connect to the same number of PIPs.
9. A field programmable logic device as in claim 1 in which PIPs are placed
on an output line such that the number of PIPs in one tile portion of an
output line decrease as distance from said logic unit increases.
10. A field programmable logic device as in claim 1 in which said first and
second output lines connect to a set of PIPs sized and of a number such
that the capacitive loads of said first and second output lines are
approximately the same.
11. A field programmable logic device as in claim 1 in which each of said
logic units comprises:
a logic element receiving some of said input lines for performing logical
operations on signals received on said input lines, and providing an
output therefrom;
a mux array driving some of said output lines; and
at least one line which receives an output signal from said logic element
and provides an input signal to said mux array, said mux array also
receiving a signal from at least one other logic unit.
12. A field programmable logic device as in claim 1 in which some of said
logic units comprise:
a logic element receiving some of said input lines for performing logical
operations on signals received on said input lines, and providing an
output. therefrom;
a mux array driving some of said output lines; and
at least one line which receives an output signal from said logic element
and provides an input signal to said mux array, said mux array also
receiving a signal from at least one other logic unit;
and in which other of said logic units comprise:
a random access memory receiving signals on some of said input lines and
supplying signals to some of said output lines.
13. A field programmable logic device as in claim 1 in which said PIP
comprises a buffer having an input terminal connected to said output line
and having an output terminal connected to a switch which programmably
connects a buffer output signal to said input line.
14. A field programmable logic device as in claim 1 in which said PIP
comprises a switch which programmably connects said one of said output
lines to said one of said input lines.
15. A field programmable logic device comprising a plurality of identical
adjacent tiles, each tile comprising:
a logic element having logic element input lines for providing input
signals to said logic element, and a logic element output line for
providing an output signal from said logic element;
an interconnect structure comprising:
a plurality of output segments which connect in adjacent tiles to form
output lines, a first output line having a length differing from that of a
second output line;
a plurality of input segments which connect in adjacent tiles to form input
lines, each input line being a logic element output line from said logic
element in said tile or from said logic element in another tile;
a mux array comprising a plurality of multiplexers, each programmable to
connect one of a set of said input lines to an output line; and
a plurality of PIPs, each PIP being programmable to connect one of said
output lines to one of said logic element input lines.
16. A field programmable logic device as in claim 15 in which one of said
output lines extending from a single mux array is of a different length
from another of said output lines extending from said single mux array.
17. A field programmable logic device as in claim 16 in which some of said
output segments connect to PIPs and some of said output segments do not
connect to PIPs.
18. A field programmable logic device as in claim 15 in which some of said
output lines connect to PIPs and some of said output lines do not connect
to PIPs.
19. A field programmable logic device as in claim 15 in which said output
lines each connect to a number of PIPs which causes all of said output
lines to have substantially the same signal delay.
20. A field programmable logic device as in claim 15 in which the density
of PIPs connected to said output lines decreases as distance from said mux
array driving said output lines increases.
21. A field programmable logic device as in claim 15 in which at least one
of said output lines can be coupled to an extension line which in turn
carries an input signal from said one of said output lines to another mux
array in another tile.
22. A field programmable logic device as in claim 21 in which said at least
one of said output lines is coupled to said extension line through a
single transistor.
23. A field programmable logic device as in claim 15 in which the density
of PIPs connected to an output line decreases as distance from said mux
array increases.
24. A field programmable logic device as in claim 15 in which at least one
of said output lines can be coupled to an extension line which in turn
carries a signal from said at least one of said output lines to another
mux array in another tile.
25. An FPGA comprising:
a plurality of logic elements, each logic element receiving input signals
from a plurality of input lines and providing at least one logic element
output signal on a corresponding logic element output lead;
a plurality of mux arrays;
for each mux array:
a plurality of output lines including at least a first output line and a
second output line, said first output line being of a length sufficiently
different from length of said second output line as to extent past a
different number of logic elements from said second output line;
for each output line in said mux array:
a plurality of programmable interconnection points (PIPs), which may be
programmed to connect one of said logic element output leads to said
output line; and
at least one programmable interconnection point (PIP) which may be
programmed to connect said output line to one of said logic element input
lines.
26. A programmable logic device comprising:
a plurality of configurable logic elements;
a plurality of multiplexer arrays; and
an interconnection network;
wherein:
one of said plurality of configurable logic elements, one of said plurality
of multiplexer arrays, and a portion of said interconnection network form
a tile,
said programmable logic device includes a plurality of said tiles, and
said interconnection network includes a plurality of lines of different,
predetermined lengths, said plurality of lines including lines:
(a) providing a direct interconnection between one of said configurable
logic elements and one of said multiplexer arrays;
(b) providing a direct interconnection between one of said multiplexer
arrays and another multiplexer array;
(c) providing connection between one of said multiplexer arrays and a
programmable interconnection point (PIP); and
(d) providing connection between one configurable logic element and another
configurable logic element.
27. A field programmable logic device comprising a plurality of logic
units, each logic unit connecting to:
a plurality of output lines extending from said logic unit comprising at
least a first output line and a second output line, said first output line
being shorter than said second output line;
a plurality of input lines extending into said logic unit, each input line
connected to said logic unit so as to provide an input signal to said
logic unit; and
a plurality of programmable interconnection points (PIPs), each PIP being
programmable to connect one of said output lines to one of said input
lines;
each logic unit comprising:
a logic element for performing logical operations on signals received on
said input lines and providing a logic element output signal therefrom;
a mux array driving some of said output lines; and receiving as input
signals said logic element output signal and a logic element output signal
from at least one other logic element.
28. A field programmable logic device comprising a plurality of logic
units, each logic unit connecting to:
a plurality of output lines extending from said logic unit comprising at
least a first output line and a second output line, said first output line
being shorter than said second output line;
a plurality of input lines extending into said logic unit, each input line
connected to said logic unit so as to provide an input signal to said
logic unit; and
a plurality of programmable interconnection points (PIPs), each PIP being
programmable to connect one of said output lines to one of said input
lines;
some of said logic units comprising:
a logic element for performing logical operations on signals received on
said input lines and providing a logic element output signal therefrom;
a mux array driving some of said output lines; and receiving as input
signals said logic element output signal and a logic element output signal
from at least one other logic element;
and others of said logic units comprising:
a random access memory receiving input signals from some of said output
lines and supplying output signals to some of said input lines.
29. A field programmable logic device comprising a plurality of logic
units, each logic unit connected to:
a plurality of output lines extending from said logic unit comprising at
least a first output line and a second output line, said first output line
being shorter than said second output line;
a plurality of input lines extending into said logic unit, each input line
connected to said logic unit so as to provide an input signal to said
logic unit; and
a plurality of programmable interconnection points (PIPs), each PIP being
programmable to connect one of said output lines to one of said input
lines;
in which PIPs are placed on an output line such that the number of PIPs in
one tile portion of an output line decreases as distance from said logic
unit increases. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to field programmable gate arrays. More particularly,
the invention relates to an interconnect architecture for a field
programmable gate array.
2. Description of the Prior Art
A conventional field programmable gate array ("FPGA") is a programmable
logic device that consists of a matrix of configurable logic elements
("CLEs") embedded in a configurable interconnect mesh. The configuration
control of the CLE functions and routing network define the function of
the device. The device is referred to as a "field programmable" device
because the array of CLEs contained in the device can be configured and
interconnected by the user in the user's facility by means of special
hardware and software.
FPGAs are well known in the art. For example, R. Freeman, Configurable
Electrical Circuit Having Configurable Logic Elements and Configurable
Interconnects, U.S. Pat. No. 4,870,302, issued 26 Sep. 1989 describes a
configurable logic array that includes a plurality of CLEs variably
interconnected in response to control signals to perform a selected logic
function, and in which a memory is used to store the particular data used
to configure the CLEs. W. Carter, Special Interconnect For Configurable
Logic Array, U.S. Pat. No. 4,642,487, issued 10 Feb. 1987 describes a
special interconnect circuit for interconnecting CLEs in an FPGA without
using the general interconnect structure of the FPGA. W. Carter,
Configurable Logic Element, U.S. Pat. No. 4,706,216, issued 10 Nov. 1987
describes a CLE that includes a configurable combinational logic element,
a configurable storage circuit, and a configurable output select logic
circuit.
A CLE may be electrically programmed by control bits to provide any one of
a plurality of logic functions. A CLE may include the circuit elements
necessary to provide an AND gate, flip flop, latch, inverter, NOR gate,
exclusive OR gate, and certain combinations of these functions, or a CLE
may include a look-up table that offers a user all functions of several
input signals. The particular function performed by the CLE is determined
by control signals that are applied to the CLE from a control logic
circuit.
In a field programmable device, the CLE is configured to implement a
selected one of its functions without any change in physical structure. In
general, a specific set of control signals is transmitted to a specific
CLE to control the configuration of that CLE or a set of values is loaded
into a look-up table to provide the truth table of the desired function.
Control signals are applied to every CLE in the device. The values of the
control bits provided to a CLE depend upon the function the CLE is to
perform. The configuration of each CLE is therefore determined by the
user's intended function of the integrated circuit.
A conventional FPGA comprises a plurality of CLEs, each CLE having input
leads and one or more output leads, a general interconnect structure, and
a set of programmable interconnection points (PIPs) for connecting the
general interconnect structure to each input lead and each output lead.
Also, each lead in the general interconnect structure can be connected to
one or more other interconnect leads by programming an associated PIP.
The various PIPs in an FPGA are typically programmed by loading memory
cells which control the gates of pass transistors or by connecting
selected antifuses in an antifuse FPGA. A specific FPGA configuration
having a desired function is created by configuring each CLE and forming
paths through the interconnect structure within the FPGA to connect the
CLEs.
Each PIP in an FPGA is programmed by opening or closing one or more
switches associated with the PIP, such that a specified signal path is
defined. Such switches may be implemented by applying a control signal to
the gate of a pass transistor. Alternatively, if the PIP is part of a
multiplexer in which only one of several PIPs will be turned on at one
time, several control signals may be decoded to determine which PIP is
turned on.
One problem with the known approach to routing signals through an FPGA
interconnect structure is caused by using many pass transistors to form a
path. Each transistor has an impedance. As a result, several pass
transistors connected in series can introduce a significant impedance into
a path. Additionally, each interconnect lead and pass transistor
introduces a capacitive element that combines with the impedance to
produce a propagation delay over the associated path. Delay is especially
pronounced if a long path is required because the path may be implemented
through several shorter segments and several pass transistors. There is a
need for an architecture which avoids the delay of longer paths and offers
resource-efficient short paths.
In addition to avoiding long delays, it is desirable to offer predictable
delay. The signal path chosen to interconnect one logic element to another
logic element is governed by algorithms implemented in software routines.
The user may exercise some control over the signal paths chosen by the
software, but it is not practical for the user to control all signal paths
in a design. The software may choose a large number of different
interconnect segment and switch combinations to realize a particular
signal path. Since the number of interconnect segments and pass
transistors will vary from combination to combination, the delay through
the signal path may also vary significantly, depending on the choice made
by the software. This variation in delay is undesirable. It would be
further advantageous to provide an FPGA interconnect structure that did
not have significant delay differences depending upon the signal path
realized by the software.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a repeatable structure is
provided which includes a logic unit capable of receiving input signals
from a plurality of input lines and providing a plurality of output
signals on a corresponding plurality of output lines, the output lines of
one logic unit being of more than one length. The output lines of one
logic unit extend past other logic units. Provided periodically along each
output line is a plurality of interconnection points (PIPs). The PIPs
allow the output lines to be connected to input lines of other logic
units. This combination of output lines of differing lengths and PIPs
allows a user to connect logic units either to nearby logic units or to
logic units some distance away.
According to another aspect of the invention, the number of PIPs which may
be driven by one output line is approximately the same as the number of
PIPs which may be driven by each other output line. Most PIPs are
buffered, that is, they comprise a buffer followed by a connector such as
a transistor. Providing an approximately equal number of buffered PIPs on
each output line produces the benefit that signals which propagate a short
distance on an output line have approximately the same delay as signals
which propagate a longer distance on a longer output line.
According to yet another aspect of the invention, the frequency of PIPs
decreases as distance from the originating logic unit increases. This has
the benefit of cooperating with software which tends to place
interconnected logic in close proximity.
As another feature, the architecture can connect selected output lines to
other output lines so that a signal path can be extended. This feature
eliminates the necessity for undedicated line segments used in
conventional FPGAs, although it also can work with an embodiment which
includes undedicated line segments.
A tile is a schematic drawing of a portion of a circuit in which elements
and lines are positioned such that an array of tiles placed side by side
shows electrical continuity across the tile boundaries between lines in
adjacent tiles. The architecture is preferably implemented using tiles,
with one logic unit in each tile, and logic unit input and output lines
extending through several tiles. One tile boundary is like another and in
one embodiment there is minimum routing hierarchy. It is not necessary
that all tiles be alike, although unlike tiles which are placed adjacent
to each other must be compatible at their boundaries.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a and 1b show tile architectures incorporating the invention.
FIG. 2 shows the meaning of symbols used in FIGS. 1a, 1b, 3-6 and 9-14.
FIG. 3 shows the structure of a multiplexer array which may be used in FIG.
1b.
FIGS. 4a and 4b illustrate one tile according to a preferred embodiment of
the invention.
FIGS. 5a and 5b illustrate portions of the tile of FIGS. 4a and 4b.
FIG. 5c is an enlarged view of the mux array of FIG. 4b.
FIGS. 5d-5g show detail of structures in FIG. 4b.
FIG. 6a illustrates the equivalent circuit formed by the illustrated lines
in FIGS. 5a and 5b when adjacent tiles are connected to form an FPGA
circuit according to the invention.
FIGS. 6b and 6c illustrate most of the equivalent circuit formed by the
structure of FIGS. 4a and 4b.
FIG. 7 is another illustration of the circuit formed by tiles of the
architecture of FIGS. 4a and 4b.
FIG. 8a illustrates one embodiment of a CLE used in conjunction with the
invention.
FIG. 8b illustrates another embodiment of a CLE which can be used with the
invention when a carry chain is not provided.
FIGS. 9a and 9b illustrate a west tile usable with the embodiment of FIGS.
4a and 4b.
FIGS. 10a and 10b illustrate a north tile usable with the embodiment of
FIGS. 4a and 4b.
FIG. 11 illustrates a west edge tile usable with the embodiment of FIGS. 4a
and 4b.
FIG. 12 illustrates a north edge tile usable with the embodiment of FIGS.
4a and 4b.
FIG. 13 illustrates an east edge tile usable with the embodiment of FIGS.
4a and 4b.
FIG. 14 illustrates a south edge tile usable with the embodiment of FIGS.
4a and 4b.
FIG. 15 illustrates the general arrangement of an FPGA which combines tiles
of the types shown in FIGS. 4a, 4b, 9a, 9b, 10a, 10b, and 11-14.
FIG. 16 illustrates one embodiment of an input/output block used in
conjunction with the invention.
FIG. 17 shows a boundary scan structure used with the input/output block of
FIG. 16.
DETAILED DESCRIPTION OF THE DRAWINGS
The present invention may be implemented by forming an array of identical
tiles adjacent to one another. The lines in a single tile are shown such
that when tiles are joined, a single CLE or logic unit and its associated
input and output lines extends over several tiles. A single tile includes
portions of many input and output lines associated with many different
logic units. A single input or output line is made of segments, each of
which is implemented in a different tile. Here the term "segment" will be
used to refer to that portion of a line which is implemented in a tile,
and the term "line" will refer to an entire electrically continuous
conductor.
FIG. 1a shows a simple embodiment which incorporates features of the
invention. In FIG. 1a, twelve identical tiles T11 through T14, T21 through
T24, and T31 through T34 which are part of a larger FPGA are shown. Each
tile includes a logic unit, which typically performs a combination of
logic and routing functions. Thus, tiles T11 through T34 include
corresponding logic units L11 through L34. Each logic unit receives input
signals on five logic unit input lines I1 through I5 and drives five logic
unit output lines O1 through O5. Logic unit output lines O1 through O3 are
direct connections to adjacent CLEs and therefore serve as input lines I1
through I3 in adjacent tiles. For example output line O1 in tile T22 is
also logic unit input line I1 in tile T11, output line O2 in tile T22 is
input line I2 in tile T12, and output line O3 in tile T22 is input line I3
in tile T21. By contrast, output lines O4 and O5 are programmably
connectable to logic unit input lines and are of different lengths from
one another. Output line O4 extends one tile to the east and output line
O5 extends three tiles to the east. Output line O4 from tile T21 extends
into tile T22 where it stops. Output line O5 from tile T21 extends into
tile T24 where it becomes input line I5 of logic unit L24 in tile T24.
Each tile includes an array of programmable interconnection points (PIPs),
each of which programmably connects two intersecting lines where the PIP
is located. In FIG. 1a, each PIP array includes four PIPs. For example,
PIP array PA11 in tile T11 includes PIPs P111, P112, P113, and P114.
Output line O4 of tile T21 is programmably connectable to input line I4 of
tile T22 through PIP P221 and to input line I4 of tile T12 through PIP
P224. Thus output line O4 accesses two PIPs. Output line O5 also accesses
two PIPs. For example, output line O5 in tile T21 accesses PIP P222 in
tile T22 (which connects to input line I4 in tile T22) and PIP P233 in
tile T23 (which connects to input line I4 in tile T13).
Thus the embodiment of FIG. 1a illustrates the logic units, the output
lines of more than one length, the input lines, and the array of PIPs
which programmably connect output lines to input lines.
PIP Array
A PIP array allows a user to choose whether to connect one line to another
line. Each PIP has a programmable element that may be programmed by a user
to open or close a switch. Thus the PIP array allows specific output lines
to be coupled to specific input lines by the appropriate programming of
the switches. In FIG. 1a, each PIP is represented by a triangle having its
apex pointing upward or north. The top row of FIG. 2 shows some of the
possible circuits which may implement this north PIP.
As indicated in the top row of circuits in FIG. 2, either a north PIP N or
a south PIP S is implemented by a buffering device which receives input
from a horizontal line H and is followed by a programmable connecting
device N2 programmed by the output signal from a memory cell M. The
connecting device (for example a pass transistor, transmission gate, or
antifuse) receives an input signal from the buffering device. If the
memory cell has been loaded with the proper value, the connecting device
provides the buffered signal to the vertical line V.
Using a buffering device in conjunction with a switch causes the PIP to be
directional. Of course, once a signal is placed onto a conductive line,
the voltage which represents that signal is the same on the full length of
the conductive line, thus the line itself is not directional. Therefore a
south PIP has the same meaning as a north PIP.
Circuit 31 illustrates an inverter I31 as the buffering device and an
N-channel pass transistor N2 as the connecting device. Inverting buffer
I31 has an input terminal connected to horizontal line H and generates an
inverted and buffered version of the signal on line H. If memory cell M
has been loaded with a logic 1, transistor N2 provides the output signal
from inverting buffer I31 to vertical line V. Circuit 32 illustrates a
noninverting buffer as the buffering device with an N-channel pass
transistor as the connecting device, and circuit 33 illustrates an XOR
gate as the buffering device, which in response to a second memory cell M2
either inverts or does not invert the input signal. The connecting device
is again a pass transistor. Depending upon the structure of the logic
unit, other logic gates such as a NAND gate or an AND gate can serve as
buffering devices. A second memory cell M2 or an internally generated
control signal enables the gate to respond to the input signal. If circuit
31 is used to provide an inverted buffered signal, the polarity of the
signal must be inverted in its destination CLE if the number of buffered
PIPs is odd. Since an inverter I31 such as shown in circuit 31 is fast,
small and efficient, it may be preferred to use this inverted
implementation of a buffered PIP. FIG. 2 is further discussed in
connection with FIGS. 4a and 4b.
Multiplexer Embodiment, FIG. 1b
In one embodiment of the invention, each logic unit comprises a
configurable logic element (CLE) and a multiplexer array or mux array. For
example, in FIG. 1b logic units L11-L34 each comprise a respective one of
CLEs C11 through C34 and mux arrays MA11 through MA34. The same reference
numerals have the same meanings in both FIGS. 1a and 1b. Input lines,
output lines, and PIP arrays are the same as in FIG. 1a, and are thus not
described again. Within a logic unit, note that input lines I1 through I3
are applied to the corresponding mux array MA while output lines O1
through O3 are taken from the corresponding CLE. In addition, an output
line O6 from the CLE connects to input line I6 in the mux array.
In the embodiment of FIGS. 1a and 1b, all tiles have the same architecture.
In still other embodiments, adjacent tiles have different architectures.
Tiles at the edges and corners of the FPGA chip typically have different
architectures from those in the center of the array, as will be discussed
below.
Multiplexer Array
FIG. 3 illustrates one mux array which works with the embodiment of FIG.
1b. Mux array MA21 includes two multiplexers MUX1 and MUX2, each of which
receives five input signals from five input lines I1, I2, I3, I5, and I6
and provides a selected one of the five input signals as its output
signal. Memory cells M1-M6 allow each of multiplexers MUX1 and MUX2 to be
separately programmable to select one of the five input signals to place
onto its respective output line. Multiplexer MUX1 provides an output
signal on output line O4 and multiplexer MUX2 provides an output signal on
output line O5. Output lines O4 and O5 couple the multiplexer output
signals to PIPs located one or more tiles away, as shown in FIG. 1b.
Whereas the mux array of FIG. 3 is an encoded structure in which three
control signals, for example M1, M2, and M3 cause the multiplexer, for
example MUX2, to select one of five input signals to place onto its output
line, another structure can be provided in which a separate memory cell
controls each line. In such an embodiment, software which generates the
values which are to be placed into each memory cell assures that only one
of the five memory cells causes its input line to be connected to the
output line.
Referring back to FIG. 1b, output line O5 is formed in four segments in
four adjacent tiles. For example, output line O5 from mux array MA21
occupies segment O5-0 in tile T21, segment O5-1 in tile T22, segment O5-2
in tile T23, and segment O5-3 in tile 24, which is applied to mux array
MA24 as input line I5.
As described with reference to FIG. 3, input line I5 provides input signals
to both of multiplexers MUX1 and MUX2. Multiplexers MUX1 and MUX2 also
both receive input signals on lines I1 through I3 and I6 from four
adjacent CLEs. In tile T22 of FIG. 1b, for example, mux array MA22
receives input signals from CLEs C22, C23, C32, and C33. Thus, although
mux array MA22 is illustrated as being associated with CLE C22 in logic
unit L22, in fact mux array MA22 is just as closely associated with three
other nearby CLEs.
A mux array may connect an output signal from any of four neighboring CLEs
or from another mux array to an output line of a selected length.
Providing a choice of output lines having different lengths (two in this
case) offers a user the option of providing an output signal to the next
adjacent tile or to tiles further away.
Output Lines
There are a number of important features associated with the output lines.
1. Different Lengths. First, different output lines originating from a
given mux array have different lengths. For example, in FIG. 1b, output
line O4 from tile T21 extends one tile east, whereas output line O5
extends three tiles east. Note that the offset feature illustrated in each
of the tiles, by which a horizontal line is offset lower before reaching a
tile boundary, allows a single continuous line to extend through several
tiles and at the same time allows adjacent tiles to be identical. The
offset illustrates the connectivity which results when tiles are joined
but this offset may not be present in an actual layout of such a structure
on silicon.
2. Output lines drive approximately equal loads. Second, the different
output signals originating from different multiplexers in a mux array are
each applied to approximately the same number of PIPs, or the PIPs are
sized such that each output line drives approximately the same capacitive
load. For example, in FIG. 1b, the signal on output line O4 from mux array
MA21 is applied to two PIPs in tile T22, and output signal O5 is applied
to one PIP in tile T22 and one PIP in tile T23. As is well known in the
art, propagation delay is caused by capacitive load and resistance
associated with the output lines. Most of the capacitive and resistive
loading experienced by the output lines comes not from metal lines but
from circuits which tap off the metal lines. Since all PIPs in FIG. 1b are
buffered, as shown in FIG. 2, the capacitive loading experienced by a
metal output line (for example O5) driving two PIPs (PIPs P222 and P233)
includes the gate regions of transistors in the PIP buffers (for example
gates of transistors P1 and N1 in inverting buffer I31 of FIG. 2). But the
capacitive loading experienced by this output line does not include the
source, drain, and channel regions of the transistors in the buffers (for
example, source, drain, and channel of transistors P1 and N1 of FIG. 2) or
the source, drain, and channel regions of transistors driven by the
buffers (for example transistor N2 in FIG. 2 and any transistors on
vertical line V), because these buffer gate regions (i.e. gates of P1 and
N1 in FIG. 2) are isolated from the structures driven by the buffers.
Capacitive loading experienced by an output line is independent of whether
the pass transistor (for example N2 in FIG. 2) in the PIP is turned on.
Thus, the capacitive loadings of output lines O4 and O5 of FIG. 1b are
predictable and approximately the same even though (a) their lengths are
different, and (b) the circuit designer does not know which PIPs a user
will turn on. Thus, output signals from a given mux array arrive at a
variety of PIPs at approximately the same time.
Each buffered PIP drives approximately the same load. Several PIPs can
drive the same input line. However, no more than one PIP will be turned on
at one time to connect its respective output line to the same input line.
Thus, the capacitance of an input line includes the source/drain diffusion
regions of the transistors such as N2 of FIG. 2 not turned on, the
conductive path (source, drain, and channel) of the transistor N2 which is
turned on, and the conductive path of the buffer transistor N1 or P1 which
drives the load. Since the capacitance and resistance of the input line is
approximately the same regardless of which PIP is driving the input line,
the delay contributed by the input line is predictable. For example, the
delay in propagating a signal from mux array MA21 to CLE C22 is
approximately the same as the delay in propagating a signal from mux array
MA21 to CLE C13. This near constant delay helps to make timing of user
designs implemented in an FPGA using the present invention predictable.
3. PIPS Decrease with Distance. A third feature associated with the output
lines is that the number of PIPs accessed by a mux array output line
decreases as the distance from the mux array increases. For example, in
FIG. 1b, considering output lines O4 and O5 of mux array MA21, the number
of PIPs accessed in tile T22 is three, the number of PIPs accessed in tile
T23 is one, and the number of PIPs accessed in tile T24 is zero.
Some placement algorithms ensure that CLEs having a high number of
electrical connections to other CLEs are placed close to each other.
Therefore, the logic implemented in tile T21 is likely to require more
electrical connections to the logic in tile T22 than to the logic in tile
T23 and even less in tile T24. Because the number of PIPs connected to
output lines in a given column of tiles determines the number of possible
electrical connections to those tiles, the structure of FIG. 1b offers a
statistical match between the distribution of PIPs and the need of a user
to make particular connections. Specifically, the distribution of PIPs
according to the present invention improves connection options while
minimizing the total number of PIPs. Minimizing PIPs decreases
capacitance, thereby increasing speed of the signal path, and also
minimizing chip area, thereby decreasing chip cost.
4. Extensions. A fourth feature associated with the output lines is that at
least one output signal from a mux array is provided to another mux array,
thereby allowing the signal to be propagated farther with minimum delay.
For example, output line O5 of tile T21 is input line I5 of mux array
MA24. This signal may then be coupled to output line O5 in mux array MA24,
thereby allowing the signal to be propagated farther eastward. The number
of PIPs in a signal path increases by two each time the signal path passes
through a mux array.
5. Several CLE Connections. Preferably, several direct connections from one
CLE (FIG. 1b) to a nearby mux array or from one logic unit (FIG. 1a) to a
nearby logic unit offer high speed and flexible connectivity for commonly
used connections. Output lines O1, O2, and O3 offer connections to nearby
CLEs or logic units in the northwest, north, and west directions,
respectively.
Input Lines
An input line carries a signal from a selected one of a plurality of PIPs
to a logic unit or CLE input port. In FIG. 1b, input lines I4 connect one
of four PIPs to a respective CLE input port. (In FIG. 1b only one input
line I4 to a CLE is shown, although in an actual CLE, input signals will
be available from several input lines, as will be discussed in connection
with the preferred embodiment.) For example, regarding CLE C24, if PIP
P241 in tile T24 is connected, input line I4 to CLE C24 is driven by a
signal on output line O4 from tile T23. If PIP P242 is connected, input
line I4 is driven by a signal on output line O5 from tile T23. If PIP P243
is connected, input line I4 is driven by a signal on output line O5 of
tile T22. The fourth PIP which drives input line I4 in CLE C24 is in tile
T34. If PIP P344 in tile T34 is connected, input line I4 to CLE C24 is
driven by a signal on output line O4 in tile T33.
Preferred Embodiment
FIGS. 4a through 16 illustrate several views of a preferred embodiment of
the invention.
FIGS. 4a and 4b together show one complete tile according to a preferred
embodiment. FIGS. 5a and 5b show this same tile with lines removed in
order to simplify the discussion. FIG. 6a shows one of the structures
which results when an array of tiles shown in FIGS. 5a and 5b is
connected. FIGS. 6b and 6c show most lines in the structure which results
when an array of tiles shown in FIGS. 4a and 4b is connected. FIG. 7 shows
another representation o | | |
