Source-level run-time software code debugging instrument

Claims

We claim:

1. A target access probe ("TAP") for connecting to a target circuit that includes a target CPU communicating with a target program memory having memory sites that store main program instructions for exercising of target circuit components, the target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the TAP testing and verifying the operational performance of software, in the target circuit in response to host command signals provided by a host computer in the electrical absence of the target CPU and comprising:

a connector for electrically and mechanically connecting the TAP to the target circuit at the target CPU position, the connector being fixedly mounted on the TAP and being adapted for attachment directly to the target circuit so that the TAP is physically supported by the target circuit;

a TAP CPU receiving target CPU input signals at the input terminal positions and delivering target CPU output signals at the output terminal positions;

in-circuit emulation ("ICE") circuitry including ICE program memory sites that store ICE program instructions, the ICE circuity communicating with the TAP CPU for producing the target CPU output signals in accordance with the ICE program instructions executed by the TAP CPU in response to the host command signals; and

an input and output signal link for providing a signal link to and from the host computer and for the target CPU input and output signals, the ICE program memory sites residing wholly outside of the target circuit and the target circuit address space, and the delivery of the target CPU input signals to the corresponding target CPU input terminal positions and the delivery of the target CPU output signals to the corresponding target CPU output positions in response to the host command signals providing a capability for testing and verifying the performance of the target circuit in accordance with the ICE program instructions independently of the target program stored therein.

2. The TAP of claim 10 wherein the TAP further includes a rigid substrate, and wherein the connector, the TAP CPU, and the in-circuit emulation circuitry are physically mounted on the substrate so that the TAP is physically supported on the target circuit by the connector.

3. The TAP of claim 1 wherein the TAP CPU includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP CPU is accessible externally of the TAP CPU and coupled to other circuitry on the TAP.

4. The TAP of claim 1 wherein the TAP CPU further performs the function of communicating directly with the host computer to receive the host command signals from the host computer.

5. The TAP of claim 1 wherein the ICE circuitry includes a memory containing at least one ICE program memory site.

6. The TAP of claim 1 wherein the ICE circuitry includes a random access memory containing the ICE program memory sites, and wherein the TAP CPU fetches the ICE program instructions directly from the random access memory.

7. The TAP of claim 1 wherein the TAP CPU is adapted to communicate with both the host computer and the target CPU.

8. The TAP of claim 1 wherein the ICE circuitry includes a memory into which the ICE program instructions are loaded upon initialization of the TAP.

9. The TAP of claim 8 wherein all of the ICE program instructions are loaded upon initialization of the TAP.

10. The TAP of claim 8 wherein multiple ICE program instructions are loaded upon initialization of the TAP.

11. The TAP of claim 8 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP.

12. An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

a target access probe ("TAP") including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source, the TAP including a connector for electrically connecting the TAP CPU to the target computer system at the target CPU position, the TAP further including a memory storing an in-circuit emulation ("ICE") program containing instructions for the TAP CPU in accordance with the command signals from the host analysis code source, the ICE program residing wholly within the memory and outside both the target computer system and the target computer address space during execution of the ICE program by the TAP CPU, the TAP further including a TAP signal routing integrated circuit for assembling the host command signals into a digital word format and routing the assembled command signals to the TAP CPU;

a communications adapter that provides an interface between the host analysis code source and the TAP; and

a data communication link for providing a data communication link between the TAP and the communications adapter.

13. The instrument of claim 12 wherein the connector is fixedly mounted on the TAP and is adapted to plug directly into the target computer system at the target CPU position so that the TAP is physically supported by the target computer system.

14. The instrument of claim 12 wherein the TAP CPU includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP CPU is accessible externally of the TAP CPU and coupled to other circuitry on the TAP.

15. The instrument of claim 12 wherein the communications adapter is physically separate from the host analysis code source.

16. The instrument of claim 12 wherein the TAP CPU further performs the function of communicating directly with the communications adapter to receive the command signals from the host analysis code source.

17. The instrument of claim 12 wherein the TAP CPU fetches the instructions of the ICE program directly from the memory.

18. The instrument of claim 12 wherein the TAP CPU is adapted to communicate with both the host analysis code source and the target CPU.

19. The instrument of claim 12 wherein the instructions of the ICE program are loaded into the memory upon initialization of the TAP CPU.

20. The instrument of claim 19 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP CPU.

21. The instrument of claim 19 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP CPU.

22. A target access probe ("TAP") for verifying and controlling the operational performance of software in a target system having a microprocessor position in accordance with instructions from a host analysis code source, comprising:

a first connector for electrically and mechanically connecting the TAP to the target system at the target microprocessor position, the first connector being fixedly mounted on the TAP and being adapted for attachment directly to the target system so that the TAP is physically supported by the target system;

a TAP microprocessor adapted to receive and transmit signals to and from the target system through the first connector;

emulation circuitry adapted to store an in-circuit emulation ("ICE") program and provide instructions to the TAP microprocessor in accordance with instructions from the host analysis code source, the ICE program being stored entirely in the emulation circuitry on the TAP during execution of the ICE program by the TAP microprocessor so that the TAP microprocessor need not fetch instructions from the target system, the target system address space, or the host analysis source code during execution of the ICE program; and

a second connector for linking the TAP with the host analysis code source.

23. The TAP of claim 22 in which the ICE program is loaded into the emulation circuitry when power is applied to the TAP.

24. The TAP of claim 23 in which the ICE program is loaded into the emulation circuitry from outside of the TAP.

25. The TAP of claim 22 in which emulation circuitry comprises a random access memory.

26. The TAP of claim 22 wherein the TAP microprocessor includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP microprocessor is accessible externally of the TAP microprocessor and coupled to other circuitry on the TAP.

27. The TAP of claim 22 wherein the TAP microprocessor further performs the function of communicating directly with the host analysis code source to receive the instructions from the host analysis code source.

28. The TAP of claim 22 wherein emulation circuitry includes a random access memory containing the ICE program, and wherein the TAP CPU fetches the instructions of the ICE program directly from the random access memory.

29. The TAP of claim 22 wherein the TAP CPU is adapted to communicate with both the host computer and the target CPU.

30. The TAP of claim 22 wherein the emulation circuitry includes a memory into which instructions of the ICE program are loaded upon initialization of the TAP.

31. The TAP of claim 30 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP.

32. The TAP of claim 22 further comprising a signal routing integrated circuit for configuring electrical signals for transmission between the TAP and the host analysis code source.

33. The TAP of claim 32 in which the signal routing integrated circuit is of a programmable type.

34. The TAP of claim 32 in which instructions for programming the signal routing integrated circuit and the ICE program are loaded into the signal routing integrated circuit and the emulation circuitry, respectively, from outside the TAP upon application of power to the TAP.

35. The TAP of claim 32 in which the signal routing integrated circuit is of a reprogrammable type.

36. The TAP of claim 35 in which the signal routing integrated circuit is programmed by instructions received after application of power to the TAP.

37. The TAP of claim 36 in which the signal routing integrated circuit is programmed by instrructions received from outside of the TAP.

38. The TAP of claim 35 in which the TAP microprocessor includes a program counter and in which upon application of power to the TAP the signal routing integrated circuit is programmed, the ICE program is loaded into the emulation circuitry, and the program counter is set to a restart vector.

39. The TAP of claim 34 in which the TAP microprocessor includes BREAK and RESET conductors having logic states and in which the BREAK and RESET conductors are set to logic states of reset the program counter to a restart vector.

40. The TAP of claim 39 in which the TAP microprocessor includes CPU registers and in which the RESET conductor and BREAK conductor are set to logic states to dump the contents of the CPU register and the BREAK conductor is then set to a logic state to run the ICE program in the emulation circuitry.

41. An instrument for testing and verifying the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

a target access probe ("TAP") including a connector for electrically and mechanically connecting the TAP to the target system at the target CPU position, the connector being fixedly mounted on the TAP and being adapted for attachment directly to the target computer system so that the TAP is physically supported by the target computer system; a TAP microprocessor adapted to receive and transmit signals to and from the target computer system; emulation circuitry adapted to store an in-circuit emulation ("ICE") program that resides wholly within the emulation circuitry and outside of the target computer system and target computer system address space during execution of the ICE program to provide instructions to the TAP microprocessor so that tile TAP itself can function as an emulator in accordance with instructions from a host analysis code source; the microprocessor and emulation circuitry being mounted in a common chassis; and

a communications adapter operatively connected to and cooperating with the TAP to provide an interface between the host analysis code source and the TAP to route signals between the TAP and the host analysis code source.

42. The instrument of claim 41 in which the communications adapter includes a memory storing the ICE program and in which the ICE program is loaded into the emulation circuitry upon application of power to the instrument.

43. The instrument of claim 41 in which the TAP further includes a signal routing integrated circuit for configuring signal paths within the TAP and the communications adapter includes a memory storing information for configuring the signal routing integrated circuit.

44. The instrument of claim 41 in which the communications adapter is physically separate from the host analysis code source.

45. The instrument of claim 41 in which the communications adapter is physically separate from the TAP.

46. The instrument of claim 41 wherein the connector is fixedly mounted on the chassis and is adapted to plug directly into the target system at the target CPU position so that the TAP chassis is physically supported by the target system.

47. The instrument of claim 41 wherein the TAP microprocessor includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the TAP microprocessor is accessible externally of the TAP microprocessor and coupled to other circuitry on the TAP.

48. The instrument of claim 41 wherein the communications adapter is physically separate from the host analysis code source.

49. The instrument of claim 41 wherein the TAP microprocessor further performs the function of communicating directly with the communications adapter to receive the instructions from the host analysis code source.

50. The instrument of claim 41 wherein the TAP CPU fetches the instructions of the ICE program directly from the emulation circuitry.

51. The instrument of claim 41 wherein the TAP CPU is adapted to communicate with both the host analysis code source and the target CPU.

52. The instrument of claim 41 wherein the instructions of the ICE program are loaded into the emulation circuitry upon initialization of the TAP CPU.

53. The instrument of claim 52 wherein all of the instructions of the ICE program are loaded upon initialization of the TAP CPU.

54. The instrument of claim 52 wherein multiple instructions of the ICE program are loaded upon initialization of the TAP CPU.

55. The instrument of claim 41 in which the tap further includes a reprogrammable signal routing integrated circuit for configuring electrical signals for transmission between the TAP and the host analysis code source communications adapter by way of the communications adapter and in which the communications adapter includes a memory storing configuration information that is loaded into the logic cell array upon application of power to the instrument.

56. A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising:

applying electrical power to the TAP;

configuring the TAP signal routing integrated circuit by applying signals through the signal link to the signal routing integrated circuit;

loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit after the signal routing integrated circuit has been configured; and

the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.

57. The method of claim 56 in which the TAP microprocessor includes a program counter and registers and further comprising:

setting program counter to a reset vector;

writing the contents of CPU registers to another memory; and

running an ICE program.

58. The method of claim 56 in which the TAP communicates with the host analysis source code through a communications adapter and in which downloading the ICE program includes transferring the ICE program from the communications adapter to the ICE circuitry through the TAP signal routing integrated circuit.

59. The method of claim 56 further including the step of maintaining the TAP microprocessor, in a reset condition while the ICE program is being loaded into the ICE circuitry through the signal link and the signal routing integrated circuit.

60. The method of claim 56 wherein multiple instruction bytes of the ICE program are downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the TAP microprocessor.

61. The method of claim 56 wherein the entire ICE program is loaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the TAP microprocessor.

62. The method of claim 56 in which the TAP communicates with the host analysis source code through a communications adapter and in which configuring the TAP signal routing integrated circuit and loading an ICE program include transferring data to the TAP from the communications adapter.

63. The method of claim 62 in which the communications adapter includes a communications adapter signal routing integrated circuit and in which configuring the TAP signal routing integrated circuit and loading an ICE program include transferring data through the communications adapter signal routing integrated circuit.

64. The method of claim 63 in which the communications adapter signal routing integrated circuit is of a reprogrammable type and in which transferring data through the communications adapter signal routing integrated circuit includes configuring the communications adapter signal routing integrated circuit.

65. The method of claim 64 in which the communications adapter includes memory sites and in which data for configuring the communications adapter signal routing integrated circuit are stored in the communications adapter memory sites.

66. The method of claim 62 in which the communications adapter includes memory sites and in which the ICE program is stored in the communications adapter memory sites.

67. The method of claim 62 in which the communications adapter includes memory sites in which data for configuring the TAP signal routing integrated circuit is stored in the communications adapter memory sites.

68. An instrument for verifying and controlling the operational performance of software in a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective target CPU input and output signals appear, the instrument comprising:

a user interface device generating command signals corresponding to manually selected user inputs;

a target access probe including a probe CPU of the same type as the target CPU and an in-circuit emulation memory storing an in-circuit emulation program that resides wholly within the in-circuit emulation memory and outside of the target computer system and the target computer system address space during execution of the in-circuit emulation program by the probe CPU so that the probe CPU need not fetch instructions from the target system or the user interface device during execution of the in-circuit emulation program, thereby allowing the target access probe itself to a function as an emulator, the in-circuit emulation memory providing instructions to the probe CPU in accordance with the command signals from the user interface device;

a signal link connecting the target access probe to the user interface device to allow the target access probe to receive the command signals from the user interface device; and

a connector electrically and mechanically connecting terminals of the target access probe to corresponding input and output terminal positions of the target CPU, the connector being fixedly mounted on the target access probe and being adapted for attachment directly to the target computer system so that the target access probe is physically supported by the target computer system.

69. The instrument of claim 68 wherein the target access probe further includes a programmable signal routing circuit that, after being programmed by the user interface device, routes the in-circuit emulation program from the user interface device and downloads the in-circuit emulation program into the in-circuit emulation memory prior to execution by the probe CPU.

70. The instrument of claim 68 wherein the signal link connecting the target access probe to the user interface includes a communications adapter to provide an interface between the user interface device and the target access probe.

71. The instrument of claim 70 wherein the communications adapter is physically separate from the user interface device.

72. The instrument of claim 70 wherein the probe CPU further performs the function of communicating directly with the communications adapter to receive the in-circuit emulation program from the user interface device.

73. The instrument of claim 68 wherein the connector is fixedly mounted on the target access probe and is adapted to plug directly into the target computer system at the target CPU position so that the target access probe is physically supported by the target computer system.

74. The instrument of claim 68 wherein the probe CPU includes emulation specific circuitry specially adapted to perform emulation functions, and wherein the emulation specific circuitry of the probe CPU is accessible externally of the probe CPU and coupled to other circuitry on the target access probe.

75. The instrument of claim 68 wherein the instructions of the in-circuit emulation program are loaded into the in-circuit emulation memory upon initialization of the probe CPU.

76. The instrument of claim 75 wherein all of the instructions of the in-circuit emulation program are loaded into the in-circuit emulation memory upon initialization of the probe CPU.

77. The instrument of claim 75 wherein multiple instructions of the in-circuit emulation program are loaded into the in-circuit emulation memory upon initialization of the probe CPU.

78. The instrument of claim 68 wherein the probe CPU fetches instructions of the in-circuit emulation program directly from the in-circuit emulation memory.

79. The instrument of claim 68 wherein the probe CPU is adapted to communicate with both the user interface device and the target CPU.

80. A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising:

applying electrical power to the TAP;

configuring the TAP signal routing integrated circuit;

loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit; and

the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.

81. The method of claim 80 further including the step of holding the TAP microprocessor in a reset condition while the ICE program is being loaded into the ICE circuitry.

82. The method of claim 80 in which the TAP communicates with a host analysis source code through a communications adapter and in which downloading the ICE program includes transferring the ICE program from the communications adapter to the ICE circuitry through the TAP signal routing integrated circuit.

83. The method of claim 80 wherein multiple instructions of the ICE program are downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the microprocessor of the target system.

84. The method of claim 80 wherein the entire ICE program is downloaded into the ICE circuitry upon configuring the TAP prior to execution of the ICE program by the microprocessor of the target system.

85. A method of configuring a target access probe ("TAP") connected to a microprocessor position of a target system and including a TAP microprocessor, in-circuit emulation ("ICE") circuitry, a TAP signal routing integrated circuit, and a signal link connecting the TAP to a host system, the method comprising:

applying electrical power to the TAP;

configuring the TAP signal routing integrated circuit by applying signals to the signal routing integrated circuit;

loading an ICE program into the ICE circuitry by downloading the program through the signal link and the signal routing integrated circuit; and

the ICE program being stored entirely in the ICE circuitry on the TAP during execution of the ICE program by the TAP microprocessor allowing the TAP microprocessor to execute the ICE program from the ICE circuitry.

86. The method of claim 85 in which the TAP communicates with a host analysis source code through a communications