 |
Claims  |
|
|
What is claimed is:
1. A data processing system, comprising:
a plurality of subsystems; and
an extension bus provided in common to and connected to the subsystems;
each subsystem includes:
(a) a local bus,
(b) one or more devices connected to the local bus among a plurality of
instruction processors to be included in the system and one connected to
the local bus among a plurality of main memory devices which form a main
memory of the system,
(c) each of the main memory devices being assigned with a corresponding one
of plural partial address spaces within a system address space assigned to
the main memory of the system, and
(d) a bus extender connected to the local bus and the extension bus for
transfer of requests therebetween, said bus extender includes:
an address check circuit responsive to a first memory access request
provided on the local bus from one of the one or more devices, checking
whether a first memory address included in the first memory access request
is assigned to one of the main memory devices included in another of the
subsystems, and responsive to a second memory access request provided on
the extension bus from the bus extender included in another of the
subsystems, checking whether a second memory address included in the
second memory access request is assigned to the each subsystem, and
a transfer control connected to the address check circuit, controlling
transfer of the first memory access request to the extension bus and
transfer of the second memory access to the local bus, in response to two
kinds of results of the checking for the first and second memory
addresses, respectively;
wherein the address check circuit of the bus extender in each subsystem
includes:
a first address check circuit connected to the local bus in the each
subsystem, checking whether another of the subsystems includes one of the
main memory devices which is assigned with a partial address space which
includes the first memory address provided on the local bus, and
a second address check circuit connected to the extension bus, checking
whether the each subsystem includes one of the main memory devices which
is assigned with a partial address space which includes the second memory
address provided on the extension bus;
wherein the first address check circuit of the bus extender of each
subsystem includes:
means responsive to the first memory address provided on the local bus of
the each subsystem, for determining a first one of the subsystems which
includes a first one of the main memory devices which is assigned with a
partial address space which includes the first memory address, and
means for determining whether the first subsystem coincides with the each
subsystem;
wherein the second address check circuit of the bus extender of the each
subsystem includes:
means responsive to the second memory address provided on the extension bus
for determining a second one of the subsystems which includes one of the
main memory devices which is assigned with a partial address space which
includes the second memory address, and
means for determining whether the second subsystem coincides with the each
subsystem;
wherein the determining means of each subsystem within the first address
check circuit includes:
a first table holding subsystem numbers assigned to the subsystem and
responsive to the first memory address provided on the local bus of the
each subsystem, providing one of the subsystem numbers for one of a
plurality of intra-subsystem address space limits which includes the first
memory address, and
a comparator comparing the subsystem number of the each subsystem and the
one subsystem number provided from the first table, and
the determining means of the one subsystem within the second address check
circuit includes:
a second table holding subsystem numbers assigned to the subsystem and
responsive to the second memory address provided on the extension bus of
the each subsystem, providing one of the subsystem numbers for one of the
intra-subsystems,
address space limits which includes the second memory address, and
a second comparator comparing the subsystem number of the each subsystem
and the one subsystem number provided from the table.
2. A data processing system according to claim 1, wherein the first and
second memory addresses are absolute addresses of the system address
space.
3. A data processing system according to claim 1, wherein the bus extender
of each subsystem further includes:
a register holding an intra-subsystem address space limit; and
wherein the first address check circuit of the bus extender of the each
subsystem comprises a comparator connected to the register, comparing
contents of the register and the first memory address provided on the
local bus of the each subsystem;
wherein the second address check circuit of the bus extender of the each
subsystem comprises a comparator connected to the register comparing
contents of the register and the second memory address provided on the
extension bus.
4. A data processing system according to claim 1,
wherein each of the main memory devices includes:
an access control connected to said local bus within one of the subsystem
which includes the each main memory device, responsive to a memory address
included in a memory access request provided on the local bus, controlling
whether the memory access request is to be executed to the each main
memory device.
5. A data processing system according to claim 4, wherein each main memory
device further includes:
a register holding a system address limit;
a comparator connected to the register and comparing contents of the
register with a memory address provided on the local bus within one of the
subsystems which includes the each main memory device and reporting a
result of the comparison.
6. A data processing system according to claim 1,
wherein each of the main memory devices includes:
a third address check circuit connected to the local bus included in one of
the subsystems to which the each main memory device belongs, checking
whether the each main memory device is assigned with a partial address
space which includes a memory address included in a memory access request
provided on the local bus; and
a control connected to said third address check circuit, controlling
execution of the memory access request on the local bus, depending upon
whether the result of the checking by the third address check circuit is
affirmative.
7. A data processing system according to claim 6, wherein the third address
check circuit within each main memory device includes:
a register holding an intra-subsystem address limit; and
a comparator connected to the register and comparing contents of the
register with a memory address provided on the local bus within one of the
subsystems which includes the each main memory device.
8. A data processing system according to claim 6, wherein the third address
check circuit of each main memory device includes:
means responsive to a memory address provided on the local bus of one of
the subsystems which includes the each main memory device, for determining
one of the subsystems which includes one of the main memory devices which
is assigned with a partial address space which includes the memory
address; and
means for determining whether the one subsystem coincides with the each
subsystem.
9. A data processing system according to claim 8, wherein the determining
means of the one subsystem within the third address check circuit
includes:
a table holding subsystem numbers assigned to the subsystems and
intra-subsystem address space limits for the subsystems and responsive to
the memory address provided on the local bus, providing one of the
subsystem numbers to which is assigned one of the intra-subsystem address
space limits which includes the memory address; and
a comparator comparing the subsystem number of the each subsystem and the
one subsystem number provided from the table.
10. A data processing system according to claim 1,
wherein each of the instruction processor and the input/output device
includes means for sending to the local bus included in one of the
subsystems to which the each of the instruction processor and the
input/output device belongs, a subsystem number of the one subsystem
together with a memory access request;
wherein each of the main memory devices includes means responsive to a
memory access request for readout of data and a subsystem number both
provided from the local bus connected to the each main memory device, for
transferring an access result to the local bus, the result including both
data requested by the access request and the provided subsystem number;
and
wherein the bus extender of each subsystem includes:
means connected to the extension bus and the local bus within the each
subsystem and responsive to a first subsystem number assigned to another
of the sub-systems and included in a first access result provided on the
local bus from one of the main memory devices included in the each
subsystem, for transferring the first access result to the extension bus
and responsive to a second subsystem number assigned to the each
sub-system and included in a second access result provided on the
extension bus from another of the subsystems, for transferring the second
access result to the local bus.
11. A data processing system according to claim 1
wherein each subsystem includes one of the main memory devices and one
instruction processor.
12. A data processing system according to claim 11, wherein each of the
plural ones of the subsystems further includes one input/output device.
13. A data processing system according to claim 11, wherein another
subsystem other than the plural ones of the subsystems includes one of the
memory devices but does not include either an instruction processor or an
input/output device.
14. A data processing system according to claim 1, further comprising:
an inter-subsystem transfer line connecting the subsystems, comprising a
plurality of separate lines each having connected thereto different
combinations of the subsystems;
wherein said transfer control connected to the address check circuit,
transfers the first memory access request to the another subsystem via the
inter-subsystem transfer line, and transfers to the local bus, a second
memory access request provided from another of the subsystems via the
inter-subsystem transfer line, the second memory access request including
a second memory address assigned to one of the main memory devices
included in the each subsystem.
15. A data processing system according to claim 14, wherein each of the
main memory devices including;
an access control connected to said local bus within one of the subsystems
which includes the each main memory device, responsive to a memory address
included in a memory access request provided on the local bus, controlling
whether the memory access request is to be executed to the each main
memory device.
16. A data processing system according to claim 15, wherein the access
control provided in each of the main memory devices includes:
a second address check circuit connected to the local bus included in one
of the subsystem to which the each main memory device belongs, checking
whether the each main memory device is assigned with a partial address
space which includes a memory address included in a memory access request
provided on the local bus; and
a control connected to said second address check circuit, controlling
execution of the memory access request on the local bus, depending upon
whether the result of the checking by said second address check circuit is
affirmative.
17. A data processing system according to claim 14, wherein each subsystem
includes at least one instruction processor and one of the main memory
device.
18. A data processing system, comprising:
a plurality of subsystems: and
an extension bus provided in common to and connecting the subsystems;
at least two of the subsystem includes:
(a) a local bus,
(b) an instruction processor connected to the local bus,
(c) a main memory device connected to the local bus, and
(d) a bus extender connected to the local bus and the extension bus for
transfer of requests therebetween, said bus extender includes:
a work memory holding a plurality of data each assigned to and held by
another main memory device included in another subsystem; and
a work memory control connected to the local bus and responsive to a first
memory read request provided on the local bus from the instruction
processor within each subsystem, checking whether first data of a first
memory address included in the first memory read request is held in the
work memory, and supplying the first data from the work memory to the
local bus, in case the first data is held in the work memory.
19. A data processing system according to claim 18, wherein the work memory
control includes:
an address array holding addresses for the plurality of data held in the
work memory; and
a check circuit connected to the address array, checking whether the first
data requested by the first memory read request is held in the work
memory, based upon the first memory address included in the first memory
read request and the addresses held in the address array.
20. A data processing system according to claim 18, wherein the bus
extender in the each subsystem further includes:
transfer control connected to the work memory control and the extension
bus, transferring the first memory read request to the extension bus, in
case the first data is not held in the work memory.
21. A data processing system according to claim 20, wherein the extender in
each subsystem further includes:
means connected to the extension bus and responsive to a return request
provided on the extension bus from another of the subsystems for the first
memory read request, the return data including the first data read from
another main memory device in another subsystem and the first memory
address, for storing the first data in the work memory.
22. A data processing system according to claim 21, wherein the work memory
control includes:
an address array holding addresses for the plurality of data held in the
work memory; and
a check circuit connected to the address array, checking whether the first
data requested by the first memory read request is held in the work
memory, based upon the first memory address included in the first memory
read request and the addresses held in the address array,
wherein the bus extender in the each subsystem further includes;
means responsive to the return request for storing the first memory address
included in the return request in the address array.
23. A data processing system according to claim 21, wherein the bus
extender in the each subsystem further includes:
means responsive to a second memory read request provided on the extension
bus for checking whether the second memory read request is for second data
held in the one main memory device provided in the each subsystem,
means connected to the checking means for transferring the second memory
read request to the local bus,
means connected to the local bus for transferring to the extension bus, a
return request provided from the one main memory device for the second
memory read request, the return data including the second data read from
the one main memory device and the second memory address.
24. A data processing system according to claim 18, wherein each main
memory device is assigned with a corresponding one of partial address
spaces within a system address space assigned to the main memory of
system.
25. A data processing system according to claim 22, wherein each main
memory device is assigned with a corresponding one of partial address
spaces within a system address space assigned to the main memory of
system;
wherein the bus extender of each subsystem further includes:
a check circuit connected to the extension bus responsive to the return
request provided on the extension bus for the first memory read request
for detecting whether the first memory address included in the return
request is assigned to the one main memory device included in the each
subsystem, so as to controlling the storing means of the first data into
the work memory and the storing means of the first address into the
address array.
26. A data processing system according to claim 18, wherein each of the
instruction processors including a buffer for holding data fetched from
the main memory devices.
27. A data processing system, comprising:
a plurality of subsystems; and
an extension bus provided in common to and connected to the subsystems;
each subsystem includes:
(a) a local bus,
(b) one or more devices connected to the local bus and each selected from a
group of devices to be included in the system, the group of devices
including one or plural instruction processors, one or plural input/output
devices and a plurality of main memory devices which form a main storage
of the system,
(c) each of the main memory devices being assigned with a corresponding one
of plural partial address spaces within a system address space assigned to
the main memory of the system, and
(d) a bus extender connected to the local bus and the extension bus for
transfer of requests therebetween, said bus extender includes:
an address check circuit responsive to a first memory access request
provided on the local bus from one of the one or more devices, checking
whether a first memory address included in the first memory access request
is assigned to one of the main memory devices included in another of the
subsystems, and responsive to a second memory access request provided on
the extension bus from the bus extender included in another of the
subsystems, checking whether a second memory address included in the
second memory access request is assigned to the each subsystem, and
a transfer control connected to the address check circuit, controlling
transfer of the first memory access request to the extension bus and
transfer of the second memory access to the local bus, in response to
results of the checking for the first and second memory addresses,
respectively;
wherein the address check circuit of the bus extender in each subsystem
includes:
a first address check circuit connected to the local bus in the each
subsystem, checking whether another of the subsystems includes one of the
main memory devices which is assigned with a partial address space which
includes the first memory address provided on the local bus, and
a second address check circuit connected to the extension bus, checking
whether the each subsystem includes one of the main memory devices which
is assigned with a partial address space which includes the second memory
address provided on the extension bus;
wherein the first address check circuit of the bus extender of each
subsystem includes:
means responsive to the first memory address provided on the local bus of
the each subsystem, for determining one of the subsystems which includes a
first one of the main memory devices which is assigned with a partial
address space which includes the first memory address, and
means for determining whether the first subsystem coincides with the each
subsystem;
wherein the second address check circuit of the bus extender of the each
subsystem includes:
means responsive to the second memory address provided on the extension bus
for determining a second one of the subsystems which includes one of the
main memory devices which is assigned with a partial address space which
includes the second memory address, and
means for determining whether the second subsystem coincides with the each
subsystem;
wherein the determining means of the one subsystem within the second
address check circuit includes:
a table holding subsystem numbers assigned to the subsystem and
intra-subsystem address space limits for the subsystems and responsive to
the second memory address provided on the local bus of the each subsystem,
providing one of the subsystem numbers for one of the intra-subsystem
address space limits which includes the second memory address, and
a comparator comparing the subsystem number of the each subsystem and the
one subsystem number provided from the table;
wherein the first and second memory addresses are absolute addresses of the
system address space.
28. A data processing system, comprising:
a plurality of subsystems; and
an extension bus provided in common to and connected to the subsystems;
each subsystem includes:
(a) a local bus,
(b) one or more devices connected to the local bus and each selected from a
group of devices to be included in the system, the group of devices
including one or plural instruction processors, one or plural input/output
devices and a plurality of main memory devices which form a main storage
of the system,
(c) each of the main memory devices being assigned with a corresponding one
of plural partial address spaces within a system address space assigned to
the main memory of the system, and
(d) a bus extender connected to the local bus and the extension bus for
transfer of requests therebetween, said bus extender includes:
an address check circuit responsive to a first memory access request
provided on the local bus from one of the one or more devices, checking
whether a first memory address included in the first memory access request
is assigned to one of the main memory devices included in another of the
subsystems, and responsive to a second memory access request provided on
the extension bus from the bus extender included in another of the
subsystems, checking whether a second memory address included in the
second memory access request is assigned to the each subsystem, and
a transfer control connected to the address check circuit, controlling
transfer of the first memory access request to the extension bus and
transfer of the second memory access to the local bus, in response to
results of the checking for the first and second memory addresses,
respectively;
wherein the address check circuit of the bus extender in each subsystem
includes:
a first address check circuit connected to the local bus in the each
subsystem, checking whether another of the subsystems includes one of the
main memory devices which is assigned with a partial address space which
includes the first memory address provided on the local bus, and
a second address check circuit connected to the extension bus, checking
whether the each subsystem includes one of the main memory devices which
is assigned with a partial address space which includes the second memory
address provided on the extension bus;
wherein the first address check circuit of the bus extender of each
subsystem includes:
means responsive to the first memory address provided on the local bus of
the each subsystem, for determining one of the subsystems which includes a
first one of the main memory devices which is assigned with a partial
address space which includes the first memory address, and
means for determining whether the first subsystem coincides with the each
subsystem;
wherein the second address check circuit of the bus extender of the each
subsystem includes:
means responsive to the second memory address provided on the extension bus
for determining a second one of the subsystems which includes one of the
main memory devices which is assigned with a partial address space which
includes the second memory address, and
means for determining whether the second subsystem coincides with the each
subsystem;
wherein the determining means of the one subsystem within the second
address check circuit includes:
a table holding subsystem numbers assigned to the subsystem and
intra-subsystem address space limits for the subsystems and responsive to
the second memory address provided on the local bus of the each subsystem,
providing one of the subsystem numbers for one of the intra-subsystem
address space limits which includes the second memory address, and
a comparator comparing the subsystem number of the each subsystem and the
one subsystem number provided from the table;
wherein the bus extender of each subsystem further includes:
a register holding an inter-subsystem address space limit; and
wherein the first address check circuit of the bus extender of the each
subsystem comprises a comparator connected to the register, comparing
contents of the register and the first memory address provided on the
local bus of the each subsystem;
wherein the second address check circuit of the bus extender of the each
subsystem comprises a comparator connected to the register comparing
contents of the register and the second memory address provided on the
extension bus.
29. A data processing system comprising:
a plurality of subsystems each including an instruction processor, a bus
extender and an internal bus connecting the instruction processor and the
bus extender;
an external bus connecting between bus extenders of said plurality of
subsystems; and
main memory devices which are accessed from said instruction processors;
at least one of said plurality of subsystems comprising:
(a) a buffer memory circuit provided within said instruction processor and
holding a copy of at least a part of address spaces of said main memory
devices;
(b) a buffer coherency check memory control circuit provided within said
bus extender and storing information indicating which address space in
said main memory devices content of a copy held in said buffer memory
circuit belongs to;
(c) an address determining circuit provided within said bus extender and
determining whether or not a relevant buffer memory circuit within a
subsystem to which said bus extender belongs has a copy of an address
space of a relevant main memory device which address space has been
changed, in response to receipt of information informing that the content
of said main memory device has been changed, through said external bus;
wherein when the buffer memory circuit within the subsystem to which said
bus extender belongs has the copy of address space of said changed main
memory device, a signal for one of changing and erasing the content of
buffer memory circuit is transferred to said instruction processor from
the bus extender through said internal bus.
30. A data processing system comprising:
a plurality of subsystems each including an instruction processor, a bus
extender and an internal bus connecting the instruction processor and the
bus extender;
an external bus connecting between bus extenders of said plurality of
subsystems; and
main memory devices which are accessed from said instruction processors;
at least one of said plurality of subsystems comprising:
(a) a buffer memory circuit provided within said instruction processor and
holding a copy of at least a part of an address space of said main memory
devices;
(b) a memory control circuit provided within said bus extender and storing
which of address spaces in said main memory devices the content of a copy
held in said buffer memory circuit belongs to;
(c) an address determining circuit provided within said bus extender and
determining whether or not a relevant buffer memory circuit within a
subsystem to which said relevant bus extender belongs has a copy of an
address space of a relevant main memory device which address space has
been changed, in response to receipt of information informing that the
content of said main memory device has been changed, through said internal
bus;
wherein when the buffer memory circuit within the subsystem to which the
relevant bus extender belongs has not the copy of address space of said
changed main memory device, a signal for one of changing and erasing the
content of buffer memory circuit is transferred to said instruction
processors of subsystems other than said subsystem to which said relevant
bus extender belongs, from said relevant bus extender, through said
external bus. |
|
 |
|
 |
Claims |
|
