Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor

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FIELD OF THE INVENTION

This invention relates to packaging for semiconductor devices. More specifically, the invention relates to a bondpad contact which is self-limiting in its penetration into bondpads or other contact points on a semiconductor die.

BACKGROUND OF THE INVENTION

Semiconductor devices are subjected to a series of test procedures in order to assure quality and reliability. This testing procedure conventionally includes "probe testing ", in which individual dies, while still on a wafer, are initially tested to determine functionality and speed. Probe cards are used to electrically test die at that level. The electrical connection interfaces with only a single die at a time in the wafer; not discrete die.

If the wafer has a yield of functional dies which indicates that quality of the functional dies is likely to be good, each individual die is assembled in a package to form a semiconductor device. Conventionally, the packaging includes a lead frame and a plastic or ceramic housing.

The packaged devices are then subjected to another series of tests, which include burn-in and discrete testing. Discrete testing permits the devices to be tested for speed and for errors which may occur after assembly and after burn-in. Burn-in accelerates failure mechanisms by electrically exercising the devices (DUT) at elevated temperatures, thus eliminating potential failures which would not otherwise be apparent at nominal test conditions.

Variations on these procedures permit devices assembled onto circuit arrangements, such as memory boards, to be burned-in, along with the memory board in order to assure reliability of the circuit, as populated with devices. This closed assembly testing assumes that the devices are discretely packaged in order that it can then be performed more readily.

If the wafer has a yield of grossly functional die, it indicates that a good quantity of die from the wafer are likely to be fully operative. The die are separated with a die saw, and the nonfunctional die are scrapped, while the rest are individually encapsulated in plastic packages or mounted in ceramic packages with one die in each package. After the die are packaged they are rigorously electrically tested. Components which turn out to be nonfunctional, or which operate at questionable specifications, are scrapped or devoted to special uses.

Packaging unusable die, only to scrap them after testing, is a waste of time and materials, and is therefore costly. Given the relatively low profit margins of commodity semiconductor components such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), this practice is uneconomical. However, no thorough and cost effective method of testing an unpackaged die is available which would prevent this unnecessary packaging of nonfunctional and marginally functional die. Secondly, the packaging may have other limitations which are aggravated by burn-in stress conditions, so that the packaging becomes a limitation for burn-in testing.

It is proposed that multiple integrated circuit devices be packaged as a single unit, known as a multi chip module (MCM). This can be accomplished with or without conventional lead frames. This creates two problems when using conventional test methods. Firstly, discrete testing is more difficult because a conventional lead frame package is not used. Furthermore, when multiple devices are assembled into a single package, the performance of the package is reduced to that of the die with the lowest performance. Therefore, such dies are tested on an individual basis at probe, using ambient and "hot chuck" test techniques, while still in wafer form. In other words, the ability to presort the individual dice is limited to that obtained through probe testing.

In addition, there is an increased interest in providing parts which are fully characterized prior to packaging. This is desired not only because of the cost of the package, but also because there is demand for multi-chip modules (MCMs), in which multiple parts in die form are tested and assembled into a single unit. While there are various techniques proposed for testing, burning in and characterizing a singulated die, it would be advantageous to be able to "wafer map" the die prior to assembly with as many performance characteristics as possible. Ideally, one would want to be able to map the wafer with full device characterization.

MCMs create a particular need for testing prior to assembly, as contrasted to the economics of testing parts which are discretely packaged as singulated parts. For discretely packaged parts, if the product yield of good parts from preliminary testing to final shipment (probe-to-ship) is, for example, 95%, one would not be particularly concerned with packaging costs for the failed parts, if packaging costs are 10% of the product manufacturing costs. Even where packaging costs are considerably higher, as in ceramic encapsulated parts, testing unpackaged die is economical for discretely packaged parts when the added costs approximates that of cost of packaging divided by yield: ##EQU1## where C=cost

C.sub.DIE =manufacturing cost of functional die

C.sub.ADDL. KGD =additional cost of testing unpackaged die in order to produce known good die (KGD)

Note that in the case of discretely packaged parts, the cost of the die (C.sub.DIE) is essentially not a factor. This changes in the case of MCMs: ##EQU2## Note that again C.sub.DIE is not a factor in modules having identical part types; however, the equation must be modified to account for varied costs and yields of die in modules with mixed part types.

With MCMs, the cost of packaging a failed part is proportional to the number of die in the module. In the case of a .times.16 memory array module, where probe-to-ship yield of the die is 95%, the costs are: ##EQU3## so the additional costs of testing for known good die (KGD) may be 16 times the cost of testing an unrepairable module and still be economical. This, of course, is modified by the ability to repair failed modules.

Testing of unpackaged die before packaging into multichip modules would be desirable as it would result in reduced material waste, increased profits, and increased throughput. Using only known good die in MCMs would increase MCM yields significantly.

Testing unpackaged die requires a significant amount of handling. Since the test package must be separated from the die, the temporary packaging may be more complicated than either standard discrete packaging or multichip module (MCM) packaging. The package must be compatible with test and burn-in procedures, while securing the die without damaging the die at the bondpads or elsewhere during the process.

In U.S. Pat. No. 4,899,107, commonly assigned, a reusable burn-in/test fixture for discrete TAB die is taught. The fixture consists of two halves, one of which is a die cavity plate for receiving semiconductor dies as the units under test (UUT); and the other half establishes electrical contact with the dies and with a burn-in oven.

The first half of the test fixture contains cavities in which die are inserted circuit side up. The die will rest on a floating platform. The second half has a rigid high temperature rated substrate, on which are mounted probes for each corresponding die pad. Each of a plurality of probes is connected to an electrical trace on the substrate (similar to a P.C. board) so that each die pad of each die is electrically isolated from one another for high speed functional testing purposes. The probe tips are arranged in an array to accommodate eight or sixteen dies.

The two halves of the test fixture are joined so that each pad on each die aligns with a corresponding probe tip. The test fixture is configured to house groups of 8 or 16 die for maximum efficiency of the functional testers.

There are some testing and related procedures when the parts are singulated. For this reason, it is inconvenient to retain multiple die in a single test fixture.

Various forms of connections are used to connect the die to a package or, in the case of a multichip module (MCM), to other connections. These include wirebonding, TAB connections, bump bonding directly to substrate, and conductive adhesives.

The bondpads are conductive areas on the face of the die which are used as an interconnect for connecting the circuitry on the die to the outside world. Normally, conductors are bonded to the bondpads, but it is possible to establish electrical contact through the bondpads by biasing conductors against the bondpads without actual bonding.

One of the problems encountered with burn in and full characterization testing of unpackaged die is the physical stress caused by connection of the bondpads to an external connection circuitry. This problem is complicated by the fact that in many die configurations, the bondpads are recessed below the surface level of a passivation layer. The passivation layer is a layer of low eutectic glass, such as BPSG, which is applied to the die in order to protect circuitry on the die. (The term "eutectic" does not, strictly speaking, apply to glass, which is an amorphous fluid; however, the term is used to describe the characteristic of some glasses wherein, as a result of their formulation, they readily flow at a given temperature.)

The ohmic contact between bondpads or test points on a die and a known good die test carrier package has been a matter of interest. It is difficult to achieve and maintain consistent ohmic contact without damaging the bondpads and passivation layer on the die. The design criteria of such contacts is somewhat different from the design criteria of the carrier package.

SUMMARY OF THE INVENTION

According to the present invention, probe tips are formed with projections which extend upward from a base. The probe tips establish electrical contact with bondpads or other contact locations on a surface such as a semiconductor die. In the case of bondpads on a semiconductor integrated circuit, the contact permits electrical communication between integrated circuit and external circuitry. The arrangement is suitable for flat bond pads or raised bump contacts.

In the preferred embodiments, the probe tips are formed on a substrate, and the substrate is formed from a material similar to that of the semiconductor integrated circuit die or wafer. In the case of silicon wafers, the substrate is formed from silicon material, thereby providing a coefficient of thermal expansion which matches that of the wafer. In one embodiment, the substrate is silicon, with one or more electrically isolating layers formed on the substrate. A plurality of raised conductors extend from the isolating layers and contact bondpads on the wafer. The conductive traces are in communication with the raised conductors in order to establish signal connections to perform the testing.

The intermediate substrate is preferably formed of a semiconductor material, and includes circuitry which is used to conduct signals between bondpad locations and external connector leads on the fixture. The substrate with circuitry is able to establish contact with the external connector leads, or with other leads on the fixture which are in communication with the external connector leads. In the preferred embodiment, the substrate is formed from silicon, although other semiconductor materials may be used. Examples of alternative materials include germanium and silicon on sapphire (SOS).

The substrate is formed with portions having increased height, such as bumps. These bumps, in turn, are formed with raised portions or points, so that the raised portion may penetrate the bondpad, while the remainder of the bump functions to limit penetration depth of the raised portion. This permits the penetration depth of the bump to be controlled by the physical dimensions of the raised portion. This results in the bumps being self-limiting in their penetration of the bondpads.

In a modification of the invention, a Z-axis anisotropic conductive interconnect material is provided as an interface between the substrate and the die. The Z-axis anisotropic conductive interconnect material is used to establish ohmic contact with bondpads or the equivalent attach points on the semiconductor die. The Z-axis anisotropic conductive interconnect material is able to conform to the shape of the die at the bondpad sufficiently to establish the ohmic contact without substantially damaging the bondpad. Since contact is able to be established by biasing force, it is possible to perform burn in and test of the die without resorting to bonding a conductor to the bondpad.

The Z-axis anisotropic conductive interconnect material is a metal filled polymer composite which is able to function as a compliant interconnection material for connector and testing applications. This material is in a group of materials which are referred to as elastomeric conductive polymer interconnect (ECPI) materials. These are available from AT&T Bell Laboratories, of Allentown, Pa., or Shin Etsu Polymer America Inc., of Union City, Calif., 3M Company of Minneapolis, Minn., at their Austin, Tex. plant or Nitto Denko America, Inc., San Jose, Calif. (a subsidiary of Nitto Denko Corporation of Japan).

The contact between the bondpads and the external connector leads is therefore established by utilizing the Z-axis anisotropic conductive interconnect material and substrate with circuitry. Conductors on the Z-axis anisotropic conductive interconnect material and substrate with circuitry extend from the bondpads to connection points, and the connection points conduct to contacts, which are in turn in communication with the external connector leads. The self-limiting nature of the bump is transferred through the Z-axis anisotropic conductive interconnect material so that the potential damage to the bondpad by force exerted through the Z-axis anisotropic conductive interconnect material is limited.

The various embodiments permit a substrate to be connected, through the contacts, to bondpads or testpoints on the die and conductors on the substrate. The connection may be permanent, or may be temporary. In the case of temporary connections, the contacts establish electrical contact with a wafer or a single die and with a burn-in oven, as well as permitting testing of dies in discretely packaged form. The contacts are thereby suitable for burn-in and testing of unpackaged die. In that application, after burn-in stress and electrical test, the wafer is removed from a test fixture and may be assembled in a conventional manner.

Connections of the substrate to the die may be effected through temporary carriers, such as described in U.S. patent application Ser. No. 8/073,003, filed Jun. 7, 1993, to Wood, Hembree, Doan and Farnworth, entitled, BONDPAD ATTACHMENTS USED TO TEMPORARILY CONNECT SEMICONDUCTOR DIE, and as described in U.S. patent application Ser. No. 08/046,675, filed Apr. 4, 1993, to Wood and Farnworth, entitled, CLAMPED CARRIER FOR TESTING 0F SEMICONDUCTOR DIES. These patent applications are hereby incorporated by reference.

The Z-axis anisotropic conductive interconnect material may be placed in a wafer or die receiving carrier between the die and the contacts so that the ohmic contact with the bondpads or testpoints on the die may be established through the Z-axis anisotropic conductive interconnect material, through the substrate, to communicate with external connections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a configuration in which a substrate has contact points for engaging bondpads on a semiconductor die;

FIG. 2 shows details of a raised portion of a bump, wherein the bump may be self-limiting in its penetration of the bondpads;

FIG. 3 i