Multi-stage digital to analog conversion circuit and method

What is claimed is:

1. A digital-to-analog conversion (DAC) circuit, comprising:

(a) an multi-stage interpolation filter circuit, having a multi-bit input and a multi-bit output;

(b) a noise shaper circuit, having a multi-bit input and a 1-bit output, said noise shaper input being connected to said multi-bit output from said multi-stage interpolation filter circuit; and

(c) a semi-digital FIR filter circuit, having a digital input and an analog output, with said FIR filter digital input being connected to said 1-bit output from said noise shaper circuit, wherein said FIR filter circuit further comprises a shift register having output taps and an input, said shift register input being connected to said FIR filter digital input, a plurality of current sinks, a plurality of DC offset current sources and a first and a second current summing operational amplifier, wherein said current sinks and DC offset current sources are selectively connected to inputs to said first and second current summing operational amplifiers and wherein said inputs of said first and second current summing operational amplifiers are also selectively connected to said output taps of said shift register.

2. The DAC circuit of claim 1, wherein a first stage of said multi-stage interpolation filter comprises a linear phase FIR filter having an input, an output and 2N-1 taps, whereby said first stage oversamples the frequency of a digital audio signal input to said first stage to twice the sample rate of said digital audio input signal.

3. The DAC circuit of claim 2, wherein a second stage of said multi-stage interpolation filter comprises a two-phase sinc.sup.5 interpolation second stage having an input and an output where said second stage input is connected to said output of said first interpolation stage, and whereby said sinc.sup.5 stage oversamples said output of said first interpolation stage to four times the sample rate of said digital audio signal input to said first interpolation stage, wherein said input of said second stage is connected to a first multiplier and to a first delay block, and wherein the output of said first delay block is input to a second delay block and to a second multiplier and, wherein the output of said second delay block is input to a third multiplier, wherein said first multiplier is within a first processing path, said second multiplier is within a second processing path and said third multiplier is within a third processing path, wherein said first, second and third processing paths operate in parallel, and wherein the output of said first processing path is summed with the output of said second processing path in a first summing node, and wherein the output of said third processing path and the output of said second processing path are summed in a second summing node, wherein an oversampler at the output of said second stage selectively samples between the output of said first summing node and said second summing node and outputs the sample so selected to said output of said second stage.

4. The DAC circuit of claim 3, wherein a third stage of said multi-stage interpolation filter comprises a sinc.sup.2 interpolation third stage having an input and an output, where said third stage output is connected to said output of said sinc.sup.5 second stage, whereby said sinc.sup.2 third stage oversamples said output of said sinc.sup.5 stage to 64 times the sample rate of said digital audio signal input to said first interpolation stage, wherein said third stage input is input to a double delay block and input to a first summing node, wherein the output of said double delay block is input to said first summing node as a negative input, wherein an output of said first summing node is input to a first single delay block and input to a second summing node, wherein the output of said first single delay block is input to said second summing node, and wherein an output of said second summing node is connected to an oversampler, wherein said oversampler selectively samples the output of said second summing node and inputs each said sample selected to an input of a third summing node at 16 times the clock rate of said third summing node, wherein an output of said third summing node is input to a second single delay block, wherein the output of said second single delay block is fed back to an input of said third summing node and is also output from said third stage as a 64 times oversampled signal.

5. The DAC circuit of claim 2, wherein said linear phase FIR filter first stage further comprises a two-phase filter, wherein a first phase sub-filter generates odd signal samples by multiplying said digital audio input signal by odd coefficients and wherein a second phase sub-filter generates even signal samples by multiplying said digital audio input signal by even coefficients, whereby said sub-filters execute in parallel.

6. The DAC circuit of claim 1, wherein said noise shaper circuit comprises a 5th order sigma-delta modulator.

7. The DAC circuit of claim 6, wherein said 5th order sigma-delta modulator has a signal transfer function of: ##EQU31## where X(z) is the digital audio input signal, whereby ##EQU32## W.sub.5 =-A.sub.5 K.sub.5, wherein A.sub.1-5 are pole positioning feedback coefficients, B.sub.1-2 are zero positioning feedback coefficients, and K.sub.1-5 are scaling factors.

8. The DAC circuit of claim 6, wherein said 5th order sigma-delta modulator has a noise transfer function of: ##EQU33## whereby ##EQU34## W.sub.5 =-A.sub.5 K.sub.5, wherein A.sub.1-5 are pole positioning feedback coefficients, B.sub.1-2 are zero positioning feedback coefficients, and K.sub.1-5 are scaling factors.

9. The DAC circuit of claim 1, wherein said noise shaper circuit extends the noise stop band to at least about 0.70 f.sub.s.

10. The DAC circuit of claim 1, wherein said noise shaper circuit extends the noise stop band of said noise shaper circuit to about 0.75 f.sub.s.

11. The DAC circuit of claim 1, wherein said noise shaper circuit comprises a fifth order sigma-delta network having five integrators, whereby scaling coefficients for two of said integrators are the same value as scaling coefficients for two other of said integrators.

12. The DAC circuit of claim 1, wherein said noise shaper circuit includes a fifth order sigma-delta network having a noise gain factor (K) of less than about 1.85.

13. The DAC circuit of claim 1, wherein said semi-digital FIR filter comprises:

(a) a shift register having a clock input, a 1-bit digital audio signal input and a plurality of data output taps;

(b) a plurality of current sinks;

(c) a plurality of DC offset current sources;

(d) a first and a second current summing operational amplifier, wherein each said current summing operational amplifier has a voltage output node and a positive and a negative input node, wherein said negative input node for each said current summing operational amplifier is a current summing input node which is connected to a different one of said DC offset current sources and is selectively connected to either said current sinks, and said positive input node for each said current summing operational amplifier is connected to a reference voltage, and wherein a first resistor is connected between said current summing node and said voltage output node on said first current summing operational amplifier, and wherein a second resistor is connected between said current summing node and said voltage output node on said second current summing operational amplifier, and wherein the voltage on said voltage output node on each said current summing operational amplifier is related to the value of said current sinks selectively connected to said current summing node for each said current summing operational amplifier; and

(e) an operational amplifier, having a single ended voltage output node and a positive and a negative voltage input node, wherein said negative voltage input node is connected through a third resistor to the voltage output node of said first or second current summing operational amplifier and said positive voltage input node is connected through a fourth resistor to the voltage output node of said other current summing operational amplifier, and a fifth resistor is connected to a reference voltage and to said positive voltage input node of said operational amplifier, and wherein a sixth resistor is connected between said negative voltage input node and said single ended voltage output node, whereby the voltage on said single ended voltage output node is related to the value of said current sinks selectively connected to said current summing node for each said current summing operational amplifier.

14. The DAC circuit of claim 13, wherein a first capacitor is connected in parallel with said first resistor and a second capacitor is connected in parallel with said second resistor.

15. A method of converting an n-bit digital signal to an analog signal, comprising the steps off

(a) inputting said n-bit signal to a multi-stage interpolator filter circuit;

(b) interpolating said input n-bit digital signal to 64 times the sample rate of said n-bit signal;

(c) outputting said interpolated signal to a noise shaper circuit;

(d) converting said interpolated signal to a 1-bit output signal;

(e) inputting said 1-bit output signal to a semi-digital FIR filter circuit, wherein said FIR filter circuit comprises a shift register having output taps and an input, said shift register input being connected to said FIR filter digital input, a plurality of current sinks, a plurality of DC offset current sources and a first and a second current summing operational amplifier, wherein said current sinks and DC offset current sources are selectively connected to inputs to said first and second current summing operational amplifiers and wherein said inputs of said first and second current summing operational amplifiers are also selectively connected to said output taps of said shift register; and

(f) converting said 1-bit signal to an analog output signal.

16. A method of converting an n-bit digital audio signal to an analog audio signal, comprising the steps of:

(a) inputting said n-bit audio signal to a three-stage interpolator filter circuit;

(b) interpolating said input n-bit digital signal in a first stage interpolator circuit to twice the sample rate of said n-bit digital audio signal;

(c) outputting said first stage interpolated signal to a second stage interpolator circuit;

(d) interpolating said first stage interpolated signal to four times the sample rate of said n-bit digital audio signal;

(e) outputting said second stage interpolated signal to a third stage interpolator circuit;

(f) interpolating said second stage interpolated signal to 64 times the sample rate of said n-bit digital audio signal;

(g) outputting said third stage interpolated signal to a 1-bit noise shaper circuit;

(h) converting said third stage interpolated signal to a 1-bit signal;

(i) outputting said 1-bit signal to a semi-digital FIR filter circuit, wherein said FIR filter circuit comprises a shift register having output taps and an input, said shift register input being connected to said FIR filter digital input, a plurality of current sinks, a plurality of DC offset current sources and a first and a second current summing operational amplifier, wherein said current sinks and DC offset current sources are selectively connected to inputs to said first and second current summing operational amplifiers and wherein said inputs of said first and second current summing operational amplifiers are also selectively connected to said output taps of said shift register; and

(j) converting said 1-bit signal to an analog audio output signal.

17. The method of claim 16, wherein said first stage interpolator circuit comprises a linear phase FIR filter.

18. The method of claim 16, wherein said second stage interpolator circuit comprises a sinc.sup.5 filter.

19. The method of claim 16, wherein said third stage interpolator circuit comprises a sinc.sup.2 filter.

20. The method of claim 16, further comprising the step of:

(k) low pass filtering said analog audio output signal.

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CROSS REFERENCE TO RELATED APPLICATIONS

The instant application is related to the following patent applications filed on even date herewith, all of which are assigned to the common assignee of the present invention, and all of which are hereby incorporated by referenced thereto and made a part hereof as if fully set forth herein:

Hazard-Free Divider Circuit, application Ser. No. 08/333,410; Monolithic PC Audio Circuit, application Ser. No. 08/333,451; Modular Integrated Circuit Power Control, application Ser. No. 08/333,537; Audio Processing Chip with External Serial Port, application Ser. No. 08/333,387; Wavetable Audio Synthesizer with Delay-Based Effects Processing, application Ser. No. 08/334,462; Wavetable Audio Synthesizer with Low Frequency Oscillators for Tremolo and Vibrato Effects, application Ser. No. 08/333,564; Wavetable Audio Synthesizer with Multiple Volume Components and Two Modes of Stereo Positioning, application Ser. No. 08/333,389; Wavetable Audio Synthesizer with an Interpolation Technique for Improving Audio Quality, application Ser. No. 08/333,398; Monolithic PC Audio Circuit with Enhanced Digital Wavetable Audio Synthesizer, Ser. No. 08/333,536; Wavetable Audio Synthesizer with Waveform Volume Control for Eliminating Zipper Noise, application Ser. No. 08/333,562; Digital Signal Processor Architecture for Wavetable Audio Synthesizer, application Ser. No. 08/334,461; Wavetable Audio Synthesizer with Enhanced Register Array, application Ser. No. 08/334,463; A Digital Decimation and Compensation Filter System, application Ser. No. 08/333,403; Digital Interpolation Circuit for Digital to Analog Converter Circuit, application Ser. No. 08/333,399; Analog to Digital Converter Circuit, application Ser. No. 08/333,535; Stereo Audio Codec, application Ser. No. 08/333,467; and Digital Noise Shaper, application Ser. No. 08/333,386.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

This invention relates to a circuit for converting digital signals to analog signals. More particularly, this invention relates to a digital-to-analog converter having an interpolator circuit, and a noise shaping circuit and a semi-digital filter.

2. Brief Description of the Related Technology

Converting digital signals to analog signals is accomplished using a digital-to-analog converter (DAC). These DACs typically operate by a resistor, capacitor divider, or current steering method to convert digital-to-analog signals or, operate using a sigma-delta conversion method. Sigma-delta DACs are often preferred because of their inherent feasibility to be manufactured as integrated circuits in standard digital integrated circuit processes.

Many DACs utilize oversampled digital data output from an interpolation circuit, which is then converted by DAC circuitry into an analog output. Sigma-delta DACs inherently introduce noise outside the passband of the DAC converter circuit. To alleviate this out of band noise, various filtering techniques are employed.

SUMMARY OF THE INVENTION

The present invention is for a digital-to-analog conversion circuit (DAC) which includes an interpolation filter circuit, a noise shaper circuit, and a semi-digital FIR filter circuit. The interpolator oversamples a digital input signal to 64 times the sample rate of the multi-bit digital input signal. A noise shaper circuit then converts the multi-bit signal output from the interpolation filter to a one-bit signal. The one-bit signal is then input to a semi-digital FIR filter which converts the one-bit signal to an analog signal and low pass filters the analog signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the various functional blocks of the present invention;

FIG. 2 is a schematic of the preferred embodiment of the left channel stereo mixer of the present invention;

FIGS. 2a-1 and 2a-2 is a table of gain and attenuation values;

FIG. 3 is a diagram of a partial wave form indicating signal discontinuities for attenuation/gain changes;

FIG. 4 is a block diagram showing zero detect circuits for eliminating "zipper" noise.;

FIG. 5 is a block diagram showing clock generation functions in the present invention;

FIG. 6 is a block diagram of serial transfer functions of the present invention;

FIG. 6a is a block diagram of the serial transfer control block;

FIG. 7 is a block diagram showing internal and external data paths and interfacing with external devices, supported by the present invention;

FIG. 8 is a block diagram of the digital to analog converter block of the present invention;

FIG. 9 is a block diagram of the digital portion, through the noise shaping block, of the digital to analog converter block of the present invention;

FIGS. 10a-10f are graphs showing output spectra of various stages of the DAC block;

FIG. 11 shows six graphs representing time domain outputs of various stages of the DAC block;

FIG. 12 is a schematic representation of the Interp.1 block, phase 1 of FIG. 9;

FIG. 13 is a schematic representation of the Interp.1 block, phase 2 of FIG. 9;

FIG. 14 is a schematic representation of the Interp.2 block of FIG. 9;

FIG. 15 is a graph of the frequency response of the Interp.2 block of FIG. 9;

FIG. 16 is a graph representing the in-band roll-off of the Interp.2 block of FIG. 9;

FIG. 17 is a schematic representation of an embodiment of the Interp.3 block of FIG. 9;

FIG. 18 is a schematic representation of another embodiment of the Interp.3 block of FIG. 9;

FIG. 19a is a graph of the frequency response of the Interp.3 block of FIG. 9;

FIG. 19b is a graph of the passband roll-off of the Interp.3 block of FIG. 9;

FIG. 20 is a schematic representation of the noise shaper block of FIG. 9;

FIG. 21 is a signal flow graph (SFG) of the noise shaper block in FIG. 9;

FIG. 22 is a plot of the poles and zeros in the s plane for the noise shaper block of FIG. 9;

FIG. 23 is a plot of the noise transfer function magnitude of the noise shaper block of FIG. 9;

FIG. 24 is a plot of the poles and zeros in the z plane of the noise shaper block of FIG. 9;

FIG. 25 is a graph of the noise transfer function of the noise shaper filter of FIG. 9;

FIG. 26 is a plot of the ideal and realizable zeros of the noise filter block of FIG. 9;

FIG. 27 is a plot comparing two embodiments of noise transfer functions for the noise shaper block of FIG. 9;

FIG. 28 is a plot of the noise and signal transfer functions of the noise shaper block of FIG. 9;

FIG. 29 is a plot of the signal transfer function magnitude and phase in the passband of the noise shaper block of FIG. 9;

FIG. 30 is a graph of the group delay (sec.) of the noise shaper block of FIG. 9;

FIG. 31 is a graph of the constant attenuation/gain contours of various embodiments of the noise shaper block of FIG. 9;

FIG. 32 plots A.sub.max (maximum input amplitude) versus noise gain k for an embodiment of the noise shaper block of FIG. 9; and

FIG. 33 is a graph of the noise gain k versus band width for G=-90 dB for a preferred embodiment of the noise shaper block of FIG. 9.

FIG. 34 is a graph showing the impulse response of the D/A semi-digital FIR filter;

FIG. 35 is a graph showing the frequency response of the D/A semi-digital FIR filter;

FIG. 36 schematically illustrates one embodiment of the D/A conversion circuit of the present invention;

FIGS. 37 and 38 schematically illustrate another embodiment showing the differential D/A conversion circuit of the present invention;

FIG. 39 is a block diagram of the CODEC ADC of the present invention;

FIG. 40 is a block diagram of the digital portion of the CODEC ADC;

FIG. 41 is a graph illustrating the sigma-delta modulator output spectrum for the ADC of the present invention;

FIG. 42 is a graph illustrating the sigma-delta modulator output spectrum, in more detail;

FIG. 43 is a graph illustrating the output spectrum of the sinc6 Decim.1 filter output;

FIG. 44 is a graph illustrating the output spectrum of the half-band Decim.2 filter output;

FIG. 45 is a graph illustrating the output spectrum of the 16-bit Decim.3 filter output;

FIG. 46 is a block diagram of the Decim.1 filter;

FIG. 47 graphically illustrates the frequency response of the Decim.1 filter;

FIG. 48 graphically illustrates a detailed frequency response inside the passband of the Decim.1 filter;

FIG. 49 is a block diagram of the half-band Decim.2 filter-direct form;

FIG. 50 is a block diagram of the half-band Decim.2 filter-transposed form;

FIG. 51 graphically illustrates the frequency response of the Decim.2 filter;

FIG. 52 is a detailed frequency response graph in the passband of the Decim.2 filter;

FIG. 53 is a block diagram of the compensation filter of the CODEC A/D conversion circuitry;

FIG. 54 graphically illustrates the frequency response of the Decim.3 filter;

FIG. 55 graphically illustrates, in detail, the frequency response of the Decim.3 filter;

FIG. 56 graphically illustrates the compensator circuit frequency response;

FIG. 57 graphically illustrates the total frequency response of the decimator circuitry in the passband (un-compensated); and

FIG. 58 graphically illustrates the total frequency response of the decimator circuitry in the passband (compensated).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 depicts, in block diagram format, the various features and functions included within the CODEC module device 505. The CODEC device 505 includes on-chip memory, which is preferably configured as 16-sample, 32-bit wide, record and playback FIFOs, 538, 532, with selectable thresholds capable of generating DMA and I/O interrupts for data read and write operations. The Mixing and Analog Functions block 510 includes left and right channel analog mixing, muxing and loopback functions. Left channel and right channel stereo, and single channel mono, analog audio signals are summed in Mixing and Analog Functions block 510. These mono and stereo audio signals are output from the CODEC 505 for external use, on analog output pins 522. Inputs to the Mixing and Analog Functions block 510 are provided from: external Analog Input Pins 520, analog output from a Synthesizer Digital-to-Analog Converter block 512, which is external to CODEC 505 or may be a processing block within CODEC 505, and from the Playback Digital-to-Analog Converter block 514. Analog audio output from Mixing Analog Functions block 510 is provided to record Analog-to-Digital Converter 516 block. Synthesizer Digital-to-Analog Converter block 512 receives Digital data from a synthesizer 524. Throughout this description, it should be understood that synthesizer 524 is an external device, or may be integrated onto the same monolithic integrated circuit as the CODEC device 505.

The record path for the CODEC 505 is illustrated in FIG. 1, with analog audio data being output from Mixing and Analog Functions block 510 and provided to record Analog-to-Digital Converter (ADC) 516 block to be converted to 16-bit signed data. The selected sample rate for record ADC 516 affects the sound quality such that the higher the sample rate for record ADC 516, the better the recorded digital audio signal approaches the original audio signal in quality. The function and operation of a fourth order cascaded delta-sigma modulator, preferably implemented in record ADC 516 block, is described in application Ser. No. 08/071,091, filed Dec. 21, 1993, entitled "Fourth Order Cascaded Sigma-Delta Modulator," assigned to the common assignee of the present invention. The converted digital audio data is then sent to format conversion block 536 which converts the 16-bit digital audio data to a preselected data format. The formatted digital data is then sent to 32-bit wide record FIFO 538 as 16-bit left and 16-bit right channel data for further submission to register data bus 526 for output to external system memory (not shown) or to off-chip local memory record FIFO 530 (LMRF).

The playback path for CODEC 505 includes digital data, in a preselected data format, being sent to 32-bit wide playback FIFO 532 from the off-chip local memory playback FIFO (LMPF) 528 or from external system memory (not shown), via the register data bus 526. It should be understood throughout this application that LMRF 530 and LMPF 528 may be discreet off-chip FIFOs, or may be dedicated address space within off-chip local memory 110 configured as FIFOs. The formatted data is then input to format conversion clock 534, where it is converted to 16-bit signed data. The data is then sent to the CODEC playback DAC 514, where it is converted to an analog audio signal and output to the input of Mixing and Analog functions block 510.

A Serial Transfer Control block 540 provides serial-to-parallel and parallel-to-serial conversion functions, and loop back capability between the output of 32-bit wide record FIFO 538 and the input of 32-bit wide playback FIFO 532. Also, synthesizer serial input data port 542 (FIG. 1), which receives serial data from synthesizer 524, communicates with serial Transfer Control block 540. Serial Transfer Control block 540 is connected to record FIFO 538, playback FIFO 532, off-chip local memory 110 (or, LMRF 530 and LMPF 528) via local memory control 790, synth serial input data port 542, and to External Serial Interface. Bi-directional serial data communication over External Serial Interface 544, which includes an external serial port, is provided to Serial Transfer Control block 540 (also see FIG. 6). External serial interface 544 may be a UART, or other device that provides either synchronous or asynchronous controlled serial data transfers. External Serial Interface 544 (FIG. 1) can be connected to communicate serially with an external digital signal processor (DSP) for off-chip generation of special audio effects, or with any other device capable of bi-directional serial data communication. External serial interface 544 can also connect to and provide a serial data path from external synthesizer serial input port 542. Bi-directional data transfer is also accomplished via data path 550 between serial transfer control 540 and local memory control 790.

The various loop back and data conversion functions associated with Serial Transfer Control block 540 are shown in more detail in FIGS. 6 and 6a.

The CODEC 505 includes A/D conversion functions in the record path and D/A conversion functions in the playback path. These conversion functions are capable of operating independently of each other at different sample rates so A/D and D/A operations may be performed simultaneously, each having a different sample rate and data format. Loop access circuitry (in mixing block 606) provides a capability to sample an audio signal and perform an A/D operation at one rate, digitize the signal, and then playback the digitized sample back through the playback D/A at a different sample rate.

The block designated Counters, Timers and Miscellaneous digital functions 518 includes circuitry which controls: the A/D and D/A conversions in CODEC 505, format conversion blocks 532, 536, and data transfer functions. CODEC 505 operation allows the following data formats: 8-bit unsigned linear; 8-bit .mu.-law; 8-bit A-law; 16-bit signed little endian; 16-bit signed big endian; or 4-bit 4:1 IMA ADPCM format.

Referring to FIG. 2, the left channel of CODEC analog mixer 606 of Mixing and Analog functions block 510 is depicted. The layout of the right channel of mixer 606 is identical to the left channel, but is not shown in FIG. 2. Except for minor signal name modifications, all descriptions of left channel signals and functions are applicable to the right channel.

The CODEC analog mixer 606 has more programmable features and more functions than prior CODEC audio devices. Each of the five input lines to the analog mixer 606 in FIG. 2 (LINEINL 682, MICL 684, AUXIL 686, AUX2 688 and MONOIN 690) includes a programmable attenuation/gain control circuit 608, 610, 612, 614 and 696, respectively. All inputs and outputs to and from analog mixer 606, are stereo signals, except for input MONOIN 690 and output MONOOUT 668, which are mono signals. The choice of mono or stereo audio signal inputs or outputs is also selectable.

Each of the triangle blocks depicted in FIG. 2 represents a programmable attenuation/gain control circuit. The registers that control the respective attenuation/gain control circuits and the attenuation/gain range for that circuit are identified in FIG. 2 next to the respective triangle block, and are located in the Registers block 566 in FIG. 7. The description and address of each of these registers is described below. Individual bits in these registers are capable of being modified as described in application Ser. No. 08/171,313, entitled Method and Apparatus for Modifying the Contents of a Register via a Command Bit, which describes a single-bit manipulation technique that obviates the need to address an entire register, and is assigned to the common assignee of the present invention and incorporated herein for all purposes.

The range of attenuation values for these registers are shown in FIGS. 2a-1 and 2a-2. The value stored in each attenuation/gain control register is used to provide the selected gain or attenuation value to CODEC control logic in the Counters, Timers and Misc. Digital Functions block 518, and Gain/attenuation Block 734 (FIG. 4) explained below. The amplitude of the analog audio signal input to the respective attenuation/gain circuit is controlled by the value stored in the respective attenuation/gain control register.

The overview of the registers used in CODEC 505 Registers block 566, including their preferred functions, are as follows:

The CODEC 505 is designed to be generally register-compatible with the CS4231 (Modes 1 and 2), with the AD1848 and other prior art. An indirect addressing mechanism is used for accessing most of the CODEC registers. In Mode 1 (discussed below), there are 16 indirect registers; in Mode 2 (discussed below), there are 28 indirect registers; and in Mode 3 (discussed below), there are 32 indirect registers.

In the following register definitions, RES or RESERVED specifies reserved bits. All such fields must be written with zeros; reads return indeterminate values; a read-modify-write operation can write back the value read.

CODEC DIRECT REGISTERS

CODEC INDEX ADDRESS REGISTER (CIDXR)

Address: PCODAR+0 read, write

Default: 0100 0000

Modes: bits[7:5,3:0] modes 1, 2, and 3; bit[4] modes 2 and 3 ##STR1## INIT Initialization. This read-only bit will be read as high if the CODEC is in an initialization phase and unable to respond to I/O activity. This bit is set only by software resets and cleared once the 16 MHz oscillator is stable and the CODEC 505 has initialized.

MCE Mode Change Enable. This bit protects the CPDFI, CRDFI, and CFIG1I from being written (except CFIGiI[1:0]; these can be changed at any time). When high, the protected registers can be modified; also, the DAC outputs (CLDACI and CRDACI) are forced to mute. When low, the protected registers cannot be modified.

DTD DMA Transfer Disable. This bit high causes DMA transfers to be suspended when either of the sample counter interrupts of CSR3R becomes active.

Mode 1: DMA is suspended (whether it be playback or record) and the sample counter stops after the sample counter causes an interrupt; also, the active FIFO is disabled from transferring more data to CODEC 505. DMA transfers, FIFO transfers and the sample counter resume when GINT is cleared or DTD is cleared.

Modes 2 and 3: Record DMA, the record FIFO and the record sample counter stop when the record sample counter causes an interrupt; playback DMA, the playback FIFO and the playback sample counter stop when the playback sample counter causes an interrupt. The pertinent DMA transfers and sample counter resume when the appropriate interrupt bit in CSR3I is cleared or DTD is cleared.

In mode 3, this bit also works to discontinue the transfer of data between the CODEC FIFOs and the LMRF and the LMPF.

IA[4:0] Indirect Address Pointer. These bits are used to point to registers in the indirect address space. In mode 1, a 16-register space is defined; IA[4] is reserved. In modes 2 and 3, a 32-register space is defined.

CODEC INDEXED DATA PORT (CDATAP)

Address: PCODAR+1 read, write

Modes: 1, 2, and 3

This is the access port through which all CODEC indexed registers--pointed to by the CODEC Indexed Address Register (CIDXR[4:0])--are written or read.

CODEC STATUS 1 REGISTER (CSR1R)

Address: PCODAR+2 read, (also, a write to this address clears GINT)

Default: 11001110

Modes: 1, 2, and 3

This register reports the interrupt status and various playback and record FIFO conditions. Reading this register also clears CSR2I[7:6] and CSR3I[3:0], if any are set. Writing to this register will clear all CODEC interrupts. ##STR2## RULB Record Channel Upper/Lower Byte Indication. When high, this bit indicates that a read of the record FIFO will return the upper byte of a 16-bit sample (bits[15:8]) or that the record data is 8-or-less bits wide. When low, this bit indicates that a read of the record FIFO will return the lower byte of a 16-bit sample (bits[7:0]). After the last byte of the last received sample has been read from the record FIFO, this bit does not change from its state