Disk controller with volatile and non-volatile cache memories

What is claimed is:

1. A disk controller coupled between a host computer and a disk drive, the disk controller comprising:

a controller microprocessor;

a cache memory including:

at least one volatile memory module; and

at least one non-volatile memory module;

a cache memory control circuit coupled to said at least one non-volatile memory module and said at least one volatile memory module wherein in response to a write command received from the host computer, said controller microprocessor allocates a predetermined number of memory blocks in each of said at least one volatile and said at least one non-volatile memory modules for storage of write-data and upon completion of a write operation to said at least one non-volatile memory modules, said cache memory control circuit transfers the write-data from said at least one non-volatile memory module to said at least one volatile memory module.

2. The disk controller of claim 1 wherein:

said controller microprocessor includes a memory having stored therein a list of memory blocks available for use in said at least one non-volatile memory module and wherein said controller microprocessor is adapted to allocate from the list a predetermined number of memory blocks of said at least one non-volatile memory module for storage of the host write-data thereby removing the predetermined number of memory blocks of said at least one non-volatile memory module from the list of memory blocks available for use; and

said controller is adapted to allocate a corresponding number of memory blocks of said at least one volatile memory module such that said cache memory control circuit can transfer the write-data from the predetermined memory blocks of said at least one non-volatile memory module to the corresponding memory blocks of said at least one volatile memory module.

3. The disk controller of claim 2 wherein said cache memory control circuit transfers the write data from said at least one non-volatile memory module to said at least one volatile memory module with a DMA transfer.

4. The disk controller of claim 3 wherein the list of available memory blocks is provided from a plurality of linked domains wherein each of said plurality of linked domains represents a predetermined number of memory blocks and wherein each of said plurality of domains has associated therewith a valid field and an in-operation field which indicate the status of each memory block in said domain.

5. The disk controller of claim 3 wherein in response to write-data being stored on the disk drive, the allocated memory blocks of said at least one non-volatile memory module are de-allocated and added to the list of memory blocks available for use.

6. The disk controller of claim 5 further comprising a sequence counter for tracking the number or write operations in particular one of said plurality of domains.

7. The disk controller of claim 3 wherein said cache memory control circuit is provided as an application specific integrated circuit.

8. The disk controller of claim 7 wherein:

said controller microprocessor includes a memory having stored therein a list of memory blocks available for use in said at least one non-volatile memory module wherein the list of available memory blocks is provided from a plurality of linked domains wherein each of said plurality of linked domains represents a predetermined number of memory blocks and wherein each of said plurality of domains has associated therewith a valid field and an in-operation field which indicate the status of each memory block in said domain;

said at least one volatile memory module is provided as a single in-line memory module; and

said at least one non-volatile memory module is provided as a single in-line memory module.

9. A disk storage subsystem comprising:

at least one disk drive; and

a disk controller coupled to said disk drive and adapted to couple to a host computer, said disk controller comprising:

a controller microprocessor;

a cache memory including:

a plurality of volatile memory modules which form a read-cache;

a plurality of non-volatile memory modules which form a write-cache; and

a cache memory control circuit coupled to said non-volatile memory module and said volatile memory module wherein in response a write command received from the host computer, said controller microprocessor allocates a predetermined number of memory blocks in each of said volatile and said non-volatile memory modules for storage of write data and upon completion of a write operation to said non-volatile memory modules, said cache memory control circuit transfers the write data from said non-volatile memory module to said volatile memory module.

10. The disk storage subsystem of claim 9 wherein:

said plurality of volatile memory modules which form said read-cache are provided from a plurality of physically separate memory modules; and

said plurality of non-volatile memory modules which form said write-cache are provided from a plurality of physically separate memory modules.

11. The disk storage subsystem of claim 10 wherein at least one of said plurality of non-volatile memory modules is provided as a single in-line memory module.

12. The disk storage subsystem of claim 11 wherein said controller microprocessor includes a memory having stored therein a list of memory blocks available for use in said non-volatile memory module wherein the list of available memory blocks is provided from a plurality of linked domains wherein each of said plurality of linked domains represents a predetermined number of memory blocks and wherein each of said plurality of domains has associated therewith a valid field and an in-operation field which indicate the status of each memory block in said domain.

13. The disk storage subsystem of claim 11 wherein:

said controller microprocessor includes a memory having stored therein a list of memory blocks available for use in said non-volatile memory module and wherein said controller microprocessor is adapted to allocate from the list a predetermined number of memory blocks of said non-volatile memory module for storage of the host write-data thereby removing the predetermined number of memory blocks of said non-volatile memory module from the list of memory blocks available for use; and

said controller is adapted to allocate a corresponding number of memory blocks of said volatile memory module such that said cache memory control circuit can transfer the write-data from the predetermined memory blocks of said non-volatile memory module to the corresponding memory blocks of the volatile memory module.

14. The disk storage subsystem of claim 12 wherein in response to write-data being stored on the disk drive, the allocated memory blocks of said non-volatile memory module are de-allocated and added to the list of memory blocks available for use.

15. The disk storage subsystem of claim 14 wherein said at least one disk drive is a first one of a plurality of disk drives each of said plurality of disk drives coupled to provide a redundant array of inexpensive disks.

16. A method of transferring data to be written from a host computer to at least one disk drive within a disk storage subsystem including a host interface circuit, a disk interface circuit, a controller microprocessor, a cache memory, a cache memory management circuit and the at least one disk drive, the method comprising the steps of:

receiving in the disk storage subsystem a host write-to-disk command;

allocating a predetermined number of memory blocks in a non-volatile memory module of the cache memory;

allocating a predetermined number of memory blocks in a volatile memory module of the cache memory;

storing the data to be written to the at least one disk drive in the allocated memory blocks of the non-volatile memory module of the cache memory; and

initiating a DMA transfer by the cache memory management circuit, to copy the data to be written to the at least one disk drive from the allocated memory blocks of the non-volatile memory module to the allocated memory blocks of the volatile memory module of the cache memory.

17. The method of claim 16 further comprising the step of transferring the data to be written from the allocated memory blocks of the volatile memory module of the cache memory to the at least one disk drive.

18. The method of claim 16 wherein the step of transferring the data to be written from the allocated memory blocks of the volatile memory module to the at least one disk drive includes the step of writing data across each of a plurality of disk drives coupled to provide a redundant array of inexpensive disks.

19. The method of claim 18 further comprising the step of writing parity information across each of the plurality of disk drives.

20. The method of claim 17 wherein after the step of transferring the data to be written from the allocated memory blocks of the volatile memory module to the at least one disk drive performing the step of de-allocating the predetermined number of memory blocks in the non-volatile memory module of the cache memory.

21. A method of controlling a cache memory of a disk storage subsystem coupled to a host computer, the method comprising the steps of:

establishing a list of available memory blocks in a write-cache;

in response to a write operation initiated by a host computer, allocating from the list of available memory blocks a predetermined number of memory blocks of the write-cache;

allocating a like predetermined number of blocks in a read-cache;

receiving write-data from the host computer;

storing the write-data in the allocated memory blocks of the write-cache;

indicating to the host computer that the write-data stored in the read-cache is valid and available for use; and transferring the write-data from the allocated memory blocks of the write-cache to the allocated memory blocks of the read-cache.

22. The method of claim 21 further comprising the step of storing the write-data on a disk drive of the disk storage subsystem.

23. The method of claim 22 further comprising the step of de-allocating the allocated memory blocks of the write-cache.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates to disk storage subsystems and more particularly to cache memory management in disk storage subsystems.

BACKGROUND OF THE INVENTION

Due to the large amount of information processed by present day computer systems, there is a trend to couple a disk storage subsystem to a host computer to thus increase the data storage capability and efficiency of the host computer.

Disk storage subsystems typically include a disk controller and one or more disk drives. The disk controller includes a controller microprocessor coupled to a host interface circuit and a disk interface circuit. The controller microprocessor generally coordinates and controls the transfer of data from the host computer to the disk storage subsystem and vice-versa.

As is known, the increasing performance characteristics of central processor units (CPUs) and memories in host computers has not generally been matched by similar performance increases in disk storage subsystems. In particular, mechanical latency i.e. the time required to access data or instructions stored in the disk storage subsystem of a computer, has increasingly become the factor which prevents the full realization of the speed of contemporary computer systems. This result is occurring because the speed of CPUs has outstripped the speed with which disk storage subsystems can provide data to a host.

The longer it takes to obtain data from the disk storage subsystem, the slower a host CPU runs because CPUs usually remain idle while waiting for data. Thus, one negative effect of disk latency is its effect on CPU speed.

This negative effect has increased as CPU speed has outstripped disk subsystem speed. Thus, despite the advances made in high density, high speed disk storage subsystems, disk storage subsystems typically remain the speed limiting link in a computer system. One way to reduce average latency in a disk storage subsystem is to add a cache memory to the disk storage subsystem.

A cache memory generally includes a relatively small memory device physically situated proximate the disk controller of the disk storage subsystem. The caching method is software controlled. Due to the physical proximity of the cache memory to the disk controller and the nature of the cache memory control, latency of the cache memory is several times less than the latency of the disk drives. Since cache memory latency is much less than disk drive latency, overall system speed is improved in disk storage subsystems that include a cache memory.

Cache memories capitalize on the characteristic that once a host computer reads data from or writes data to the disk drives, it is very likely that this data will be reused by the host computer in the near future. For simplicity of description, data, instructions and any other forms of information commonly stored in computer memories are collectively hereinafter referred to as data. Thus, frequently used data or instructions are replicated in cache memories.

When the host computer initiates a data write operation for example, the data is first stored in the cache memory and then subsequently stored on the disk drives. If the host computer later requests the same data, the data may thus be retrieved from the cache memory rather than from a disk drive.

Retrieving data from the cache memory avoids the necessity of accessing one or more disk drives of the disk storage subsystem which are relatively slow compared to the cache memory. Therefore data retrieval is accomplished more rapidly which in turn leads to an overall increase in system performance.

While disk storage subsystems that include a cache memory have a number of advantages, one disadvantage is the expense of cache memories. This disadvantage is amplified because a cache memory does not add memory capacity to disk storage subsystem. Rather, cache memories are add-ons to disk memory, because, as noted above cache memories replicate data stored in the disk drives of the disk storage subsystem.

Another problem which arises with cache memories is the need to maintain coherency between data stored in the cache memory and data stored on the disk drives of the disk storage subsystem. More specifically, since data stored at either location can be updated, a disk storage subsystem that includes a cache memory must also include a technique for maintaining coherency between the same data stored in the cache memory and the disk drives. If coherency is not maintained, data at one memory location may become stale and the same data at another memory location may be updated. The subsequent use of stale or corrupt data in the computer system can lead to errors.

Several different types of cache management techniques have been developed to control the process which occurs when data stored in a cache memory are updated. Generally, in response to a host processor initiated write operation, the write-data is written to the cache memory and then propagated directly to the disk drives. Cache memories throughout the disk storage subsystem are searched and any copies of written data are either invalidated or updated.

Another problem with cache memories is the volatile nature of the cache memories. That is, data stored in volatile cache memories is lost in the event of a power or device failure in the disk controller.

One solution to this problem is to provide the entire cache memory as a non-volatile cache memory. For example, the cache memory may include a battery back-up circuit which provides power to the cache memory in the event of a power failure. One problem with this approach, however, is the large expense involved in providing a cache memory having a battery circuit and a power sense circuit to detect when a power failure is occurring and that batteries should be engaged for back up operation. Moreover, such battery and power sense circuits lead to a relatively complex cache memory circuit design. Also the additional circuitry may reduce the reliability of the cache memory.

Furthermore, if the entire cache is provided as a non-volatile cache it is relatively difficult and expensive to duplicate the contents of the cache memory since it would be necessary to provide a second non-volatile cache memory having a memory size equal to or greater than first non-volatile cache memory so that the contents of the first non-volatile cache memory could be duplicated and stored to protect the contents before transfer to a drive disk.

It would be desirable, therefore, to provide a disk storage subsystem which includes a cache memory system which is relatively inexpensive, which minimizes the chance of corrupting data and which maintains the data integrity of the disk storage subsystem.

SUMMARY OF THE INVENTION

To increase the data integrity of disk storage subsystems, a cache memory can include both a volatile memory portion and a non-volatile memory portion. The volatile memory portion of the cache memory may be provided from volatile memory modules while the non-volatile memory portion may be provided from non-volatile memory modules.

Data transferred between the host computer and one or more disk drives of the disk storage subsystem is written to and read from the volatile cache memory modules. The non-volatile memory modules duplicate or mirror data stored in the volatile memory modules. Each non-volatile memory module can include a battery back-up power source which powers the non-volatile memory modules in the event of system power failure.

With this approach, the cost of the cache memory is minimized because rather than providing the entire cache memory as a non-volatile cache memory, the cache memory can include several non-volatile memory modules and a greater number of volatile memory modules. Moreover, the data integrity of the system is increased since in the event of a system power failure, for example, data stored in the non-volatile memory is preserved until the system power is restored. Upon power restoration the data may be retrieved from the non-volatile memory modules. Alternatively, if power cannot be restored, the non-volatile memory modules may be transferred to a different disk controller which has not lost power. This likewise increases the data integrity of the system since a user can restore the data preserved on the non-volatile memory module with relatively little difficulty.

The volatile cache memory is generally accessed by the disk subsystem controller microprocessor as a physically and logically contiguous memory. This is generally true even where the volatile cache memory may be provided from one or more physically separate volatile memory modules.

Each non-volatile memory module, on the other hand, is generally accessed as a physically and logically separate memory. This gives rise to certain problems in cache memory management of the volatile and non-volatile cache memory modules. Since the volatile and non-volatile memory modules are physically and logically separate, a technique is required to either update or invalidate data which is stored in both the volatile and non-volatile cache memory modules and thus prevent the corruption of data in the disk storage subsystem.

One approach to solving this problem is to provide separate cache memory management circuits for each of the logically and physically separate non-volatile memory modules. This approach, however, leads to a relatively expensive and complicated cache system since each of the separate cache memory management circuits must be coupled together and there activities must be coordinated to prevent data corruption.

It would thus be desirable to provide a relatively simple, low cost cache memory which includes a non-volatile memory module and a volatile memory module and which protects against data corruption in the cache memory.

It would also be desirable to provide a technique for managing a cache memory which includes at least one volatile memory module and a plurality of physically and logically separate non-volatile memory modules.

A disk controller is presently disclosed which includes a controller microprocessor coupled to a cache memory. The cache memory includes one or more volatile cache memory modules and one or more non-volatile cache memory modules which are physically and logically separate or disjoint from each other and from the volatile cache memory modules. A cache memory control circuit is coupled to each of the volatile and non-volatile cache memory modules. In response to a write command received from a host computer, the controller microprocessor allocates a predetermined number of memory blocks in the non-volatile cache memory modules. After allocating the memory blocks of the non-volatile cache memory, the disk controller selects and allocates a corresponding plurality of memory blocks in the volatile memory modules. Host supplied write-data is then stored in the allocated memory blocks of the non-volatile memory module. Immediately thereafter the subsystem sends an acknowledgment signal to the host that the write operation is complete. The cache memory control circuit then performs a direct memory access (DMA) operation to copy the write-data from the allocated memory blocks of the non-volatile memory module to the corresponding allocated memory blocks of the volatile memory module. The write-data is then stored on a disk drive at which point the allocated memory blocks of the non-volatile memory are de-allocated and thus made available for further use. Thus, by allocating memory blocks of the non-volatile memory only on an as-needed basis, the physically and logically disjoint volatile and non-volatile memories can be managed as if they were a single cache memory. Also by de-allocating the memory blocks of non-volatile memory module immediately after the data is written to disk, the data integrity of the disk controller can be improved with only a limited number of non-volatile memory modules rather than providing the entire cache as a non-volatile cache memory.

The memory