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Claims  |
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What is claimed is:
1. In an integrated circuit having a plurality of circuit components and a
clock generator circuit, an apparatus for supplying a plurality of
synchronous clock signals to said plurality of circuit components, said
plurality of synchronous clock signals referenced from said clock
generator circuit, said apparatus comprising:
a plurality of global clock driver means uniformly disposed along a
periphery of said integrated circuit, said plurality of global clock
driver means for generating a plurality of synchronous clock signals;
a plurality of feeder means, each feeder means coupled to a global clock
driver means, said plurality of feeder means for supplying said plurality
of synchronous clock signals from said periphery of said integrated
circuit to said plurality of circuit components of said integrated
circuit; and
power cell means disposed along edges of said integrated circuit for
providing spatial areas within said integrated circuit, for coupling said
integrated circuit to a power source, said plurality of global clock
driver means disposed within said power cell means of said integrated
circuit.
2. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 1 further
comprising:
an intermediate driver stage comprising a plurality of intermediary clock
drivers for supplying clock signals to said plurality of global clock
driver means, each of said intermediary clock drivers for supplying a set
of global clock driver means via an intermediary clock supply network.
3. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 2 further
comprising:
a common clock driver stage comprising a common clock driver for supplying
a clock signal generated by said clock generator circuit to said plurality
of intermediary clock drivers via a common clock supply network.
4. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 3 wherein said
common clock supply network and each intermediary clock supply network are
comprised of a plurality of coupling lines, each of said plurality of
coupling lines being resistance matched having substantially similar
length and width.
5. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 4 wherein said
plurality of coupling lines of said common clock supply network and said
intermediary clock supply network are capacitance matched and disposed
within said power cell means.
6. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 1 wherein said
integrated circuit is a microprocessor device having a first overall
dimension and wherein widths associated with said plurality of feeder
means do not sum in excess of 5 percent of said first overall dimension of
said microprocessor device.
7. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 1 wherein said
plurality of synchronous clock signals supplied over said feeder means do
not contain a clock skew in excess of 100 picoseconds associated with any
point of any particular feeder means.
8. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 1 further
comprising a plurality of alignment lines for coupling select circuit
components to selected feeder means of said plurality of feeder means,
said plurality of alignment lines disposed substantially perpendicular to
said plurality of feeder means.
9. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 1 wherein said
plurality of feeder means are composed of an upper level metal M.sub.4.
10. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 1 wherein said
plurality of global clock driver means are disposed in a substantially
uniform pattern along two opposing edges of said periphery of said
integrated circuit.
11. In a microprocessor device having a plurality of circuit components, an
apparatus for supplying a plurality of synchronous clock signals to said
plurality of circuit components, said apparatus comprising:
a plurality of global clock drivers uniformly disposed along a periphery of
said microprocessor device, said plurality of global clock drivers for
generating a plurality of synchronous clock signals, wherein said
plurality of global clock drivers are disposed in a substantially uniform
pattern along two opposing edges of said periphery of said microprocessor
device;
a plurality of feeder lines, each feeder line coupled to a global clock
driver, said plurality of feeder lines for supplying said plurality of
synchronous clock signals from said periphery of said microprocessor
device to said plurality of circuit components of said microprocessor
device;
power cell means disposed along edges of said microprocessor device, said
power cell means for providing spatial areas within said microprocessor
device for coupling said microprocessor device to a power source and
wherein said plurality of global clock drivers are disposed within said
power cell means; and
an intermediate driver stage comprising a plurality of intermediary clock
drivers for supplying clock signals to said plurality of global clock
drivers, each of said intermediary clock drivers for supplying a set of
global clock drivers via an intermediary clock supply network.
12. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components of a microprocessor device according
to claim 11 further comprising:
a clock generator circuit for generating a reference clock signal; and
a common clock driver stage comprising a common clock driver for supplying
said reference clock signal to said plurality of intermediary clock
drivers via a common clock supply network.
13. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components of a microprocessor device according
to claim 12 wherein said common clock supply network and each intermediary
clock supply network are comprised of a plurality of coupling lines, each
of said plurality of coupling lines being resistance matched having
substantially similar length and width and wherein said common clock
supply network is disposed within a power supply ring of said
microprocessor device.
14. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components of a microprocessor device according
to claim 11 wherein said plurality of global clock drivers, said plurality
of intermediary global drivers and said intermediary clock supply network
are all disposed within a spatial area of said power cell means of said
microprocessor.
15. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components of a microprocessor device according
to claim 11 wherein said microprocessor device has a first overall
dimension and wherein widths associated with said plurality of feeder
lines do not sum in excess of 5 percent of said first overall dimension of
said microprocessor device and wherein said plurality of synchronous clock
signals generated over said feeder lines do not contain a clock skew in
excess of 100 picoseconds associated with any point of any particular
feeder line.
16. In an integrated circuit having a plurality of circuit components, an
apparatus for supplying a plurality of synchronous clock signals to said
plurality of circuit components, said apparatus comprising:
a plurality of global clock drivers uniformly disposed along a periphery of
said integrated circuit, said plurality of global clock drivers for
generating a plurality of synchronous clock signals, wherein said
plurality of global clock drivers are disposed in a substantially uniform
pattern along two opposing edges of said periphery of said integrated
circuit;
a plurality of feeder lines, each feeder line coupled to a global clock
driver, said plurality of feeder lines for supplying said plurality of
synchronous clock signals from said periphery of said integrated circuit
to said plurality of circuit components of said integrated circuit; and
power cells disposed along edges of said integrated circuit for providing
spatial areas within said integrated circuit, for coupling said integrated
circuit to a power source, said global clock drivers disposed within said
power cells of said integrated circuit.
17. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 16 further
comprising:
a plurality of intermediary clock drivers for supplying clock signals to
said plurality of global clock drivers, each of said intermediary clock
drivers for supplying a set of global clock drivers via an intermediary
clock supply network; and
a common clock driver for supplying a clock signal generated by said clock
generator circuit to said plurality of intermediary clock drivers via a
common clock supply network.
18. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 17 wherein said
common clock supply network and each intermediary clock supply network are
comprised of a plurality of coupling lines, each of said plurality of
coupling lines being resistance matched having substantially similar
length and width.
19. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 16 wherein said
integrated circuit is a processor device having a first overall dimension
and wherein widths associated with said plurality of feeder lines do not
sum in excess of 5 percent of said first overall dimension of said
microprocessor device.
20. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 16 wherein said
plurality of synchronous clock signals generated over said feeder lines do
not contain a clock skew in excess of 100 picoseconds associated with any
point of any particular feeder line.
21. An apparatus for supplying a plurality of synchronous clock signals to
said plurality of circuit components according to claim 16 wherein said
plurality of feeder lines are composed of an upper level metal M.sub.4.
22. A computer system comprising:
bus means for coupling system components, display means coupled to said bus
means, memory means coupled to said bus means, information storage means
coupled to said bus means and microprocessor means having a distributed
clock network, said microprocessor means coupled to said bus means, said
microprocessor means further comprising:
a plurality of circuit components;
a plurality of global clock driver means uniformly disposed along a
periphery of said microprocessor means, said plurality of global clock
driver means for generating a plurality of synchronous clock signals;
a plurality of feeder means, each feeder means coupled to a global clock
driver means, said plurality of feeder means for supplying said plurality
of synchronous clock signals from said periphery of said microprocessor
means to said plurality of circuit components of said microprocessor
means; and
power cell means disposed along edges of said microprocessor means for
providing spatial areas within said microprocessor means, for coupling
said microprocessor means to a power source, said plurality of global
clock driver means disposed within said power cell means of said
microprocessor means.
23. A computer system in accordance with claim 22 further comprising:
a plurality of intermediary clock drivers for supplying clock signals to
said plurality of global clock driver means, each of said intermediary
clock drivers for supplying a set of global clock driver means via an
intermediary clock supply network.
24. A computer system in accordance with claim 23 further comprising:
a common clock driver for supplying a clock signal generated by said clock
generator circuit to said plurality of intermediary clock drivers via a
common clock supply network.
25. A computer system in accordance with claim 24 wherein said common clock
supply network and each intermediary clock supply network are comprised of
a plurality of coupling lines, each of said plurality of coupling lines
being resistance matched having substantially similar length and width.
26. A computer system in accordance with claim 25 wherein said plurality of
coupling lines of said common clock supply network and said intermediary
clock supply network being capacitance matched and are disposed within
said power cell means.
27. A computer system in accordance with claim 24 wherein said common clock
supply network is disposed along a power supply ring of said
microprocessor means.
28. A computer system in accordance with claim 22 wherein said
microprocessor means includes an overall dimension and wherein widths
associated with said plurality of feeder means do not sum in excess of 5
percent of said overall dimension of said microprocessor device.
29. A computer system in accordance with claim 22 wherein said plurality of
synchronous clock signals generated over said feeder means do not contain
a clock skew in excess of 100 picoseconds associated with any point of any
particular feeder means.
30. A computer system in accordance with claim 22 further comprising a
plurality of alignment lines for coupling selected circuit components to
selected feeder means of said plurality of feeder means, said plurality of
alignment lines disposed perpendicular to said plurality of feeder means.
31. A computer system in accordance with claim 22 wherein said plurality of
feeder means are composed of an upper level metal M.sub.4.
32. A computer system in accordance with claim 22 wherein said plurality of
global clock driver means are disposed in a substantially uniform pattern
along two opposing edges of said periphery of said microprocessor means.
33. In an integrated circuit having a plurality of circuit components and a
clock generator circuit, a method for supplying a plurality of synchronous
clock signals to said plurality of circuit components, said method
comprising the steps of:
generating a common clock signal;
generating a plurality of synchronous clock signals from a plurality of
global clock driver means uniformly disposed along a periphery of said
integrated circuit;
disposing power cell means along edges of said integrated circuit for
providing spatial areas within said integrated circuit, for coupling said
integrated circuit to a power source, said global clock driver means
disposed within said power cell means of said integrated circuit;
supplying said plurality of synchronous clock signals from said periphery
of said integrated circuit to said plurality of circuit components of said
integrated circuit through a plurality of feeder means, each feeder means
coupled to a global clock driver means; and
supplying said common clock signal to said plurality of global clock driver
means.
34. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 33 wherein said step of
supplying said common clock signal to said plurality of global clock
driver means further comprises the steps of:
supplying clock signals to said plurality of global clock driver means via
a plurality of intermediary clock drivers, each of said intermediary clock
drivers for supplying a set of global clock driver means via an
intermediary clock supply network; and
supplying said common clock signal to said intermediary clock drivers via a
common clock supply network.
35. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 34 wherein said common
clock supply network and each intermediary clock supply network are
comprised of a plurality of coupling lines, each of said plurality of
coupling lines having substantially similar length and width such that
they are resistance matched.
36. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 35 further comprising
the step of disposing said plurality of coupling lines of said common
clock supply network and said intermediary clock supply network within
said power cell means so that they are capacitance matched.
37. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 34 wherein said
integrated circuit is a microprocessor device having a first overall
dimension and wherein widths associated with said plurality of feeder
means do not sum in excess of 5 percent of said first overall dimension of
said microprocessor device.
38. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 34 wherein said
plurality of synchronous clock signals generated over said feeder means do
not contain a clock skew in excess of 100 picoseconds associated with any
point of any particular feeder means.
39. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 34 further comprising
the step of coupling said plurality of circuit components to selected
feeder means of said plurality of feeder means via a plurality of
alignment lines, said plurality of alignment lines disposed perpendicular
to said plurality of feeder means.
40. A method for supplying a plurality of synchronous clock signals to said
plurality of circuit components according to claim 34 wherein said step of
generating a plurality of synchronous clock signals comprises the step of
disposing said global clock driver means in a substantially uniform
pattern along two opposing edges of said periphery of said integrated
circuit. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the field of microprocessor architecture
and layout. Specifically, the present invention relates to the technology
of clock signal distribution throughout a microprocessor device.
(2) Prior Art
Components of an integrated circuit operate based on the timing and pulsing
of clock signals which provide a reference point or activation signal for
circuit activity and processing. The clock signal also provides a timing
or alignment reference which different circuits adopt when stepping
through their respective processing tasks. It is important that the
clocking signals be predictable and not delayed such that processing and
execution by circuit components are accomplished in synchronization.
Microprocessor integrated circuit devices utilize a system clock which
provides timing and pulsing to drive the various elements and processing
of the microprocessor. It is vital to the operation of a microprocessor
that the system clock be supplied uniformly to all components of the
microprocessor with minimal clock skew and minimal clock delay. Each
system component should receive the same clock signal, in synchronization,
with all other components.
Throughout the following discussions, reference is made to clock delay and
clock skew. Clock delay refers to the timing delay between a clock signal
within an integrated circuit to the system clock. Clock skew, on the other
hand, refers to the variations between clock delays associated with
various points of an integrated circuit. While it may be physically
impossible to totally eliminate clock delay, it is not impossible to match
this delay across the entire IC and thus eliminate clock skew to various
circuit components. To this extent, two points within an integrated
circuit may have equal clock delays, but no clock skew between them.
Therefore, it would be advantageous to match clock delays for all circuit
components and thus eliminate clock skew within an IC; the present
invention offers such a solution.
As microprocessor integrated devices use faster and faster clock speeds,
variations in the topology of the microprocessor device may introduce
delay or error factors within the metal lines that carry and propagate the
clock signal. As the clock signal pulse becomes narrower, these clock
signal variations become significant in modern microprocessor design.
These factors contribute to propagation errors within the clock signals
and will act to delay the clock signals as they are distributed to the
various components of the microprocessor. Resistance within the clock line
and capacitance on the clock line will create RC skews as the clock signal
propagates. Also, other discontinuities within the circuit topology of the
microprocessor will add to the propagation error of the clock signal, such
as differences in thickness of the components that surround the clock line
which introduce variable dielectric values to the signal lines (such as
dielectric thickness variations within the insulating layers). These
dielectric variations will contribute to the capacitance of the clock
signal lines. What is desired is a scheme to provide all components of the
microprocessor with a synchronized and identical clock signal even in
microprocessor architecture having complex topologies having complex
dielectric variations across them.
Several prior art methods have been implemented in order to provide
components of a microprocessor integrated device with a clock. FIG. 1A
illustrates one such prior art method wherein a signal driver is used to
supply a clock signal to all of the components of a microprocessor device.
A microprocessor integrated circuit device 10 is illustrated such that its
top metal processing layer is facing upward. Within this top metal layer
is a connection point from a clock driver 12 which drives the
microprocessor clock. The system clock is usually input from outside the
chip by an oscillator network or circuit. The clock oscillator is then
driven by the clock driver 12. The driver is coupled to a very wide line
14a which is then coupled throughout the microprocessor device in a tree
or branch scheme as shown. Different components of the microprocessor will
then couple to the branching structure at different points as needed to
gain access to the supplied clock signal. As shown, the branchings of the
tree 14b and 14c are less in width than the initial line 14a which is
coupled directly to the driver 12. The line coupled directly to the driver
must be wider in order to carry the entire clock signal throughout the
components of the microprocessor device 10.
Because a single clock driver 12 is utilized by the prior art method of
FIG. 1A to supply the entire chip, it must be a very high power driver,
but this is not the only reason why this prior art technique utilizes a
high current driver. It is desired to reduce the resistance of the line
14a by increasing its width to reduce to total RC component of the line.
Resistance within the clock driver lines 14a, 14b, and 14c, is a function
of the length of the signal line between a point and the driver. Signal
skew is a function of the resistance and capacitance (RC) of the line.
When the signal lines are relatively small, the proportional increase in
line capacitance will not equal the proportional decrease in resistance
upon widening the line 14a, therefore, the overall RC product will
decrease upon widening 14a. However, by decreasing the resistance, the
driver size must increase to supply additional current to the clock line.
An increase of power is used to decrease clock skew. This high power
driver may create an excessive amount of noise associated with the clock
signal. Under this system, the signal lines 14a are widened to lower
resistance, which requires relatively higher power clock drivers; all of
the above done in an effort to reduce the signal skew.
Because the length of the signal lines are long in the prior art method of
FIG. 1A, the skew associated with the clock signal of this method is very
great and not predictable from component to component. In larger
microprocessors, this skew can approach 1.0 nanosecond in degree. This is
an unacceptable level of skew in modern computers that operate at speeds
well in excess of 50 megahertz. Also, the variable width of the signal
line (i.e., from very wide at 14a to smaller at 14c) contribute to more
variable skew in the signal delivered throughout the microprocessor 10
depending on the length of the signal line. Therefore, this prior art
technique requires a high power (and therefore noisy) clock driver and has
a corresponding large amount of variable skew associated with the clock
signal. What is needed is a clock distribution system that reduces the
amount of skew within the clock signal supplied throughout the
microprocessor without relying on high power drivers. The present
invention offers such capability.
FIG. 1B illustrates another prior art clock supply implementation that
utilizes several different current drivers 17a-17d which each receive the
same clock signal input. The outputs of each driver are then coupled to a
separate circuit block within the microprocessor. For example, driver 17a
is coupled to block 15a, and 17b to block 15b and so on such that each
block 15a-15d receives its clock signal by a separate driver of 17a-17d
respectively. The widths of each of these lines are controlled such that
they are constant. Also the length of each line is controlled such that
each line has the same length. Since the components 15a-15d are located at
different distances to the clock generators, the lines 18, 19, 20, and 21
are doubled back in some areas to maintain the constant distance. For
example line 18 has a few double back running lines so that line 18 will
be equal in length to line 19, etc. The line 20 has no doubling back and
will determine the length for all the other clock lines. In so doing, the
microprocessor device 10 of this design will deliver a clock signal to
each component. This system is able to utilize lower power drivers 17a-17d
because the lines are smaller and there are more separate lines to
distribute the clock signal.
In theory this prior art design of FIG. 1B is workable but it offers
several disadvantages. First, it may not be possible to maintain constant
width for each of the lines 18-21 over the entire signal line from the
clock drivers to the components. Also, each of the lines will cross over
and under different circuit topologies of the microprocessor which will
alter the effective capacitance of the overall line. Uncontrollable
differences in the manufacture of the signal lines in the processing
stages of the microprocessor will effect the thickness of the dielectric
of these lines up to 20 percent which will effect the capacitance of these
lines and therefore contribute to topological mismatch. Although these
variations may exist within all designs, this prior art system does not
account for them in the most advantageous manner.
In summary, it may not be possible to match the capacitance values and
resistance values of the clock signal lines over the entire topology of
the integrated microprocessor device 10. These variations in the
resistance and capacitance of the clock signal lines 18-21 will create
unwanted signal skew within the clock signals supplied to the components
of the microprocessor. Therefore, differences in dielectric values and
processing irregularities may render this prior art method unachievable.
What is desired is a system that can supply a relatively constant and
predictable clock signal to all of the components of a microprocessor
regardless of topology and processing variations throughout the
microprocessor device. The present invention offers such capability.
A third prior art design is illustrated in FIG. 1C. With this system, many
clock drivers 21 are situated in the center strip of the microprocessor 10
and supply clock signals outward horizontally to the fight and left sides
across the topology of the chip utilizing a horizontal signal line for
each driver. The drivers 21 are distributed across the entire dimension of
the microprocessor. The maximum length of each horizontal driver line is
half the length of the microprocessor chip. Various circuit components 24
and 25 will tap into these clock signals where the drivers supply the
illustrated horizontal clock signal lines. Each of the clock drivers are
supplied with power via a power line 23 which is coupled to the outer
portion of the chip where the power pads 28 are located. Each of the
drivers 21 must be coupled to power. The initial clock signal is fed to
the drivers 21 via the center strip of the microprocessor device 10. This
prior art method is a distributed clock scheme.
The prior art method of FIG. 1C is disadvantageous because the clock
drivers 21, and associated logic to initially bring the clocking signal to
the drivers, will consume excessive amounts of circuit space within the
center strip of the microprocessor. It would be advantageous to utilize
this space (real estate) of the microprocessor for purposes other than
just a clock supply function. Furthermore, because the drivers 21 are
located far away from the power pads 28 of the chip (located on the
edges), large power supply lines 23 must be incorporated into this design
to supply the drivers 21 with power. The resistance associated with these
high power lines create an excessive amount of noise within the overall
microprocessor that becomes unacceptable at high processor operating
speeds (more resistance yields more noise associated with the power line
due to IR noise). Therefore, what is needed is a system for supplying a
synchronized clock signal throughout a microprocessor that does not
consume valuable circuit space (especially circuit space within the mid
sections of the topology which is regarded at a premium) and also that
does not generate an excessive amount of noise within the microprocessor.
The present invention offers such advantageous functions.
Furthermore, regarding the clock distribution system, it would be
advantageous to be able to interrupt the clock signal that supplies the
microprocessor device. In certain applications, especially within laptop
systems, it is advantageous to conserve power by reducing the clock pulses
supplied to the microprocessor. Prior art systems have been developed that
control the clock signal that supplies the entire microprocessor but not
individual components within the microprocessor. However, it would be
advantageous to be able to selectively control the application of the
clock signal to various components of the microprocessor independently. It
would be advantageous to be able to selectively interrupt the clock signal
to some microprocessor components while allowing others to operate
normally so as to perform power management functions within the
microprocessor device. The present invention allows such capability.
Accordingly, it is an object of the present invention to offer a clock
supply system to provide a synchronous clock signal throughout the
components of a integrated microprocessor device with minimal signal skew
and distortion. It is further an object of the present invention to
provide a distributed clock system that does not consume valuable circuit
space of the microprocessor that can be used for other advantageous
purposes. It is further an object of the present invention to provide the
above functions in a system that does not utilize relatively long high
power lines and therefore that does not generate an excessive amount of
signal noise associated with the clock signal. It is also a function of
the present invention to provide the above in a system wherein the clock
driver units of the distributed system can be individually disabled so
that clocking signals can be temporarily suspended to individual circuit
components of the microprocessor device for power management functions.
These and other objects of the present invention not specifically
mentioned herein will become clear upon review of the discussion of the
present invention to follow.
SUMMARY OF THE INVENTION
Embodiments of the present invention include a clock distribution system
and clock interrupt system for an integrated circuit device. Ignoring
effects associated with the matched stages, the present invention includes
a clock distribution and interrupt system for providing clock signals with
less than 100 picoseconds of skew to various components of an integrated
circuit device. Considering the effects of the matched input stages, the
above value may approach 300 picoseconds due to processing imperfections
and imperfections associated with the matching input stages. The present
invention utilizes several stages of drivers to evenly supply the
distributed clock signals and each stage has RC matched input lines. The
present invention advantageously locates the matched stages and clock
drivers within the power supply ring of the integrated circuit located on
the periphery of the microprocessor topology. This is done in order to
better predict the topology surrounding these lines to match the
capacitance of these lines. Further, this metal level offers a larger
width dimension line (since as a top layer it may be thicker) having less
resistance per unit area and also generally avoids spatial competition
with other IC components and circuitry. The present invention additionally
offers the capability of selectively powering down various components
within the integrated device with a power management unit and enable
network that is included within the clock distribution system.
Specifically, an embodiment of the present invention is described in an
integrated circuit having a plurality of circuit components and a clock
generator circuit, an apparatus for supplying a plurality of synchronous
clock signals to the plurality of circuit components, the plurality of
synchronous clock signals referenced from the clock generator circuit, the
apparatus including: a plurality of global clock driver means uniformly
disposed along a periphery of the integrated circuit, the plurality of
global clock driver means for generating a plurality of synchronous clock
signals; and a plurality of feeder means, each feeder means coupled to a
global clock driver means, the plurality of feeder means for supplying the
plurality of synchronous clock signals from the periphery of the
integrated circuit to the plurality of circuit components of the
integrated circuit. An embodiment of the present invention includes the
above and further includes power cell means disposed along edges of the
integrated circuit, the power cell means for providing spatial areas
within the integrated circuit for coupling the integrated circuit to a
power source and wherein the global clock driver means are disposed within
the power cell means of the integrated circuit.
An embodiment of the present invention is described in a microprocessor
having a plurality of circuit components, an apparatus for power
management of the microprocessor, the apparatus including: a plurality of
global clock driver means disposed within the microprocessor, the
plurality of global clock driver means for generating a plurality of
synchronous clock signals; a plurality of feeder means, each feeder means
coupled to a global clock driver means, the plurality of feeder means for
supplying individual circuit components of the microprocessor with clock
signals; disable means disposed within each global clock driver means for
interrupting the clock signals supplied to the individual circuit
components; and power management means coupled to the disable means and
coupled to the microprocessor for controlling the disable means to
selectively interrupt or restore the synchronous clock signal to various
circuit components of the microprocessor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A illustrates a prior art system of clock signal distribution using
only a single high power signal driver.
FIG. 1B illustrates a prior art system of clock distribution that utilizes
a separate and matched signal line for each circuit component.
FIG. 1C illustrates another prior art system of clock distribution using a
distributed network driver array that generates noise and consumes
microprocessor circuit space.
FIG. 2 is an illustration of an integrated circuit device of the present
invention utilizing a clock distribution network of two rows of global
drivers and associated feeder lines located on opposing edges of the
integrated circuit device that feed inward.
FIG. 3 is an illustration of the present invention clock distribution
network showing the matched stages associated with the intermediary
drivers and global drivers.
FIG. 4 illustrates the clock distribution network of the present invention
and illustrated in detail the alignment lines used to couple the global
drivers to the integrated circuit components.
FIG. 5 is an illustration of a global driver and shows in detail the enable
and disable functions of the global driver.
FIG. 6A is an illustration in detail of the power management functions of
the present invention including the enable network coupled to the global
drivers.
FIG. 6B is an illustration of a microprocessor of the present invention and
a full clock distribution network of the present invention including the
60 global drivers and the power management network and unit.
FIG. 7 is a flow diagram of the present invention illustrating the major
process steps employed by the present invention to perform power
management functions.
FIG. 8 illustrates a general purpose computer system employing the
integrated circuit of the present invention.
FIG. 9 illustrates the power supply pads utilized by the present invention
clock supply network.
DETAILED DESCRIPTION OF THE INVENTION
The present invention includes an apparatus and method for distributing a
clock signal throughout the components of a microprocessor device such
that there is a predictable and minimal amount of signal skew (less than
100 picoseconds) at any given supply point of the clock signal. Using the
distribution system of the present invention, the clock signal will reach
each component of the microprocessor at relatively the same time
irrespective of the particular tap point selected by the component. Along
the outer edges (periphery) of the microprocessor topology, the clock
drivers are located which feed clock signals inward to the center or
interior portions of the microprocessor. The clock signal drivers are
situated in the surrounding space of a power pad of the microprocessor.
These surrounding spaces of the power pad are typically otherwise unused
by the microprocessor and therefore the signal drivers of the present
invention do not waste otherwise usable circuit space. Also, because the
signal drivers are located on the edge of the integrated circuit
microprocessor device, they are near the power supply pins. Therefore, the
resistance within the lines that power the clock drivers is very low
because the power supply lines are short.
In addition, the present invention includes, for each clock driver, an
enable function so that each clock driver can be disabled to temporarily
interrupt the clock signal supply to various components of the
microprocessor. This can be done to selectively power down certain
components of the microprocessor during power management functions. This
function is especially useful in microprocessors used in laptop computer
systems or battery powered systems.
In the following detailed description of the present invention numerous
specific details are set forth in order to provide a thorough
understanding of the present invention. However, it will be obvious to one
skilled in the art that the present invention may be practiced without
these specific details. In other instances well known methods, components,
systems and electronics have not been described in detail as not to
unnecessarily obscure the present invention. Furthermore, it is noted that
components of the following figures of the present invention are not
necessarily drawn to scale spatially and the components of the present
invention are illustrated within these figures for purposes of
illustration and clarity rather than purely for purposes of scale.
In general, computer systems 130 used by the preferred embodiment of the
present invention as illustrated in block diagram format in FIG. 8,
comprise a bus 100 for communicating information, a central processor 101
coupled with the bus for processing information and instructions, a random
access memory 102 coupled with the bus 100 for storing information and
instructions for the central processor 101, a read only memory 103 coupled
with the bus 100 for storing static information and instructions for the
processor 101, a data storage device 104 such as a magnetic or optical
disk and disk drive coupled with the bus 100 for storing information and
instructions, a display device 105 coupled to the bus 100 for displaying
information to the computer user, an alphanumeric input device 106
including alphanumeric and function keys coupled to the bus 100 for
communicating information and command selections to the central processor
101, a cursor control device 107 coupled to the bus for communicating user
input information and command selections to the central processor 101, and
a signal generating device 108 coupled to the bus 100 for communicating
command selections to the processor 101. Coupled with the microprocessor
of the present invention is a crystal oscillator 110 that is used along
with other well known clock generation circuitry in order to generate a
system clock which is supplied to the microprocessor. A common clock
driver 301 (not shown in FIG. 8) is coupled to receive and amplify the
clock signal generated by the oscillator circuit 110. It is appreciated
that embodiments of the present invention may utilize a phase locked loop
(PLL) circuit which is coupled between the circuit 110 and driver 301;
such a PLL is utilized in the clock supply functions of the present
invention to reduce actual clock signal delay.
The display device 105 of FIG. 8 utilized with the computer system of the
present invention may be a liquid crystal device, cathode ray tube, or
other display device suitable for creating graphic images and alphanumeric
characters recognizable to the user. The cursor control device 107 allows
the computer user to dynamically signal the two dimensional movement of a
visible cursor symbol (pointer) on a display screen of the display | | |
