 |
Description  |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device
which takes in external signals including an external control signal, an
address signal, write data and the like in synchronization with a clock
signal formed of a series of pulses, and more particularly, it relates to
a structure for easily making a test for deciding
defectiveness/nondefectiveness of memory cells at a high speed.
2. Description of the Background Art
The operating speed of a microprocessor (MPU) has been increased in recent
years. On the other hand, a dynamic random access memory (hereinafter
referred to as DRAM) which is employed as a main memory cannot follow the
MPU in operating speed although its operation has also been speeded up.
Thus, it is frequently pointed out that access and cycle times of such a
DRAM bottleneck the operation of the overall system, to deteriorate its
performance.
In order to improve performance of such a system, frequently employed is a
technique of arranging a high-speed memory called a cache memory, which is
formed of a high-speed static random access memory (hereinafter referred
to as SRAM) between a DRAM and an MPU. This high-speed cache memory is
adapted to store frequently-used data, and accessed when the cache stores
data required by the MPU. The DRAM is accessed only when the cache memory
stores no data required by the MPU. Due to the high-speed cache memory
storing frequently-used data, it is possible to extremely reduce frequency
of access to the DRAM, thereby eliminating influences by the access and
cycle times of the DRAM and improving performance of the system.
However, the SRAM is so high-priced, as compared with the DRAM, that the
method employing a cache memory is unsuitable for a relatively low-priced
device such as a personal computer. Thus, awaited is improvement in
performance of such a system with a low-priced DRAM.
A synchronous DRAM (hereinafter referred to as SDRAM) which operates in
synchronization with a high-speed external clock signal such as a system
clock signal, for example, is proposed at present as one of DRAMs
operating at high speeds. JEDEC (Joint Electron Device Engineering
Council) of the U.S.A. employs such an SDRAM as a main memory for a
high-speed MPU, and is now in operation for standardizing the
specification thereof. While the standard specification is not yet
clarified in detail, the following structure is proposed at present:
(1) The SDRAM is synchronized with a clock signal having a cycle of 10 to
15 ns (nanoseconds).
(2) The first data is randomly accessed with 4 to 6 clock delay after a row
address signal is inputted. Thereafter data of continuous addresses can be
accessed every clock.
(3) Circuits provided in a chip are pipeline-driven while serial
input/output buffers are provided in a data input/output portion to reduce
an access time.
However, the aforementioned structure is a mere proposal, and no means for
implementing this structure is described specifically.
On the other hand, another proposal has also been made as to provision of a
test mode for deciding defectiveness/nondefectiveness of the SDRAM. As to
a method of and a structure for carrying out such a test, however, no
definition is made specifically.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an SDRAM which can
efficiently make a test.
Another object of the present invention is to provide a semiconductor
memory device which can efficiently make a test in a short time.
Further object of the present invention is to provide an SDRAM in which a
plurality of memory cells are simultaneously tested without additional
complicated circuit arrangement.
An SDRAM according to the present invention includes a data output
terminal, read circuitry for simultaneously reading data from a
predetermined plurality of memory cells in response to a read mode command
for successively transferring the data to the data output terminal, and
compression means for carrying out prescribed arithmetic operations on the
data which are read from the plurality of memory cells by the read
circuitry in response to a test mode command for compressing the same to
1-bit data and outputting the same.
1-bit compression may be executed on respective IO pins. Alternatively,
test results of all IO pins may be compressed to 1-bit data, to be
outputted from a particular IO pin.
According to the present invention, data which are read from a plurality of
simultaneously selected memory cells are compressed to 1-bit data by the
compression circuitry to be outputted. Thus, it is possible to
simultaneously test a plurality of memory cells, thereby reducing the test
time.
The foregoing and other objects, features, aspects and advantages of the
present invention will become more apparent from the following detailed
description of the present invention when taken in conjunction with the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a chip layout of an SDRAM to which the present invention
is applied;
FIG. 2 illustrates arrangement of a memory array of the SDRAM shown in FIG.
1;
FIG. 3 illustrates correspondence between a single column selection line
and data input/output terminals;
FIG. 4 illustrates internal structures of memory cell array of the SDRAM to
which the present invention is applied;
FIG. 5 is a block diagram showing a structure of control signal generation
circuitry of the SDRAM to which the present invention is applied;
FIG. 6 schematically illustrates a structure of a first control signal
generation circuit shown in FIG. 5;
FIG. 7 shows relation between states of external control signals and
correspondingly specified operation modes in the SDRAM to which the
present invention is applied;
FIG. 8 illustrates structures of data read circuitry of the SDRAM to which
the present invention is applied;
FIG. 9 illustrates an exemplary structure of a read register shown in FIG.
8;
FIG. 10 is a signal waveform diagram showing operations of the read
register shown in FIG. 9;
FIG. 11 is a timing chart showing operations of data read circuitry shown
in FIG. 8;
FIG. 12 illustrates states of the external control signals in data reading
of the SDRAM shown in FIG. 8;
FIG. 13 illustrates a structure of data write circuitry of the SDRAM to
which the present invention is applied;
FIG. 14 illustrates exemplary structures of a write register and a write
circuit shown in FIG. 13;
FIG. 15 is a signal waveform diagram showing operations of the circuit
shown in FIG. 14;
FIG. 16 illustrates states of the external control signals in operation of
the write circuit circuitry shown in FIG. 13;
FIG. 17 illustrates a structure of data input/output circuitry in an SDRAM
according to an embodiment of the present invention;
FIG. 18 is a timing chart showing a data read operation of the SDRAM shown
in FIG. 17 in a test mode;
FIG. 19 is a timing chart showing a data write operation of the SDRAM shown
in FIG. 17 in a test mode;
FIG. 20 illustrates an exemplary structure of a wrap address generation
circuit shown in FIG. 17;
FIG. 21 illustrates an exemplary structure of a write control circuit shown
in FIG. 17;
FIG. 22 illustrates a structure of a compression circuit shown in FIG. 17;
FIG. 23 is a signal waveform diagram showing operations of the compression
circuit shown in FIG. 22;
FIG. 24 illustrates states of internal signals and current states of
degeneration data bits in operation of the compression circuit shown in
FIG. 22;
FIG. 25 illustrates an arrangement for outputting test data in the SDRAM
according to the present invention;
FIG. 26 illustrates another structure of a data compression mode of the
SDRAM according to the present invention;
FIG. 27 illustrates a structure of a second compression circuit shown in
FIG. 26;
FIG. 28 illustrates another structure of the second compression circuit
shown in FIG. 26;
FIG. 29 illustrates still another structure of the second compression
circuit shown in FIG. 26;
FIG. 30 illustrates an exemplary output scheme of compressed data bits
outputted from the second compression circuit;
FIG. 31 illustrates another exemplary output scheme of the compressed data
bits outputted from the second compression circuit;
FIG. 32 illustrates still another exemplary output scheme of the compressed
data bits outputted from the second compression circuit;
FIG. 33 illustrates another structure of the SDRAM according to the present
invention;
FIG. 34 illustrates an arrangement for writing test data in the SDRAM
according to the present invention;
FIG. 35 illustrates another writing arrangement for test data in the SDRAM
according to the present invention;
FIG. 36 illustrates a structure of test circuitry of an SDRAM according to
still another embodiment of the present invention;
FIG. 37 illustrates an exemplary structure of a selective activation
circuit for bringing both banks into activated states in a test mode
operation;
FIG. 38 is a signal waveform diagram showing operations of the selective
activation circuit shown in FIG. 37 in a test mode; and
FIG. 39 is a signal waveform diagram showing operations of the selective
activation circuit shown in FIG. 37 in an ordinary operation mode.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[Chip Layout]
FIG. 1 illustrates a chip layout of an SDRAM to which the present invention
is applied. FIG. 1 shows a chip layout of a 16-megabit SDRAM having a 2M
word by 8 bit structure. This SDRAM includes four memory mats MM1 to MM4,
each having 4-megabit storage capacity. Each of the memory mats MM1 to MM4
includes 16 memory arrays MA1 to MA16 each having 256-k bit storage
capacity.
Row decoders RD1 to RD4 are arranged on respective one sides of the memory
mats MM1 to MM4 along a chip longer side.
Further, column decoders CD1 to CD4 are arranged on chip center sides of
the memory mats MM1 to MM4 along chip shorter side respectively. Outputs
of the column decoders CD (symbol CD is adapted to genericly indicate the
column decoders CD1 to CD4) are provided onto column selection lines CSL
extending across the respective arrays of the corresponding memory mat MM
(symbol MM genericly indicates the memory mats MM1 to MM4). Each column
selection line CSL simultaneously brings eight bit line pairs BLP into a
selected state.
Global IO line pairs GIO for transmitting internal data are arranged across
the respective arrays along the longer sides of the memory mat MM.
The respective memory mats MM1 to MM4 are further provided on the chip
center sides thereof with input/output circuits PW1 to PW4, which are
formed by preamplifiers PA for amplifying data of selected memory cells
and write buffers WB for transmitting write data to the selected memory
cells respectively.
Peripheral circuit PH including circuitry for generating address and
control signals is arranged on the chip central portion.
The SDRAM shown in FIG. 1 comprises two banks #1 and #2 which can carry out
precharge operations and activating operations independently of each
other. The bank #1 includes the memory mats ME1 and MM2 while the bank #2
includes the memory mats MM3 and MM4, for example.
Each of the memory mats MM1 to MM4 includes two array blocks each having
2-megabit storage capacity. One of the array blocks having 2-megabit
storage capacity is formed by the memory arrays MA1 to MA8, while the
other 2-megabit array block is formed by the memory arrays MA9 to MA16.
A single memory array is selected at the maximum in each array block. Four
memory arrays are simultaneously activated. Referring to FIG. 1, the
memory arrays MA1 and MA9 in the memory mats MM3 and MM4 are activated. In
other words, a single memory array is selected from each array block of
each memory mat in the selected bank #1 or #2.
On the other hand, eight column selection lines CSL are simultaneously
selected. Each column selection line CSL selects eight pairs of bit lines.
Thus, 8.times.8=64 bit memory cells are selected at the same time.
The input/output circuit PW (generic indicating the input/output circuits
PW1 to PW4) is employed in common for the respective memory arrays of the
corresponding memory mat MM. Each input/output circuit PW includes 32
preamplifier PA and 32 write buffers WB. Namely, the overall SDRAM
includes 128 preamplifiers PA and 128 write buffers WB.
FIG. 2 specifically illustrates arrangement of IO lines in the SDRAM shown
in FIG. 1. FIG. 2 shows two 2-megabit memory arrays MSA1 and MSA2. The
2-megabit memory array MSA1 is a 2-megabit array block which is arranged
in a position away from the chip central portion, while the other memory
array MSA2 is a 2-megabit array block which is close to the chip central
portion.
Each of the 2-megabit memory arrays MSA1 and MSA2 includes 64 32-k bit
memory arrays MK arranged in 8 rows and 8 columns. Each 2-megabit memory
array MSA (this symbol genericly indicates the memory arrays MSA1 and
MSA2) is divided into four array groups AG1, AG2, AG3 and AG4 along an
extending direction of word lines WL. Word line shunt regions WS are
provided between the 32-k bit memory arrays MK which are adjacent to each
other along the word lines WL.
In an ordinary DRAM, low-resistance metal wires of aluminum or the like are
arranged in parallel with word lines WL of polysilicon in order to reduce
resistances of the word lines WL, so that the former are electrically
connected with the latter at prescribed intervals. Regions for connecting
the polysilicon word lines and the low-resistance metal wires are called
word line shunt regions. In general, such low-resistance metal wires are
formed above the bit lines, and the word lines are formed under the bit
lines. Therefore, the word line shunt regions are provided in regions
provided-with no bit lines, i.e., regions provided with no memory cells,
i.e., regions between the memory arrays.
The global IO line pairs GI0 are arranged in the word line shunt regions
WS. In the 2-megabit memory array MSA2 which is close to the chip central
portion, each word line shunt region WS is provided with four global IO
line pairs. Two of the four pairs of global IO lines further extend toward
the 2-megabit memory array MSA1 which is away from the chip central
portion. Namely, two global IO line pairs GIO are arranged on each word
line shunt region of the 2-megabit memory array MSA1 which is away from
the chip central portion. The two global IO line pairs GIO are used by a
single 2-megabit memory array MSA in each array group AG.
Local IO line pairs LIO are provided in order to transfer data between
selected memory cells and the global IO line pairs GIO. These local IO
line pairs LIO are independently provided for the respective array groups
AG1, AG2, AG3 and AG4. Four local IO line pairs LIO are arranged for each
32-k bit memory array MK so that two pairs are arranged on one side and
the remaining two pairs are arranged on the other side.
These local IO line pairs LIO are shared by the 32-k bit memory arrays MK,
belonging to the same array group AG, which are adjacent in a direction of
the word lines WL, as well as the 32-k bit memory arrays MK which are
adjacent in a direction of the bit lines BL.
The memory arrays MK have an alternately arranged type shared sense
amplifier structure, as hereinafter described in detail. A sense amplifier
is arranged in each region between each pair of 32-k bit memory arrays MK
which are adjacent to each other in a direction of the bit lines BL. Block
selecting switches BS are arranged in order to connect the global IO line
pairs GIO with the local IO line pairs LIO. These block selecting switches
BS are arranged on intersections between the word line shunt regions WS
and the sense amplifier bands.
As to the column selection lines CSL for transmitting column selection
signals from the column decoders CD, a single column selection line is
brought into a selected state in each of the array groups AG1 to AG4. The
single column selection lines CSL selects four bit line pairs BLP to
connect the same to corresponding local IO line pairs LIO in the 2-megabit
memory array MSA1 which is away from the chip central portion, while
selecting four bit line pairs BLP to connect the same to corresponding
local IO line pairs LIO in the 2-megabit memory array MSA2 which is close
to the chip central portion.
Namely, the single column selection lines CSL selects eight bit line pairs
BLP, to connect the same to eight global IO line pairs GIO through the
local IO line pairs LIO. Two memory mats MM are activated and 8.times.4=32
bit line pairs BLP are selected in each memory mat MM, whereby 64 bit line
pairs BLP are simultaneously selected in total so that 64-bit memory cells
are simultaneously accessible in total.
FIG. 3 illustrates exemplary correspondence between the column selection
lines CSL, the global IO line pairs GIO and data input/output terminals
DQ. In the example shown in FIG. 3, data are inputted/outputted in units
of eight bits. Referring to FIG. 3, each column selection line CSL
corresponds to one data input/output terminal DQ. In other words, eight
global IO line pairs GIO0 to GIO7 which are related to a column selection
line CSL correspond to one data input/output terminal. A wrap length
indicates the number of continuously accessed byte data (denoted by
symbols a0 and a1 in FIG. 3). This wrap length is changeable.
In the structure shown in FIG. 3, the preamplifiers (read registers) PA or
the write buffers WB are successively activated in accordance with wrap
addresses described later.
[Arrangement of Memory Cell]
FIG. 4 illustrates a structure which is related to a single 32-k bit memory
array MK2. Referring to FIG. 4, the 32-k bit memory array MK2 includes a
word line WL which receives a row selecting signal from the row decoder
RD, bit line pairs BLP which are arranged in a direction intersecting with
the word lines WL, and dynamic memory cells MC which are arranged in
correspondence to intersections between the word line WL and the bit line
pairs BLP.
Each memory cell MC includes an access transistor and a capacitor for
storing information. Each bit line pair BLP includes bit lines BL and/BL
which receive complementary signals. Referring to FIG. 4, the memory cells
MC are shown being arranged in correspondence to intersections between the
bit lines BL and the word line WL.
Array selector gates SAG1 and SAG2 are arranged on both sides of the memory
array MK2. These array selector gates SAG1 and SAG2 are alternately
arranged with respect to the bit line pairs BLP. The array selector gates
SAG1 enter a conducting state in response to an array selection signal
.phi.A1, while the array selector gates SAG2 enter a conducting state in
response to an array selection signal .phi.A2. The bit line pairs BLP are
connected to sense amplifiers SA1 and SA2 through the array selector gates
SAG1 and SAG2 respectively.
The sense amplifiers SA1 are arranged on one side of the memory array MK2
in parallel with the word line WL, while the other sense amplifiers SA2
are arranged on the other side of the memory array MK2 in parallel with
the word line WL. Namely, these sense amplifiers SA1 and SA2 are
alternately arranged with respect to the bit line pairs BLP of the memory
array MK2. The sense amplifiers SA1 are shared by another memory array MK1
and the memory array MK2, while the sense amplifiers SA2 are shared by the
memory array MK2 and still another memory array MK3.
Local IO line pairs LIO1 and LIO2 are arranged in parallel with the sense
amplifiers SA1. On the other hand, local IO line pairs LIO3 and LIO4 are
arranged in parallel with the sense amplifiers SA2. Referring to FIG. 4,
two local IO line pairs are provided on either side of the sense
amplifiers SA. Alternatively, the local IO line pairs may be arranged on
both sides of the sense amplifiers SA.
With respect to the sense amplifiers SA1, column selector gates CSG1 are
provided for transmitting data which are detected and amplified by the
sense amplifiers SA1 to the local IO line pairs LIO1 and LIO2. With
respect to the sense amplifiers SA2, column selector gates CSG2 are
provided for transmitting data which are detected and amplified by the
sense amplifiers SA2 to the local IO line pairs LIO3 and LIO4.
The column selection line CSL which receives the signal from the column
decoder CD simultaneously brings the two column selector gates CSG1 and
the two column selector gates CSG2 into a conducting state. Thus, four bit
line pairs BLP are simultaneously connected to the local IO line pairs
LIO1, LIO2, LIO3 and LIO4. The data which are detected and amplified by
the sense amplifiers SA1 are transmitted to the local IO line pairs LIO1
and LIO2. On the other hand, the data which are detected and amplified by
the sense amplifiers SA2 are transmitted to the local IO line pairs LIO3
and LIO4.
The block selecting switches BS for connecting the local IO line pairs LIO
to the global IO line pairs GIO conduct in response to a block selection
signal .phi.B. As such block selecting switches BL, FIG. 4 shows block
selecting switches BS1 and BS2 for connecting the local IO line pairs LIO1
and LIO2 to the global IO line pairs GIO1 and GIO2 respectively.
The local IO line pairs LIO3 and LIO4 are connected to two adjacent global
IO line pairs GIO through the block selecting switches BS respectively
(this connection is not shown in FIG. 4). The operation is now briefly
stated.
When the memory array MK2 includes a selected word line WL, the array
selection signals .phi.A1 and .phi.A2 enter active states so that the bit
line pairs BLP included in the memory array MK2 are connected to the sense
amplifiers SA1 and SA2. Array selector gates SAG0 and SAG3 which are
provided for the memory arrays MK1 and MK3 enter a nonconducting state,
while the memory arrays MK1 and MK3 maintain precharged states.
After memory cell data appear on the respective bit line pairs BLP, the
sense amplifiers SA1 and SA2 are activated to detect and amplify the
memory cell data.
Then, the signal on the column selection line CSL rises to a high level to
enter an active state, whereby the column selector gates CSG1 and CSG2
conduct so that the data which are detected and amplified by the sense
amplifiers SA1 and SA2 are transmitted to the local IO line pairs LIO1 to
LIO4 respectively.
Subsequently or simultaneously the block selection signals .phi.B enter
high-level active states, so that the local IO line pairs LIO1 to LIO4 are
connected to the global IO line pairs GIO1 to GIO4. In data reading, the
data of the global IO line pairs GIO1 to GIO4 are amplified through the
preamplifiers PA and outputted. In data writing, on the other hand, write
data which are supplied from the write buffers WB are transmitted to the
selected bit line pairs BLP through the global IO line pairs GIO and the
local IO line pairs LIO, so that the data are written in the memory cells
MC.
The block selection signals .phi.B enter active states only for the memory
array MK2 including the selected word line WL. This also applies to the
array selection signals .phi.A1 and .phi.A2. The block selection signals
.phi.B and the array selection signals .phi.A1 and .phi.A2 can be
generated through a prescribed number of bits (high-order four bits, for
example) of a multibit row address signal.
[Bank Structure]
In the SDRAM, the memory arrays are divided into a plurality of banks, as
hereinabove described. The banks must execute precharge operations and
activating operations (selection of word lines, activation of sense
amplifiers and the like) independently of each other. In the arrangement
shown in FIG. 1, the SDRAM includes the bank #1 which is formed by the
memory mats MM1 and MM2, and the bank #2 which is formed by the memory
mats MM3 and MM4.
The row decoders RD and the column decoders CD are provided in
correspondence to the respective memory mats MM, while internal data
transmission lines (the global IO line pairs GIO and the local IO line
pairs LIO) are also independently provided for the respective memory mats
MM, to satisfy conditions for such banks.
In the arrangement shown in FIG. 1, further, the input/output circuits PW
including the preamplifiers PA and the write buffers WB are also provided
for the respective memory mats MM, whereby it is also possible to
implement an interleave operation of alternately accessing the banks #1
and #2.
In other words, it is possible to precharge the bank #2 while accessing the
bank #1, for example. In this case, the bank #2 can be accessed with no
precharge time. It is possible to eliminate time loss caused by
precharging, which is required in a DRAM before access, by accessing and
precharging the banks #1 and #2 alternately, thereby implementing
high-speed access.
[Internal Control Signal Generation Circuitry]
FIG. 5 is a block diagram schematically showing a structure of internal
control signal generation circuitry of the SDRAM to which the present
invention is applied. The internal control signal generation circuitry
shown in FIG. 5 is included in the peripheral circuits PH shown in FIG. 1.
Referring to FIG. 5, a memory array includes a first bank (bank #A) 100a
and a second bank (bank #B) 100b. The banks 100a and 100b include the
column decoders CD, the row decoders RW and the input/output circuits PW
shown in FIG. 1.
FIG. 5 shows internal control signals which are generated in common for the
banks 100a and 100b, in order to avoid complication of illustration. In an
ordinary operation, only one of the banks 100a and 100b is activated in
accordance with a bank address signal BA, so that active control signals
are supplied to only the activated bank 100a or 100b.
Referring to FIG. 5, internal control circuitry (peripheral circuitry PH)
includes a CS buffer 114 which buffers an external control signal ext./CS
and generates an internal control signal/CS, and a clock buffer 110 which
buffers an external clock signal ext.CLK and generates an internal clock
signal CLK. The external control signal ext./CS is a chip selection signal
which indicates selection of this SDRAM. The SDRAM enters an operable
state when the signal ext./CS enters a low-level active state.
The peripheral circuit PH further includes a first control signal
generation circuit 116 which is activated in response to the internal
control signal/CS received from the CS buffer 114 to take in external
control signals ext./RAS, ext./CAS, ext./WE and ext. DQM and generate
various internal control signals, and a second control signal generation
circuit 118 which generates various control signals for driving a selected
array or bank in response to the control signals received from the first
control signal generation circuit 116 and the bank address signal BA.
The first control signal generation circuit 116 takes in the external
control signals ext./RAS, ext./CAS and ext./WE in response to the internal
clock signal CLK to determine a specified operation mode along combination
of the states of the control signals. In accordance with the result of
this determination, the first control signal generation circuit 116
generates a write control signal .phi.W, a read control signal .phi.O, a
row selection control signal .phi.R, a column selection control signal
.phi.C, a row address buffer activation signal RADE and a column address
buffer activation signal CADE. The first control signal generation circuit
116 further takes in the circuit control signal ext.DQM on a leading edge
of the internal clock signal CLK, to enable an input/output buffer.
The second control signal generation circuit 118 receives the internal
clock signal CLK and the bank address signal BA, to generate a sense
amplifier activation signal .phi.SA, a preamplifier activation signal
.phi.PA, a write register activation signal .phi.WB, an input buffer
activation signal .phi.DB and an output buffer enable signal .phi.OE.
The control signals .phi.WB, .phi.DB and .phi.OE are generated from the
second control signal generation circuit 118 along a prescribed count
number (latency) of the internal clock signal CLK.
The peripheral circuit PH further includes an address buffer 124 which is
activated in response to the row address buffer activation signal RADE and
the column address buffer activation signal CADE received from the first
control signal generation circuit 116 to take in an external address
signal ext.A as a row address signal and a column address signal
respectively and generate an internal row address signal Xa, an internal
column address signal Ya and the bank address signal BA, and a register
control circuit 122 which operates in response to the internal clock
signal CLK to receive a predetermined bit of a column address signal Ym
from the address buffer 124 and generate signals for controlling
operations of read and write registers (described later) included in the
input/output circuits PW, i.e., a wrap address WY, a read register driving
signal .phi.Rr and a write register driving signal .phi.RW.
Under control by the register control circuit 122, a plurality of read
registers and a plurality of write registers provided for each data
input/output terminal are selected and have operation thereof controlled.
FIG. 6 illustrates an internal structure of the first control signal
generation circuit 116 shown in FIG. 5. As shown in FIG. 6, the first
control signal generation circuit 116 includes a state decoder 116a which
is activated in response to the internal control signal/CS to determine
states of the external control signals ext./RAS, ext./CAS and ext./WE on a
leading edge of the clock signal CLK received from the clock buffer 110.
This state decoder 116a generates required internal controls and address
buffer activation signals in accordance with the states of the received
control signals. These external control signals ext./RAS, ext./CAS and
ext./WE are supplied in the form of one-shot pulse only in a clock cycle
specifying an operation mode.
[Correspondence between State of Control Signal and Operation Mode]
FIG. 7 illustrates correspondence between states of the external control
signals on leading edges of the clock signal CLK and correspondingly
specified operation modes. The state decoder 116a shown in FIG. 6
generates various required internal control signals so that the operations
shown in FIG. 7 are executed.
(a)/CS=/RAS="L" and/CAS=/WE="H"
In this state, strobing of a row address signal as well as activation of an
array are specified. Namely, this state is called an active command, and
the row and bank addresses are taken in so that operations related to row
selection with respect to the selected bank are executed.
(b)/CS=/CAS="L" and/RAS=/WE="H"
In this state, strobing of a column address signal and a data read
operation mode are specified. This state is called a read command, and a
read data register is selected so that data are transferred from selected
memory cells to the read data register and successively read out.
(c)/CS=/CAS=/WE="L" and/RAS="H"
This state specifies strobing of a column address and a data write
operation. This state is called a write command. When this write command
is supplied, a write register is activated so that supplied data are
written in the write register and selected memory cells.
At this time, a column selecting operation is executed in accordance with
the strobed column address.
(d)/CS=/RAS=/WE="L" and/CAS="H"
This state is called a precharge command, in which a selected array is
brought into a precharged state and termination of a self-refresh
operation is specified.
(e)/CS=/RAS=/CAS="L" and/WE="H"
In this state, a refresh mode is specified and a self-refresh operation is
started. In this operation mode, generation of a refresh address and a
refresh operation for memory cells in a selected row are executed through
a built-in address counter and a timer (not shown).
(f)/cs=/RAS=/CAS=/WE="L"
In this operation mode, data are set in a mode register. This mode register
is adapted to specify an operation mode which is specific to the SDRAM, so
that a desired operation is executed in accordance with the data set in
this mode register. Such a mode register is used for setting of a wrap
length or the like.
(g) DQM="L"
In this operation mode, a data write or read operation is executed in an
operation mode (read or write mode) which is previously decided by the
signals/CAS and WE. Namely, externally supplied write data are stored in
the write register or data stored in the read data register are read out.
(h) DQM="H"
In this operation mode, data reading is inactivated and a write mask
operation (mask operation on continuous byte data (wrap data)). Namely, a
data write/read operation is inhibited.
(i)/CS="L" and/RAS=/CAS=/WE=H"
In this state, no particular change is caused in the operation. No
operation mode is specified. The SDRAM is in a selected state and in
execution of a previously specified operation.
(j)/cs="H"
In this state, the SDRAM is in a non-selected state, and the
signals/RAS,/CAS and/WE are ignored.
Referring to FIG. 7, signs "-" indicate "don't care" states, and symbols X
indicate "arbitrary" states.
[Data Read Circuitry]
FIG. 8 illustrates structures of data read circuitry of the SDRAM to which
the present invention is applied. Referring to FIG. 8, the SDRAM includes
banks #A and #B having the same structures. FIG. 8 shows only structures
of data read circuitry for a single data input/output terminal DQ. When
the SDRAM has an 8-bit structure, eight structures corresponding to that
shown in FIG. 8 are provided in parallel with each other.
Referring to FIG. 8, the data read circuitry of the bank #A includes read
registers RG0A to RG7A which amplify and latch data on corresponding
global IO line pairs GIO0A to GIO7A in accordance with a preamplifier
enable signal PAEA and a transfer command signal TLRA, tristate inverter
buffers TBOA to TB7A which transfer data of corresponding read registers
RGOA to RG7A in accordance with wrap addresses RWYiA and/RWYiA (i=0 to 7),
a latch circuit LA-A which latches an output of a selected one of the
inverter buffers TBOA to TB7A, and a tristate inverter buffer TB8A which
inverts and amplifies latch data of the latch circuit LA-A in accordance
with bank specifying signals BAA and BAB.
The data read circuitry of the bank #B includes a structure which is
similar to that of the bank #A. Read registers RB0B to RG7B amplify and
latch data on corresponding global IO line pairs GIO0B to GIO7B in
accordance with a preamplifier enable signal PAEB and a transfer command
signal TLRB. Tristate inverter buffers TB0B to TB7B invert and amplify
latch data of the corresponding read registers RG0B to RG7B in accordance
with wrap addresses RWY0B,/RWY0B to RWY7B,/RWY7B.
A latch circuit LA-B latches an output of an activated one of the tristate
inverter buffers TB0B to TB7B. A tristate inverter buffer TB8B inverts and
amplifies data latched by the latch circuit LA-B.
The SDRAM further includes a latch circuit 150 which latches outputs from
the banks #A and #B (the tristate inverter buffers TB8A and TB8B), and an
output buffer 160 which transmits an output of the latch circuit 150 to
the data input/output terminal DQ in accordance with an output enable
signal OEM. The output buffer 160 enters an output high impedance state
when the output enable signal OEM is in a low-level inactive state.
The latch circuit 150 includes a tristate inverter buffer 152 which is
activated in response to control signals DOT and/DOT, and a latch circuit
154 which latches an output of the tristate inverter buffer 152. The
operations are now described.
One of the banks #A and #B is activated in accordance with the bank address
BA. In other words, one of the tristate inverter buffers TB8A and TB8B
enters an active state and the other one enters an inactive state.
Consider that the bank #A is now activated.
Data of 8-bit memory cells are transmitted onto the global IO line pairs
GIO0A to GIO7A. The read registers RGOA to RG7A store the data on the
corresponding global IO line pairs GIO0A to GIO7A in accordance with the
preamplifier enable signal PAEA and the transfer command signal TLRA.
Then, the wrap address signals RWY0,/RWY0 to RWY7, /RWY7 are successively
activated in a prescribed order, so that the tristate inverter buffers
TB0A to TB7A are successively activated in the prescribed order. The
register control circuit 122 decides the order for activating the wrap
address signals RWY0 to RWY7 by decoding a prescribed number of bits of
the column address signal Ym which is supplied from the address buffer
124. Memory cell data outputted from the tristate inverter buffers TB0A to
TB7A are latched by the latch circuit LA-A. Then, the data latched in the
latch circuit LA-A is stored in the latch circuit 154 in accordance with
the transfer signals DOT and/DOT. The data stored in the latch circuit 154
is outputted from the output buffer 160 in accordance with the output
enable signal OEM.
[Read Register]
FIG. 9 illustrates an exemplary structure of each read register shown in
FIG. 8. The read registers RG0A to RG7A and RG0B to RG7B are identical in
structure to each other, and hence the read register appearing in FIG. 9
is denoted by symbol RG.
Referring to FIG. 9, the read register RG includes a preamplifier PRA which
amplifies signal potentials on corresponding global IO lines GIOi and/GIOi
in response to a preamplifier enable signal PAE (the signal PAEA or PAEB),
and a latch circuit LRG which latches the data amplified by the
preamplifier PRA.
The preamplifier PRA includes complimentarily connected p-channel and
n-channel MOS transistors (insulated gate field-effect transistors) 750
and 754 receiving the preamplifier enable signal PAE at gates thereof, an
n-channel MOS transistor 756 which is provided between the transistor 754
and a ground potential and has a gate connected to the global IO
line/GIOi, complementarily connected p-channel and n-channel MOS
transistors 752 and 755 receiving the preamplifier enable signal PAE at
gates thereof, and an n-channel MOS transistor 757 which is provided
between the transistor 755 and a ground potential and has a gate connected
to the global IO line GIOi.
The preamplifier PRA further includes p-channel MOS transistors 751 and 753
which are provided in parallel with the transistors 750 and 752
respectively. Gates and drains of the transistors 751 and 753 are
cross-connected with each other.
The latch circuit LRG includes a pair of two-input NAND circuits 760 and
762. The NAND circuit 760 has an input which is coupled to a node N30 (one
output node of the preamplifier PRA), and another input which is coupled
to an output of the NAND circuit 762. On the other hand, the NAND circuit
762 has an input which is coupled to a node N32 (another output node of
the preamplifier PRA), and another input which is coupled to an output
node N34 of the NAND circuit 760. The output node N34 of the NAND circuit
760 outputs the data stored in the read register RG. The operations of the
read register RG shown in FIG. 9 are now described with reference to an
operation waveform diagram shown in FIG. 10.
When a read command is supplied, column selection is executed in accordance
with a currently supplied column address signal Ym. In the selected bank,
data of selected memory cells are transmitted onto the global IO lines
GIOi and/GIOi, so that signals on the global IO lines GIOi and /GIOi are
changed to potentials corresponding to the read data. Referring to FIG.
10, data "1" corresponding to a high-level potential is read on the global
IO line GIOi, while data "0" corresponding to a low-level potential is
read on the global IO line/GIOi.
Upon ascertainment of the potentials on the global IO lines GIOi and/GIOi,
the preamplifier enable signal PAE is generated when the read command is
supplied, through use of the clock signal CLK as a trigger signal.
The preamplifier enable signal PAE is included in the signal .phi.PA which
is generate | | |
