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Claims  |
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What is claimed is:
1. A data processing system comprising
a digital processor;
a system clock circuit for producing a system clock signal having timing
edges for controlling operation of the digital processor;
a synchronous random access memory, directly responsive to the edges of the
system clock signal, for accessing addressable storage cells within the
synchronous memory to write data into the storage cells and to read out
data from the storage cells; and
the synchronous random access memory including input and output data
latches arranged for latching data directly in response to the system
clock signal.
2. A data processing system, in accordance with claim 1, further comprising
a timing and control circuit, directly responsive to the edges of the
system clock signal, for producing control signals synchronized with the
system clock signal to control write-in and read out operations of the
synchronous random access memory;
row address circuitry, responsive to a first control signal produced by the
control and timing circuit, for accessing a row of addressable storage
cells to write data in or to read data out of the synchronous memory; and
column address circuitry, responsive to other control signals produced by
the control and timing circuit, for accessing a block of columns of
addressable storage cells to write data in or to read data out of the
synchronous memory.
3. A data processing system, in accordance with claim 1, wherein
the synchronous random access memory is fabricated as a metal oxide
semiconductor device having an array of static storage cells.
4. A data processing system, in accordance with claim 1, wherein
the synchronous random access memory is fabricated as a metal oxide
semiconductor device having an array of dynamic storage cells.
5. A data processing system, in accordance with claim 1, wherein
the digital processor produces control signals that are applied to a timing
and control circuit together with the system clock signal for controlling
generation of synchronous random access memory control signals.
6. A data processing system, in accordance with claim 5, wherein
the array of dynamic storage cells is fabricated as complementary metal
oxide semiconductor circuits.
7. A data processing system, in accordance with claim 5, wherein
the array of dynamic storage cells is fabricated as bipolar complementary
metal oxide semiconductor circuits.
8. A data processing system comprising
a digital processor;
a system clock circuit for producing a system clock signal having a timing
edge for controlling operation of the digital processor;
a synchronous random access memory arranged for storing data in an array of
storage cells, which are addressable by row and column addresses;
the digital processor being responsive to edges of the system clock signal
and arranged for producing a gated system clock signal having timing edges
correlated with the timing edges of the system clock signal; and
the synchronous random access memory being directly responsive to the edges
of the gated system clock signal for accessing the storage cells for
write-in and read out operations.
9. A synchronous random access memory comprising:
an array of storage cells arranged in addressable rows and columns;
a row address buffer;
a row address decoder;
a column address buffer;
a column address decoder; and
circuitry, responsive to edges of a system clock signal applied directly
from a microprocessor, for enabling row address data to be stored in the
row address buffer for decoding through the row address decoder and for
enabling column address data to be stored in the column address buffer for
decoding in the column address decoder.
10. A synchronous random access memory, in accordance with claim 9, wherein
a row address control signal, in conjunction with an edge of the system
clock signal, enables the row address buffer to store the row address
data;
a column address control signal, in conjunction with an edge of the system
clock signal, enables the column address buffer to store the column
address data;
a write signal, in conjunction with an edge of the system clock signal,
generates a write control signal that enables data, applied to an input
terminal of the synchronous random access memory, to be written into an
addressed storage cell in synchronism with the system clock signal; and
a read signal, in conjunction with an edge of the system clock signal,
generates a read control signal that enables data, stored in an addressed
storage cell, to be read out to an output terminal of the synchronous
random access memory in synchronism with the system clock signal.
11. A synchronous random access memory comprising:
an array of storage cells arranged in addressable rows and columns;
a row address buffer;
a row address decoder;
a column address buffer;
a column address decoder; and
circuitry, responsive to edges of a system clock signal, for enabling row
address data to be stored in the row address buffer for decoding through
the row address decoder and for enabling column address data to be stored
in the column address buffer for decoding in the column address decoder.
12. A synchronous random access memory, in accordance with claim 11,
wherein
a row address control signal, in conjunction with an edge of the system
clock signal, enables the row address buffer to store the row address
data;
a column address control signal, in conjunction with an edge of the system
clock signal, enables the column address buffer to store the column
address data;
a write signal, in conjunction with an edge of the system clock signal,
generates a write control signal that enables data, applied to an input
terminal of the synchronous random access memory, to be written into an
addressed storage cell; and
a read signal, in conjunction with an edge of the system clock signal,
generates a read control signal that enables data, stored in an addressed
storage cell, to be read out to an output terminal of the synchronous
random access memory.
13. A synchronous random access memory, in accordance with claim 11,
further comprising
a column address counter, interposed between the column address buffer and
the column address decoder, for receiving an initial column address;
the column address decoder, in response to a most significant group of bits
in the column address counter, accesses a block of columns of storage
cells in the array for writing in data or for reading out data; and
an input or output multiplexer, responsive to a least significant group of
bits in the column address counter, establishes a conduction path for data
bits being written into or read out of the array of storage cells.
14. A synchronous random access memory in accordance with claim 11, wherein
a circuit for receiving a write signal that controls the synchronous random
access memory to selectively write or read data in concurrence with edges
of the system clock signal.
15. A synchronous random access memory in accordance with claim 11, wherein
in response to edges of the system clock signal, the synchronous random
access memory performs a random access read operation in synchronism with
the system clock signal.
16. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, the synchronous random
access memory performs a random access write operation in synchronism with
the system clock signal.
17. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, a read signal, a burst
select signal, and a burst increment signal, the synchronous random access
memory performs a synchronous burst read-up operation.
18. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, a read signal, a burst
select signal, and a burst decrement signal, the synchronous random access
memory performs a synchronous burst read-down operation.
19. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, a write signal, a burst
select signal, and a burst increment signal, the synchronous random access
memory performs a synchronous burst write-up operation.
20. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, a write signal, a burst
signal, and a burst decrement signal, the synchronous random access memory
performs a synchronous burst write-down operation.
21. A synchronous random access memory, in accordance with claim 11,
wherein
the array of storage cells is fabricated as an array of static memory
circuits.
22. A synchronous random access memory, in accordance with claim 21,
wherein
the array of storage cells is fabricated as a metal oxide semiconductor
device.
23. A synchronous random access memory, in accordance with claim 22,
wherein
the array of storage cells comprises complementary metal oxide
semiconductor circuits.
24. A synchronous random access memory, in accordance with claim 22,
wherein
the array of storage cells comprises bipolar complementary metal oxide
semiconductor circuits.
25. A synchronous random access memory, in accordance with claim 11,
wherein
the array of storage cells is fabricated as an array of dynamic memory
circuits.
26. A synchronous random access memory, in accordance with claim 25,
wherein
the array of storage cells is fabricated as a metal oxide semiconductor
device.
27. A synchronous random access memory in accordance with claim 26, wherein
the array of storage cells comprises complementary metal oxide
semiconductor circuits.
28. A synchronous random access memory in accordance with claim 26, wherein
the array of storage cells comprises bipolar complementary metal oxide
semiconductor circuits.
29. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, a read signal, a burst
select signal, a wrap length signal, and a wrap control signal, the
synchronous random access memory performs a synchronous wrap read
operation.
30. A synchronous random access memory, in accordance with claim 11,
wherein
in response to edges of the system clock signal, a write signal, a burst
select signal, a wrap length signal and a wrap control signal, the
synchronous random access memory performs a synchronous wrap write
operation.
31. A data processing system, in accordance with claim 1, wherein
the timing edges are rising edges; and
the input and output latches are arranged for latching data in direct
response to the rising edges.
32. A data processing system, in accordance with claim 1, wherein
the timing edges are falling edges; and
the input and output latches are arranged for latching data directly in
response to the falling edges.
33. A data processing system, in accordance with claim 1, wherein
the timing edges are rising and falling edges; and
the input and output latches are arranged for latching data directly in
response either to the rising edges or the falling edges.
34. A data processing system, in accordance with claim 2, wherein
the edges of the system clock signal are rising edges; and
the input and output latches are arranged for latching data directly in
response to the rising edges.
35. A data processing system, in accordance with claim 2, wherein
the edges of the system clock signal are falling edges; and
the input and output latches are arranged for latching data directly in
response to the falling edges.
36. A data processing system, in accordance with claim 2, wherein
the edges of the system clock signal are rising and falling edges; and
the input and output latches are arranged for latching data directly in
response either to the rising or the falling edges.
37. A data processing system comprising
a digital processor;
a system clock circuit for producing a system clock signal having timing
edges for controlling operation of the digital processor;
a synchronous random access memory, directly responsive to the edges of the
system clock signal, for accessing addressable storage cells within the
synchronous memory to write data into the storage cells and to read out
data from the storage cells;
the synchronous random access memory including input and output data
latches arranged for latching data directly in response to the system
clock signal;
a timing and control circuit, directly responsive to the edges of the
system clock signal, for producing control signals synchronized with the
system clock signal to control write-in and read out operations of the
synchronous random access memory;
row address circuitry, responsive to a first control signal produced by the
control and timing circuit, for accessing a row of addressable storage
cells to write data in or to read data out of the synchronous memory; and
column address circuitry, responsive to other control signals produced by
the control and timing circuit, for accessing a set of columns of
addressable storage cells to write data in or to read data out of the
synchronous memory.
38. A data processing system, in accordance with claim 37, wherein the
timing edges of the system clock signal are positive-going edges.
39. A data processing system, in accordance with claim 37, wherein the
timing edges of the system clock signal are negative-going edges.
40. A data processing system, in accordance with claim 37, wherein the
timing edges are positive-going or negative-going edges.
41. A data processing system comprising
a digital processor;
a system clock circuit for producing a system clock signal having either
rising or falling timing edges for controlling operation of the digital
processor;
a synchronous random access memory arranged for storing data in an array of
storage cells, which are addressable by row and column addresses;
the digital processor being responsive to the timing edges of the system
clock signal and arranged for producing a gated system clock signal having
either rising or falling timing edges correlated with the timing edges of
the system clock signal; and
the synchronous random access memory being directly responsive either to
the rising or falling edges of the gated system clock signal for accessing
the storage cells for write-in and read out operations.
42. A synchronous random access memory comprising:
an array of addressable storage cells;
a circuit for receiving a system clock signal; and
circuitry, responsive to edges of the system clock signal, for enabling
address data to be stored in an address circuit for decoding through an
address decoder.
43. A synchronous random access memory, in accordance with claim 42,
wherein
the edges are positive-going edges.
44. A synchronous random access memory, in accordance with claim 42,
wherein
the edges are negative-going edges.
45. A synchronous random access memory, in accordance with claim 42,
wherein
the edges are either negative-going or positive-going edges.
46. A synchronous random access memory, in accordance with claim 42,
wherein
a row address control signal, in conjunction with an edge of the system
clock signal, enables a row address part of the address circuit to store
the row address data;
a column address control signal, in conjunction with an edge of the system
clock signal, enables a column address part of the address circuit to
store the column address data;
a write signal, in conjunction with an edge of the system clock signal,
generates a write control signal that enables data, applied to an input
terminal of the synchronous random access memory, to be written into an
addressed storage cell in synchronism with the system clock signal; and
a read signal, in conjunction with an edge of the system clock signal,
generates a read control signal that enables data, stored in an addressed
storage cell, to be read out to an output terminal of the synchronous
random access memory in synchronism with the system clock signal.
47. A synchronous random access memory, in accordance with claim 46,
wherein
the edges are either negative-going or positive-going edges.
48. A synchronous random access memory comprising:
an array of addressable storage cells;
a circuit for receiving a system clock signal; and
circuitry, responsive to an edge of the system clock signal, for enabling
address data to be stored in an address buffer for decoding through an
address decoder.
49. A synchronous random access memory, in accordance with claim 48,
wherein
the edge is either a negative-going transition or a positive-going
transition.
50. A synchronous random access memory, in accordance with claim 48,
wherein
a row address control signal, in conjunction with the edge of the system
clock signal, enables a row address part of the address circuit to store
the row address data;
a column address control signal, in conjunction with the edge of the system
clock signal, enables a column address part of the address circuit to
store the column address data;
a write signal, in conjunction with the edge of the system clock signal,
generates a write control signal that enables data, applied to an input
terminal of the synchronous random access memory, to be written into an
addressed storage cell in synchronism with the system clock signal; and
a read signal, in conjunction with the edge of the system clock signal,
generates a read control signal that enables data, stored in an addressed
storage cell, to be read out to an output terminal of the synchronous
random access memory in synchronism with the system clock signal.
51. A synchronous random access memory, in accordance with claim 50,
wherein
the edge is either a negative-going transition or a positive-going
transition.
52. A data processing system comprising:
a digital processor;
an input peripheral device interconnected with the digital processor;
an output peripheral device interconnected with the digital processor;
a system clock circuit, producing a system clock signal having timing
edges, for controlling operation of the digital processor, the input
peripheral device, and the output peripheral device; and
a synchronous dynamic random access memory, directly responsive to the
timing edges of the system clock signal, for accessing addressable storage
cells within the synchronous dynamic random access memory to write data
into the storage cells and to read out data from the storage cells.
53. A data processing system comprising:
a digital processor;
an input peripheral device interconnected with the digital processor;
an output peripheral device interconnected with the digital processor;
a clock circuit, producing a clock signal for controlling operation of the
digital processor, the digital processor producing a system clock signal
having timing edges for controlling operation of the input peripheral
device and the output peripheral device; and
a synchronous random access memory, directly responsive to the timing edges
of the system clock signal, for accessing addressable storage cells within
the synchronous dynamic random access memory to write data into the
storage cells and to read out data from the storage cells. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
This invention relates to random access memory (RAM) arranged for operating
in a data processing system.
In the past, semiconductor random access memory operated faster than the
associated microprocessor. During the late 1970's and early 1980's, the
microcomputer market was in the early stages of development. At that time,
a microcomputer system included a microprocessor and a dynamic random
access memory. In a microcomputer arrangement, the microprocessor ran
synchronously in response to a clock signal, but the dynamic random access
memory ran asynchronously with respect to the operation of the
microprocessor. The microprocessor clock was applied to a controller
circuit that was interposed between the microprocessor and the dynamic
random access memory. In response to the microprocessor clock signal, the
controller derived other control or clock signals which ran the dynamic
random access memory operation.
Typical operating speeds of the microprocessor and the dynamic random
access memory were different from each other. A microprocessor cycle time
was in a range of 400-500 nanoseconds while a dynamic random access memory
cycle time was approximately 300 nanoseconds. Thus the dynamic random
access memory was able to operate faster than its associated
microprocessor. The memory completed all of its tasks with time to spare.
As a result, the microprocessor operated at its optimum speed without
waiting for the memory to write-in data or read out data.
Subsequently, as the semiconductor art developed, the operating speeds of
microprocessors and memory devices have increased. Microprocessor speeds,
however, have increased faster than dynamic random access memory speeds.
Now microprocessors operate faster than their associated dynamic random
access memory. For instance, a microprocessor cycle time is approximately
40 nanoseconds and a dynamic random access memory cycle time is
approximately 120 nanoseconds. The microprocessor completes all of its
tasks but must wait significant periods of time for the dynamic random
access memory.
Having the microprocessor waiting for the memory is a problem that has been
attracting the attention of many microcomputer designers. High speed
static cache memories have been added to the microcomputer systems to
speed up access to data stored in the memory. A significant part of the
problem is to speed up access to data in the memory without significantly
increasing the cost of the microcomputer system. Cache memory, however, is
significantly more expensive than dynamic random access memory.
An existing problem with dynamic random access memory devices is that they
require a substantial amount of peripheral circuitry between the
microprocessor and the memory for generating several control signals. So
many interdependent control signals are generated by long logic chains
within the peripheral circuitry that microcomputer systems designers must
resolve very complex timing problems. The delay caused by the timing
problems and the fact that memories now are accessed slower than the
associated microprocessor cause problems of excessive time delays in
microcomputer system operations.
SUMMARY OF THE INVENTION
These and other problems are solved by a random access memory which is
arranged to be responsive directly to a system clock signal for operating
synchronously with the associated digital processor. The synchronous
random access memory is further arranged to write-in or read out data in
either a synchronous burst mode or a synchronous wrap mode in addition to
synchronous random access operations. Such a synchronous random access
memory device may be fabricated as a dynamic or as a static storage
device.
Control signals from the digital processor are used for controlling various
memory operations. As an alternative, the digital processor may process a
clock signal that is used as the system clock for operating both the
digital processor and the synchronous random access memory. The digital
processor may be a microprocessor.
BRIEF DESCRIPTION OF THE DRAWING
A better understanding of the invention may be derived by reading the
following detailed description with reference to the drawing wherein:
FIG. 1 is a block diagram of a data processing system including a
synchronous random access memory;
FIG. 2 is a block diagram of a synchronous random access memory;
FIG. 3 is a timing diagram of a synchronous random access read operation;
FIG. 4 is a timing diagram of a synchronous random access write operation;
FIG. 5 is a timing diagram of a synchronous burst read-up operation;
FIG. 6 is a block diagram of a column address counter and the wrap address
scrambler;
FIG. 7 is a timing diagram of a synchronous burst read-down operation;
FIG. 8 is a timing diagram of another synchronous burst read-up operation;
FIG. 9 is a timing diagram of another synchronous burst read-down
operation;
FIG. 10 is a timing diagram of a synchronous burst write-up operation;
FIG. 11 is a timing diagram of a synchronous burst write-down operation;
FIG. 12 is a timing diagram of another synchronous burst write-up
operation;
FIG. 13 is a timing diagram of another synchronous burst write-down
operation;
FIG. 14 is a timing diagram of a synchronous wrap read 8-bit operation;
FIG. 15 is a truth table for a wrap address scrambler used in a synchronous
wrap read 8-bit operation;
FIG. 16 is a timing diagram of a synchronous wrap read 4-bit operation;
FIG. 17 is a truth table for a wrap address scrambler used in a synchronous
wrap read 4-bit operation;
FIG. 18 is a schematic block diagram of a stage for the column address
counter of FIG. 17;
FIG. 19 is a logic schematic diagram of a timing gate circuit;
FIG. 20 is a timing diagram for the operation of the gate circuit of FIG.
19;
FIG. 21 is a logic schematic diagram for another timing gate circuit;
FIG. 22 is a timing diagram for the operation of the gate circuit of FIG.
20;
FIG. 23 is a block diagram of an input multiplexer and an output
multiplexer arrangement for the synchronous memory of FIG. 2; and
FIG. 24 is a block diagram of an alternative data processing system
including a synchronous random access memory.
DETAILED DESCRIPTION
Referring now to FIG. 1, a data processing system 15 includes a digital
processor 20 which receives digital data by way of a bus 17 from an input
peripheral device 24. The digital processor 20 may be a microprocessor.
Control signals pass between the digital processor 20 and the input
peripheral device 24 by way of a control bus 18. The digital processor 20
processes that data and other data, all of which may be transmitted by way
of a data bus 25 for storage in and retrieval from a synchronous memory,
device 30. The digital processor 20 also sends resulting output data via
an output data bus 32 to an output peripheral device 40 where the output
data may be displayed or used for reading, viewing or controlling another
device that is not shown. Control signals are transmitted between the
digital processor 20 and the synchronous memory device 30 by way of a
control bus 60. Control signals also are transmitted between the digital
processor 20 and the output peripheral device 40 by way of a control bus
62. System clock signals are produced by a system clock device 65 and are
applied through a clock lead 67 to the digital processor 20, the
synchronous memory device 30, the input peripheral device 24, and the
output peripheral device 40.
From time to time during operation of the data processing system 15, the
digital processor 20 accesses the synchronous memory 30 for writing data
into storage cells or for reading data from the storage cells thereof.
Storage cell row and column addresses, generated by the digital processor
20, are applied through an address bus 45 to the synchronous memory 30.
Data may be sent by way of the data bus 25 either from the digital
processor 20 to be written into the synchronous memory 30 or to be read
from the synchronous memory 30 to the digital processor 20.
Control signals, produced by the digital processor 20 and transmitted by
way of the control bus 60 to the synchronous memory 30 include a row
address control signal RE, a column address control signal CE, a write
signal WE, a burst signal BT, a burst direction signal .+-., a wrap select
signal WP, a wrap-type signal WT, a wrap-length signal WL, and others.
Control signals may also be transmitted from the synchronous memory 30 to
the digital processor 20.
Referring now to FIG. 2, the synchronous random access memory 30 includes a
memory array 75 of metal-oxide-semiconductor (MOS) dynamic storage cells
arranged in addressable rows and columns. The memory array 75 of storage
cells is similar to the well known arrays of cells used in dynamic random
access memory devices. Either complementary metal-oxide-semiconductor
(CMOS) or bipolar complementary metal-oxide-semiconductor (BICMOS)
technology may be used for fabricating the memory array 75.
Several other circuit blocks are shown in FIG. 2. These other circuit
blocks are designed and arranged for operating the array of storage cells
synchronously with the digital processor 20 of FIG. 1 in response to the
common system clock signal CLK, which may be gated by the digital
processor, as discussed subsequently with respect to FIG. 20. The circuit
blocks other than the array of storage cells may be fabricated as either
CMOS or BICMOS circuits.
The synchronous random access memory 30 is operable for synchronous random
access read or write operations, for synchronous burst read or write
operations, and for synchronous wrap read or write operations. All types
of synchronous operations are to be described fully hereinafter. Such
descriptions are to be made in reference to timing diagrams and truth
tables presented in FIGS. 3-5 and 7-17. In the timing diagrams, a DON'T
CARE state is represented by cross-hatching.
Referring now to FIGS. 3 and 2 for a synchronous random access read
operation, an N bit wide row address and the row address control signal RE
are applied to the address bus 45 and a lead 46. Control signals, such as
the signal RE and others, are active low signals. The write signal WE on a
lead 47 being high, at clock cycle time 2, designates a read operation.
The synchronous read operation commences at a falling edge of the system
clock signal CLK at signal time 1. For this illustrative embodiment, the
system clock times operations in synchronism at the negative-going edges
of the clock pulses, such as at the cycle times 1, 2, 3, etc. In other
embodiments, not shown herein, the system may time operations at the
positive-going edges or on both negative-going and positive-going edges of
the clock pulses.
When the system clock CLK has a negative-going edge while the row address
is applied at the clock cycle time 1 and the row address control signal RE
is low, the row address is latched into the row address buffer 48.
Since the illustrative embodiment has an N bit wide address bus, that bus
is time shared by row addresses and column addresses. During the clock
cycle time 2 following the latching of the row address into the row
address buffer 48, a column address is applied to the address bus 45.
While the column address control signal CE is low and the write signal WE
is high at the clock cycle time 2, the system clock goes low, latching the
column address into the column address buffer 49.
Concurrently with the latching of the column address into the column
address buffer, the row address is being decoded through the row address
decoder 50. The row address decoder 50 decodes the binary number row
address into a one-out-of-2.sup.N selection. As a result of the
one-out-of-2.sup.N selection, an active signal is applied to the wordline
of the one selected row. This wordline remains selected throughout the
remainder of the random access read operation.
At the next negative-going edge of the system clock CLK, a load initial
address signal LIA enables a group of load count transfer gates 51 to move
the initial column address into upper count and lower count sections of a
column address counter 52. The most significant bits of the column address
are latched into the upper count section 58 and the least significant bits
of the column address are latched into the lower count section 59 of the
column address counter 52. All of those address bits in the column address
counter 52 represent the initial column address to be applied to the
memory array for the read out operation. Since the operation being
described is a synchronous random access operation, the initial column
address is the only column address to be applied to the memory array
during the read operation.
The most significant bits of the initial column address are applied from
the upper count section 58 through a gate 53 to the column address decoder
54 for selecting M columns of storage cells of the memory array, from
which data are to be read out. These most significant bits of the column
address are decoded by the column address decoder 54 to enable a block of
M columns of storage cells in the memory array 75.
Data bits are read from a group of M storage cells, determined by a part of
the decoded column address, i.e., the decoded most significant bits of the
column address. These M data bits are transferred in parallel from the
memory array 75 through a group of leads 55 to an output multiplexer OMUX
where they are latched for output.
A one-out-of-M selection is made by the output multiplexer OMUX in response
to control signals applied to the output multiplexer from the lower count
section 59 of the column address counter 52. The least significant bits of
the initial column address, residing in the lower count section 59,
determine which bit latched in the output multiplexer OMUX is the
one-out-of-M bit to be gated through the output multiplexer to a lead in
the data bus 25.
Referring now to FIGS. 4 and 2 for a synchronous random access write
operation, row addressing and column addressing occur similar to the
synchronous random access read operation except that the write signal WE
is at a low level at the clock cycle time 2 to designate the synchronous
random access write operation. The decoded row address from the row
decoder 50 enables one row of storage cells in the memory array 75. The
most significant bits of the column address, decoded by the column decoder
54, enable a block of M column leads in the array. The selected set of
storage cells at the addressed intersections of the addressed row and the
set of M addressed columns are enabled to receive the data that is to be
written. The least significant bits of the column address (residing in the
lower count section 59 of the column address counter 52) determine control
signals that are applied to the input multiplexer IMUX for determining
which one-out-of-M bit on the data bus 25 is transmitted through the input
multiplexer IMUX to be written into the memory array 75. The one-out-of-M
bit is applied to the associated column lead of the selected block of
columns of storage cells in the memory array 75. That bit of data is
written into the storage cell at the address selected by the row address
and the initial column address. The other M-1 bits of data, related to the
selected set of M columns, are not written into the memory array 75
because the input multiplexer IMUX does not transmit those M-1 bits to the
associated column lines of the memory array 75.
The next subsequent operation of the memory array following either the
synchronous read operation or the synchronous write operation may be
another synchronous random access operation, i.e., either a synchronous
read operation or a synchronous write operation. The same row and column
addresses or a different row or column address can be used to select the
storage cell for the next access. A synchronous burst or a synchronous
wrap operation also may follow the synchronous random access read or write
operations.
In the foregoing discussion of the synchronous read and write operations,
the illustrative embodiment includes an N bit wide address bus 45 that is
time-shared by row and column addresses. In another useful embodiment, not
shown, | | |
