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Description  |
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FIELD OF USE
This invention relates to semiconductor devices. More particularly, this
invention relates to bipolar transistors, including structures and methods
for fabricating bipolar transistors.
BACKGROUND
A bipolar transistor formed with an emitter, collector, and intervening
base is typically created in a vertical arrangement along a major surface,
referred to here (for convenience) as the upper surface, of a
monocrystalline semiconductor body. The emitter, collector, and base are
all situated in the semiconductor body. The emitter adjoins the body's
upper surface.
The base consists of an intrinsic part (commonly referred to as the
"intrinsic base") and one or more laterally adjoining extrinsic parts
(commonly referred to as "extrinsic bases"). The intrinsic base lies
directly below the emitter. In a standard symmetrical configuration, there
are two extrinsic bases located on opposite sides of the intrinsic base.
Each extrinsic base includes a heavily doped contact zone which extends to
the upper semiconductor surface and to which electrical contact is made at
a location spaced laterally apart from the emitter. Each extrinsic base
may include a connection (or link) zone that provides a low-resistance
electrical path between the intrinsic base and the associated base contact
zone.
The collector contains a buried main portion situated below the intrinsic
base so that the emitter-collector current flows generally in the vertical
direction. The main collector portion extends laterally beyond the
intrinsic base to a heavily doped collector contact zone which typically
extends to the upper semiconductor surface to provide electrical access to
the collector at a location spaced laterally apart from the emitter and
the two base contact zones. Overlying ohmic electrical contacts to the
emitter and contact zones complete the transistor.
Referring to the drawings, FIG. 1 illustrates a prior art oxide-isolated
npn transistor of the vertical type as described in De Jong et al, U.S.
Pat. No. 5,006,476. The semiconductor body in FIG. 1 consists of p-
monocrystalline silicon substrate 10 and overlying n- epitaxial silicon
layer 12. Recessed field-oxide region 14 divides the epitaxial silicon
into a group of laterally separated active semiconductor regions, two of
which are interconnected by n+ buried layer 16 situated along the
metallurgical interface between substrate 10 and epitaxial layer 12.
In the device of FIG. 1, n+ emitter 18, which is formed by dopant
outdiffusion from n+ polycrystalline silicon ("polysilicon") emitter
contact 20 so as to be self-aligned to emitter contact 20, overlies p
intrinsic base 22. The transistor has two extrinsic bases, each formed
with a p+ contact zone 24 and a p connection zone 26. N+ collector contact
zone 28 connects to a main collector portion consisting of n+ buried layer
16 and overlying n-type epitaxial portions 30 and 32. Metal silicide caps
34, 36, and 38 respectively overlie contact zones 20, 24, and 28. Oxide
spacers 40 provide spacing between emitter contact 20 and each metal
silicide cap 36 through which a metal line (not shown) is connected to
underlying base contact zone 24.
Numerous engineering trade-offs are made in designing vertical bipolar
transistors. For example, by incorporating spacers 40 into the npn
transistor of FIG. 1, the probability of an electrical short between
emitter contact 20 and either of the base contacts is typically quite low.
Base connection zones 26 accompany spacers 40 in order to provide
low-resistance links between intrinsic base 22 and each base contact zone
24. However, forming connection zones 26 typically entails additional
processing and thus additional manufacturing expense.
As the lateral dimensions of transistors shrink, the probability that
heavily doped base contact zones 24 will encroach on emitter 22 increases.
Tang et al, "Design Considerations of High Performance Narrow-Emitter
Bipolar Transistors, " IEEE Elect. Dev. Lett., April 1987, pp. 174-175,
and Lu, "Lateral Encroachment of Extrinsic-Base Dopant in Submicrometer
Bipolar Transistors," IEEE Elect. Dev. Lett., October 1987, pp. 496-498
both investigate the effect of such encroachment in vertical bipolar
transistors similar to that of FIG. 1. Tang et al reports decreases in the
transistor cutoff frequency f.sub.T and the small-signal transistor
current gain. Cutoff frequency f.sub.T is the frequency at which the
small-signal current gain drops to 1. Lu et al reports a decrease in the
collector current I.sub.c.
An important parameter in bipolar transistor design is the punch-through
voltage V.sub.P. This is the value of the collector-to-emitter voltage
V.sub.CE at which the depletion region of the collector-base junction
reaches the depletion region of the emitter-base junction when the base is
open or the when base-to-emitter voltage V.sub.BE is at a selected value.
FIGS. 2a, 2b, 3a, and 3b are helpful in understanding the punch-through
phenomenon. FIG. 2a illustrates a simplified one-dimensional version of an
npn transistor during normal transistor operation, where t.sub.E and
t.sub.B respectively are the emitter and base thicknesses. FIG. 3a
illustrates the transistor when it is in the punch-through condition.
FIGS. 2b and 3b respectively depict the potentials across the transistor
when it is in the conditions of FIGS. 2a and 3a.
During normal operation, electrons in the emitter must overcome the
potential barrier at the emitter-base junction in order to enter the
quasi-neutral region of the base between the two depletion regions.
Electrons then diffuse across the quasi-neutral region until they reach
the collector-base depletion region where the electric field pulls them
into the collector. See FIGS. 2a and 2b. Altogether, the current flow from
emitter to collector is barrier limited and diffusion limited. The
magnitude of collector-to-emitter voltage V.sub.CE does not substantially
impact the magnitude of the emitter-to-collector current during normal
operation because (a) the potential barrier at the emitter-base junction
is controlled by the base-to-emitter voltage V.sub.BE and (b) the
diffusion-limiting action on the emitter-to-collector current flow is
determined by the thickness of the quasi-neutral region of the base.
When collector-to-emitter voltage V.sub.CE is raised to such a value that
the collector-base depletion region punches through to the emitter-base
depletion region, the quasi-neutral region of the base is eliminated as
shown in FIGS. 3a and 3b. The diffusion limitation on the
emitter-to-collector current flow is no longer present. Also, voltage
V.sub.CE now directly influences the emitter-base barrier potential,
causing its magnitude to be easily reduced. The net result is that the
number of electrons passing through the base increases rapidly in a
generally undesirable manner as voltage V.sub.CE is increased.
Accordingly, it is desirable that the magnitude of punch-through voltage
V.sub.P be high.
Another important bipolar design parameter is the Early voltage V.sub.A. At
a given value of base-emitter voltage V.sub.BE, collector current I.sub.C
is ideally independent of collector-to-emitter voltage V.sub.CE across the
normal V.sub.C operating range. However, because the size of the
quasi-neutral region of the base decreases with increasing V.sub.CE,
I.sub.C actually increases slowly with increasing V.sub.CE at fixed
V.sub.BE in the manner generally shown in FIG. 4.
Early voltage V.sub.A is a transistor modeling parameter that constitutes
the voltage at which the collector current asymptotes approximately
intersect the V.sub.CE axis. The points at which the I.sub.C asymptotes at
various V.sub.BE values intersect the V.sub.CE axis do not exactly
coincide in a real bipolar transistor. Nonetheless, it has turned out to
be a good modeling parameter to consider the I.sub.C asymptotes as all
meeting at the V.sub.A position on the V.sub.CE axis. As with
punch-through voltage V.sub.P, it is desirable that the magnitude of the
Early voltage V.sub.A be high, ideally infinite.
A critical engineering trade-off relating to the intrinsic base involves
punch-through voltage V.sub.P, Early voltage V.sub.A, and the base
(series) resistance r.sub.B, on one hand, and cutoff frequency f.sub.T and
collector current I.sub.C, on the other hand. Reducing base thickness
t.sub.B and/or the total base doping causes f.sub.T and I.sub.C to
increase. The current gain also increases with reduced t.sub.B. However,
V.sub.P, V.sub.A, and r.sub.B are degraded when t.sub.B and/or the base
doping is reduced.
In a simplified one-dimensional analysis, this trade-off can be seen from
the following equations that apply to a symmetrical single-emitter
vertical npn transistor such as that shown in FIG. 1:
##EQU1##
where: x is an integrating variable in the base along the direction of
main current flow,
.alpha..sub.0 is the static common-base current gain (nearly 1),
D.sub.n is the average electron diffusivity in the base,
t.sub.B is the metallurgical thickness of the base--i.e., the distance
between the emitter-base and collector-base junctions,
t.sub.BEFF is the effective electrical thickness of the base--i.e., the
distance between the boundaries of the emitter-base and collector-base
depletion regions,
n.sub.i is the intrinsic electron density (approximately
1.4.times.10.sup.10 electrons/cm.sup.3 in silicon at room temperature),
N.sub.A is the base (acceptor) dopant concentration,
W.sub.E is the lateral width of the emitter,
L.sub.E is the length of the emitter,
C.sub.jc is the depletion capacitance of the collector-base junction per
unit area,
N.sub.D is the collector (donor) dopant concentration, assumed to be
constant and much smaller than base dopant concentration N.sub.A except in
the immediate vicinity of the collector-base junction,
.mu..sub.n, which equals D.sub.n q/kT, is the electron mobility,
q is the electronic charge,
k is Boltzmann's constant
T is the absolute temperature,
.epsilon..sub.0 is the permittivity of free space, and
K.sub.S is the relative permittivity of silicon.
Use of t.sub.BEFF in the dopant integral (in each) of Eqs. 2 and 4
indicates that this integral is taken across the quasi-neutral region of
the intrinsic base--i.e., the region extending between the two depletion
regions. The dopant integral in Eqs. 2 and 4 is commonly referred to as
the Gummel number. The dopant integral in Eqs. 3 and 5 is taken across the
full metallurgical thickness of the base as indicated by the use of
t.sub.B in this integral.
Eqs. 1-4 are available in prior art semiconductor literature. See: (a)
Philips, Transistor Engineering (McGraw-Hill; reprinted: Robert E. Krieger
Pub. Co., 1981), 1962, pages 298-304; (b) Warner et al, Transistor
Fundamentals for the Integrated-Circuit Engineer (John Wiley & Sons),
1983, pages 559-562; (c) Muller et al, Device Electronics for Integrated
circuits (John Wiley & Sons), 1977, pages 241-245; and (d) Grove, Physics
and Technology of Semiconductor Devices (John Wiley & Sons), 1967, pages
228-230.
Eq. 5 has been derived here based on the following approximations: (a) the
base region is totally depleted by the collector-base voltage at
punch-through and (b) the collector-base junction is sufficiently
asymmetrical to apply the single-sided abrupt approximation for the
calculation of its depletion layer thickness, and to neglect the voltage
drop on its heavily doped side. These modeling approximations are
considered to be particularly valid in high-frequency transistors.
In particular, equating the depletion layer charges in the base and
collector leads to:
##EQU2##
where X.sub.dC is the total depletion thickness on the collector side of
the collector-base junction. Assuming that x.sub.dC is approximately equal
to the total depletion thickness along the collector-base junction
according to classical pn-junction theory as provided in Grove (cited
above), one has:
##EQU3##
Substituting Eq. 7 into Eq. 6 produces Eq. 5.
If base dopant concentration N.sub.A is reduced, the dopant integral in Eq.
2 decreases along with t.sub.BEFF in Eq. 1. Collector current I.sub.C and
cutoff frequency f.sub.T thereby increase, as is desirable. However, the
dopant integrals in Eqs. 3-5 also decrease. This leads to decreases in
punch-through voltage V.sub.P and Early voltage V.sub.A and an increase in
base resistance r.sub.B, all of which are disadvantageous. It would be
desirable to increase the collector current and cutoff frequency without
degrading the punch-through voltage, Early voltage, and base resistance.
GENERAL DISCLOSURE OF THE INVENTION
The present invention furnishes a special two-dimensional intrinsic base
doping profile that enables the output current-voltage ("I-V")
characteristics to be improved in a vertical bipolar transistor. For
example, the magnitudes of the punch-through voltage and Early voltage are
considerably higher in the transistor of the invention than in an
otherwise similar bipolar transistor having the same active-region
collector current extrapolated to zero collector-to-emitter voltage as the
present transistor but lacking the special two-dimensional intrinsic base
doping profile of the invention. Alternatively, the invention enables the
collector current to be increased while maintaining the values of the
punch-through and Early voltages.
When the magnitude of the punch-through voltage is raised at constant
zero-V.sub.CE extrapolated active-region collector current in accordance
with the invention, the base resistance is typically reduced without
decreasing the cutoff frequency. Alternatively, when the invention is
employed to raise the collector current at constant punch-through voltage,
the cutoff frequency typically increases without degrading the base
resistance. In either case, the net result is a substantial improvement in
transistor performance.
The intrinsic base of the present transistor includes a main intrinsic
portion. The two-dimensional intrinsic base doping profile of the
invention is achieved with a pair of more lightly doped base portions that
encroach substantially into the intrinsic base below the main intrinsic
base portion. The two deep encroaching base portions set up a
two-dimensional charge-sharing mechanism. Part of the fixed collector
depletion charge which would otherwise couple vertically with the fixed
depletion charge in the main intrinsic portion of the base so as to cause
punch-through now couples laterally with fixed depletion charge in the two
encroaching base portions. For a given nominal base thickness, the
magnitude of the punch-through voltage thereby increases.
More particularly, the bipolar transistor of the invention is furnished
with an emitter, collector, and intervening multi-component base all
situated in a vertical arrangement in a semiconductor body. The emitter
extends to the upper surface of the semiconductor body. The main intrinsic
portion of the base is located below the emitter and above a main portion
of the collector.
As indicated above, the two base portions which encroach into the intrinsic
base have lighter doping than the main intrinsic base portion and extend
deeper into the semiconductor body than the main intrinsic base portion.
The two deep encroaching base portions are laterally separated from each
other below the main intrinsic base portion by a minimum spacing S.sub.NE
which is less than three times the minimum vertical thickness t.sub.BMIN
of the base. Preferably, S.sub.NE is less than twice T.sub.BMIN. In any
case, the two encroaching base portions extend sufficiently close to each
other to set up the above-mentioned charge sharing and thereby improve the
output I-V characteristics.
Inasmuch as the two deep encroaching base portions are more lightly doped
than the main intrinsic base portion, the upper boundary of the portion of
the collector-base depletion region below the emitter extends to
substantially the same vertical position in the intrinsic base of the
present transistor as in the intrinsic base of a bipolar transistor that
lacks the two deep encroaching base portions but is otherwise the same as
the transistor of the invention. Thus, the presence of the two deep
encroaching base portions does not significantly change the effective
electrical thickness of the base. Accordingly, the cutoff frequency of the
present transistor is substantially the same as that of an otherwise
equivalent bipolar transistor that lacks the deep encroaching base
portions.
The two deep encroaching base portions can be arranged in various
configurations with respect to the emitter. When, as viewed in a direction
perpendicular to the upper semiconductor surface, the emitter is in the
shape of a stripe, the two nearest opposing edges of the deep encroaching
base portions typically extend along the length of the stripe.
Alternatively, the two nearest opposing edges of the deep encroaching base
portions can cross the stripe, typically at a right angle. The transistor
can also be furnished with one or more additional emitters and one or more
additional encroaching base portions.
In fabricating the transistor of the invention, the following steps are
performed on a surface-adjoining major region of a first conductivity type
in a semiconductor body. Dopant of a second conductivity type opposite to
the first conductivity type is introduced into the major region through
its upper surface to define a first base layer of the second conductivity
type. Dopant of the first conductivity type is introduced into the major
region through a segment of its upper surface to define the emitter as a
region of the first conductivity type overlying a main intrinsic portion
of the first base layer. Further dopant of the second conductivity type is
introduced into the major region through laterally separated segments of
its upper surface. During this step, part of the further dopant is driven
sideways and downwards to form the two deep encroaching base portions as
regions of the second conductivity type.
The three dopant-introduction steps can be initiated in various orders.
Typically, these three steps are performed at least partially in parallel.
In one embodiment of the present method, the step of introducing the
further dopant to form the two deep encroaching base portions is initiated
after initiating the other two dopant-introduction steps. In this case,
the further dopant is typically implemented with a semiconductor impurity
which diffuses through the major region at a faster rate than the dopants
used in the other two dopant-introduction steps. When the first and second
conductivity types respectively are n-type and p-type, aluminum is
preferably utilized as the fast-diffusing impurity. Consequently, the
locations of the encroaching base portions can be established without
significantly affecting the locations of the emitter and the main
intrinsic base portion. During the driving of the further dopant, spacers
provided along an emitter contact are typically used to control the
locations of the encroaching base portions.
Alternatively, the step of introducing the further dopant can be initiated
before initiating the emitter dopant-introduction step.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional front view of a conventional vertical bipolar
transistor.
FIGS. 2a and 3a are simplified one-dimensional diagrams of a bipolar
transistor respectively in normal operation and in a punch-through
condition.
FIGS. 2b and 3b are graphs for potential as a function of distance for the
simplified transistor of FIGS. 2a and 3a respectively during normal
operation and punch-through.
FIG. 4 is a graph of collector current as a function of
collector-to-emitter voltage for indicating the Early voltage.
FIG. 5 is a cross-sectional front view of a vertical bipolar transistor
that contains a pair of deep encroaching base portions in accordance with
the invention.
FIG. 6 is a three-fold magnification of a portion of FIG. 5 generally
centering around the main intrinsic base portion.
FIG. 7 is a layout view for the transistor of FIG. 5. The cross section of
FIG. 5 is taken through plane 5-5 in FIG. 7.
FIG. 8 is a stepped cross-sectional side view for the transistor of FIG. 5.
The cross section of FIG. 8 is taken through stepped plane 8--8 in FIGS. 5
and 7. The cross section of FIG. 5 is further taken through plane 5--5 in
FIG. 8.
FIG. 9 is a graph of dopant concentration as a function of depth for an
implementation of the transistor of FIG. 5.
FIG. 10 is a cross-sectional front view of a simplified vertical bipolar
transistor provided with a pair of deep encroaching base portions in
accordance with the invention for use in computer simulation.
FIGS. 11a and 11b are graphs for dopant concentration as a function of
depth for the encroached-base transistor of FIG. 10.
FIG. 12 and 13 are three-dimensional graphs of the doping surfaces
respectively for the encroached-base transistor of FIG. 10 and a simulated
baseline transistor.
FIG. 14 is a graph for dopant concentration as a function of depth for two
simulated transistors in a baseline simulation group. The two simulated
transistors in FIG. 14 have the extreme dopant profiles considered in the
baseline simulation group.
FIG. 15 is a graph for collector current as a function of
collector-to-emitter voltage for all the simulated transistors in the
baseline simulation group.
FIGS. 16a, 16b, and 16c are graphs illustrating lines of constant potential
for different values of collector-to-emitter voltage in the
encroached-base transistor of FIG. 10.
FIGS. 17a, 17b, and 17c are graphs for current flow at different values of
collector-to-emitter voltage in the encroached-base transistor of FIG. 10.
FIGS. 18 and 19 are graphs for current flow, both electrons and holes,
respectively for the encroached-base transistor of FIG. 10 and the
simulated baseline transistor.
FIGS. 20 and 21 are graphs for the potential surfaces respectively for the
encroached-base transistor of FIG. 10 and the simulated baseline
transistor.
FIG. 22 is a graph for potential as a function of depth for the
encroached-base transistor of FIG. 10 and the simulated baseline
transistor.
FIGS. 23 and 24 are graphs for collector current as a function of
collector-to-emitter voltage for the encroached-base transistor of FIG. 10
and the simulated baseline transistor for respective situations in which
impact ionization is absent and present.
FIGS. 25 and 26 are three-dimensional graphs of the electric field surfaces
respectively for the encroached-base transistor of FIG. 10 and the
simulated baseline transistor.
FIG. 27 is a graph for collector current as a function of
collector-to-emitter voltage for the encroached-base transistor of FIG. 10
and all the transistors in the baseline simulation group.
FIGS. 28a, 28b, 28c, 28d, 28e, and 28f are cross-sectional front views
representing steps in a process for manufacturing the transistor of FIG. 5
in accordance with the invention.
FIG. 29 is a cross-sectional front view representing a step that can be
substituted into the process of FIGS. 28a-28f for manufacturing a vertical
bipolar transistor in accordance with the invention.
FIGS. 30, 32, 33, and 35 are partial transistor layout views for extensions
of the layout of FIG. 7 in accordance with the invention.
FIG. 31 is a cross-sectional front view through plane 31--31 in FIG. 30.
FIG. 34 is a cross-sectional side view through plane 34--34 in FIGS. 33 and
35.
FIGS. 36, 37, 38, and 39 are partial mask layout views respectively
corresponding to the partial transistor layout views of FIGS. 30, 32, 33,
and 35.
Dashed lines generally indicate boundaries between regions of the same
conductivity type but of substantially different dopant concentration. In
the drawings containing depletion regions, dotted lines generally indicate
the locations of the depletion regions. The metallurgical interface
between substrate and epitaxial layer is indicated by dot-and-dash lines
in the drawings.
Like reference symbols are employed in the drawings and in the description
of the preferred embodiments to represent the same or very similar item or
items.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIGS. 5-8 illustrate a narrow-emitter vertical npn transistor structure
configured according to the teachings of the invention so as to improve
the output I-V characteristics. In particular, the magnitudes of
punch-through voltage V.sub.P and Early voltage V.sub.A are both greater
in the transistor of FIGS. 5-8 than in an otherwise identical bipolar
transistor that has either the same extrapolated active-region collector
current at zero collector-to-emitter voltage or the same minimum base
thickness but lacks the enhancements of the invention. Also, the base
resistance r.sub.B is typically reduced in the transistor of FIGS. 5-8
without impairing the transistor cutoff frequency f.sub.T.
The cross-sectional views of FIGS. 5 and 8 are taken through planes 5--5
and 8--8 in the transistor layout view of FIG. 7. FIG. 6 is a
magnification of the portion of FIG. 5 centered generally around the
intrinsic base.
The transistor of FIGS. 5-8 has an emitter, collector, and intervening
base. These elements are created from a semiconductor body consisting of a
(100) lightly doped p-type monocrystalline silicon semiconductor substrate
50 and an overlying moderately doped n-type epitaxial silicon layer 52. P-
substrate 50 has an average net dopant concentration of 2.times.10.sup.14
-6.times.10.sup.14 atoms/cm.sup.3, typically 4.times.10.sup.14
atoms/cm.sup.3. N epitaxial layer 52 has an average net dopant
concentration of 1.times.10.sup.16 -4.times.10.sup.16 atoms/cm.sup.3,
typically 2.times.10.sup.16 atoms/cm.sup.3. The thickness of epitaxial
layer 52 is 0.9-1.2 m, typically 1.0 .mu.m.
A patterned electrically insulating field region 54 of silicon oxide is
recessed into the semiconductor body along the upper surface of n
epitaxial layer 52. Field-oxide region 54 typically extends fully through
epitaxial layer 52 and slightly into p- substrate 50 so as to divide layer
52 into a group of laterally separated active semiconductor device
regions. Two such active device regions are shown in FIG. 5. The lateral
dimension of the portion of field oxide 54 lying between these two device
regions is not drawn to scale in FIG. 5.
A very heavily doped buried n-type layer 56 situated along the
metallurgical interface between substrate 50 and layer 52 electrically
interconnects the two active device regions shown in FIG. 5. Buried n++
layer 56 has a maximum net dopant concentration of 2.times.10.sup.19
-8.times.10.sup.19 atoms/cm.sup.3, typically 4.times.10.sup.19
atoms/cm.sup.3.
The transistor's emitter is a very heavily doped n-type zone 58 situated in
the left-hand active region along the upper surface of the semiconductor
body. N++ emitter 58 reaches a maximum net dopant concentration of
1.times.10.sup.20 -4.times.10.sup.20 atoms/cm.sup.3, typically
2.5.times.10.sup.20 atoms/cm.sup.3,at the upper semiconductor surface
Emitter 58 extends to a depth d.sub.E of 0.09-0.11 .mu.m, typically 0.10
.mu.m, into epitaxial layer 52. Emitter depth d.sub.E is also the emitter
thickness (corresponding to emitter thickness t.sub.E in the
one-dimensional representation of FIG. 2a). The lateral width W.sub.E of
emitter 58 is 0.5-0.7 .mu.m, typically 0.6 .mu.m.
An overlying very heavily doped n-type polysilicon emitter contact 60
coated with a thin metal silicide cap 62 contacts emitter 58 in a
self-aligned manner. Polysilicon emitter contact 60 has a lateral width
W.sub.ECONT of 0.45-0.55 .mu.m, typically 0.5 .mu.m.
The base of the transistor consists of a heavily doped p-type intrinsic
base layer 64, a pair of moderately doped deep p-type encroaching base
portions 66, and a pair of very heavily doped p-type extrinsic base
contact zones 68 respectively corresponding to encroaching base portions
66. Components 64-68 are divided into an intrinsic base and a pair of
extrinsic bases located symmetrically on opposite sides of the intrinsic
base.
The intrinsic part of the base lies directly below n++ emitter 58 so that
the lateral width W.sub.IB of the intrinsic base is the same as emitter
width W.sub.E. Portions of components 64 and 66 form the intrinsic base.
P+ base layer 64 extends fully across the left-hand active semiconductor
region in FIG. 5 and reaches a maximum net dopant concentration of
2.times.10.sup.18 -8.times.10.sup.18 atoms/cm.sup.3, typically
5.times.10.sup.18 atoms/cm.sup.3, at the upper semiconductor surface.
Layer 64 extends to a depth d.sub.IB of 0.18-0.24 .mu.m, typically 0.20
.mu.m, into n epitaxial layer 52.
P base portions 66 extend deeper into n epitaxial layer 52 than p+ base
layer 64 and have a lighter doping concentration than p layer 64. In
particular, p portions 66 reach a maximum net dopant concentration of
1.times.10.sup.17 -4.times.10.sup.17 atoms/cm.sup.3, typically,
2.times.10.sup.17 atoms/cm.sup.3, along the bottom of layer 64 outside the
intrinsic base. Each portion 66 extends to a depth d.sub.DB of 0.4-0.6
.mu.m, typically 0.45 .mu.m, into epitaxial layer 12 outside the intrinsic
base. FIG. 9 illustrates a typical doping profile for the transistor of
FIG. 5 except for p++ base contact zones 68.
A main portion 64M of p+ base layer 64 directly underlies n++ emitter 58
and constitutes part of the intrinsic base. Each deep p portion 66
encroaches substantially into the semiconductor material directly below p+
main intrinsic base portion 64M to form an additional part of the
intrinsic base. The minimum thickness of the intrinsic base occurs at a
location between encroaching base portions 66 and is also the minimum
thickness t.sub.BMIN of main intrinsic base portion 64M. Inasmuch as
t.sub.BMIN equals d.sub.IB -d.sub.E, t.sub.BMIN equals 0.08-0.12 .mu.m,
typically 0.10 .mu.m.
Deep encroa | | |
