 |
Claims  |
|
|
What is claimed is:
1. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
a semiconductor film that forms an active region (channel-forming region)
of said thin film transistor comprises the same layer of a semiconductor
film as that of an intrinsic region (I-layer) of said thin film diode, and
a concentration of a catalyst element for promoting crystallization of
semiconductor contained in source and drain regions of said thin film
transistor is higher by more than one digit than that in the active region
of said thin film transistor.
2. A semiconductor circuit as defined in claim 1, wherein the concentration
of the catalyst element in the source and the drain regions is
1.times.10.sup.17 cm.sup.-3 or higher and less than 1.times.10.sup.20
cm.sup.-3.
3. A semiconductor circuit as defined in claim 2, wherein the concentration
of the catalyst element is defined by a minimum value obtained by
secondary ion mass spectroscopy.
4. A semiconductor circuit as defined in claim 1, wherein the catalyst
element is at least one of nickel, iron, cobalt and platinum.
5. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
source and drain regions of said thin film transistor, and an n-type region
and a p-type region of said thin film diode substantially comprises
crystalline semiconductor, and an active region (channel-forming region)
of said thin film transistor and an intrinsic region (I-layer) of said
thin film diode substantially comprise amorphous semiconductor.
6. A semiconductor circuit as defined in claim 5, wherein a semiconductor
film that forms the active region of the thin film transistor comprises
the same layer of a semiconductor film as that of the intrinsic region of
said thin film diode.
7. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
a semiconductor film that forms an active region (channel-forming region)
of said thin film transistor comprises the same layer of a semiconductor
film as that of an n-type region, a p-type region and an intrinsic region
(I-layer) of said thin film diode, and
a concentration of a catalyst element for promoting crystallization of
semiconductor contained in a source region and a drain region of the thin
film transistor is at 1.times.10.sup.17 cm.sup.-3 or higher and less than
2.times.10.sup.20 cm.sup.-3.
8. A semiconductor circuit as defined in claim 7, wherein the concentration
of the catalyst element is defined by a minimum value obtained by
secondary ion mass spectroscopy.
9. A semiconductor circuit as defined in claim 7, wherein the catalyst
element is at least one of nickel, iron, cobalt and platinum.
10. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
a source region and a drain region of said thin film transistor
substantially comprise crystalline semiconductor and an n-type region and
a p-type region of said thin film diode substantially comprise amorphous
semiconductor.
11. A semiconductor circuit as defined in claim 10, wherein a semiconductor
film that forms an active region (channel-forming region) of the thin film
transistor comprises the same layer of a semiconductor film as that of the
n-type region, the p-type region and an intrinsic region (I-layer) of said
thin film diode.
12. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
a semiconductor film that forms an active region (channel-forming region)
of said thin film transistor comprises the same layer of a semiconductor
film as that for an n-type region, a p-type region and an intrinsic region
(I-layer) of said thin film diode, and
a concentration of a catalyst element for promoting crystallization of
semiconductor contained in the active region of the thin film transistor
is at 1.times.10.sup.17 cm.sup.-3 or higher and less than
2.times.10.sup.20 cm.sup.-3.
13. A semiconductor circuit as defined in claim 12, wherein the
concentration of the catalyst element is defined by a minimum value
obtained by secondary ion mass spectroscopy.
14. A semiconductor circuit as defined in claim 12, wherein the catalyst
element is at least one of nickel, iron, cobalt and platinum.
15. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
an active region of said thin film transistor substantially comprises
crystalline semiconductor and
an intrinsic region of said thin film diode substantially comprises
amorphous semiconductor.
16. A semiconductor circuit as defined in claim 15, wherein a semiconductor
film that forms the active region of the thin film transistor comprises
the same layer of a semiconductor film as that of an n-type region, a
p-type region and the intrinsic region of said thin film diode.
17. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
a semiconductor film that forms an active region (channel-forming region)
of said thin film transistor is the same layer of a semiconductor film as
that of an intrinsic region (I-layer) of said thin film diode, and
a concentration of a catalyst element for promoting crystallization of
semiconductor contained in the active region of the thin film transistor
and the intrinsic region of said thin film diode is at 1.times.10.sup.17
cm.sup.-3 or higher and less than 2.times.10.sup.20 cm.sup.-3.
18. A semiconductor circuit as defined in claim 17, wherein the
concentration of the catalyst element is defined by a minimum value
obtained by secondary ion mass spectroscopy.
19. A semiconductor circuit as defined in claim 17, wherein the catalyst
element is at least one of nickel, iron, cobalt and platinum.
20. A semiconductor circuit as defined in claim 17, wherein an amorphous
semiconductor film is disposed in an intimate contact with the intrinsic
region of the thin film diode.
21. A semiconductor circuit as defined in claim 20, wherein an element for
changing a wavelength dependence of photosensitivity is added to the
amorphous semiconductor film.
22. A semiconductor circuit having at least one thin film transistor and at
least one thin film diode formed on a substrate, wherein
a width (channel length) of an active region (channel-forming region) of
said thin film transistor is shorter than a width of an intrinsic region
of said thin film diode,
the active region of said thin film transistor substantially comprises
crystalline semiconductor and
at least a portion of the intrinsic region of said thin film diode
comprises amorphous semiconductor.
23. A semiconductor circuit as defined in claim 22, wherein a semiconductor
film that forms the active region of the thin film transistor is the same
layer of a semiconductor film as that of the intrinsic region (I-layer) of
the thin film diode.
24. A semiconductor device having at least one thin film diode formed on a
substrate, wherein
said thin film diode includes an amorphous semiconductor film at least a
portion of which is crystallized by a catalyst element.
25. A semiconductor device as defined in claim 24, wherein an n-type region
and a p-type region of the thin film diode are formed in an identical
amorphous semiconductor film and have a planer structure. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device/circuit having at
least partially crystallized semiconductor layer and a manufacturing
method thereof. The semiconductor device/circuit manufactured according to
the present invention is formed on any of insulation substrates such as
glass substrates and semiconductor substrates such as single crystal
silicon substrates. In particular, the present invention relates to a
semiconductor device/circuit having a thin film transistor (TFT) and/or a
thin film diode (TFD) (for example, image sensor) manufactured by way of
crystallization (activation) through heat annealing.
2. Description of the Prior Art
Thin film semiconductor devices such as TFT and TFD are classified into
amorphous devices and crystalline devices depending on the crystalline
structures of the semiconductor materials used. Amorphous silicon can be
fabricated at a low temperature and shows excellent mass productivity.
However, it is inferior to crystalline silicon in view of physical
properties such as field effect mobility or conductivity. So it has been
demanded for crystalline semiconductor devices in order to obtain hiEh
speed characteristics. On the other hand, it has been known that amorphous
semiconductors are usable, for example, to light sensors since they
generally show large change in the photoconductivity. It has been proposed
recently a circuit for driving a light sensor using an amorphous silicon
diode or a thin film diode by a thin film transistor using crystalline
silicon capable of high speed operation ( for example, integrated image
sensor circuit).
FIGS. 1A-1E show an example for the steps of fabricating a circuit
comprising a combination of an amorphous silicon diode and a crystalline
silicon TFT in the prior art. An underlying insulation film 51 is formed
on a glass substrate 50, over which an amorphous silicon film is formed
and crystallized by applying long time annealing at a temperature higher
than 600.degree. C. Then, it is patterned to obtain an island-like silicon
region 52. Then, a gate insulation film 53 is formed and, further, gate
electrodes 54N and 54P are formed (refer to FIG. 1A).
Then, an N-type impurity region 55N and a p-type impurity region 55P are
formed by using known CMOS fabrication technique. In this impurity
introduction step, an impurity element is introduced into a semiconductor
layer with a gate electrode as a mask in a self-aligning manner. After the
implantation of impurities, the impurities are activated by laser
annealing, heat annealing or like other means (refer to FIG. 1B).
Then, a first interlayer insulator 58 is formed through which contact holes
are formed, thereby forming electrode/wiring 57a, 57b, 57c for source and
drain of TFT, and an electrode 57d for an amorphous silicon diode (FIG.
1C).
Then, p-, I- (intrinsic) and N-type amorphous silicon films 58P, 58I and
58N are successively laminated, which are then patterned to form a diode
junction portion (FIG. 1D).
Finally, a second interlayer insulator 59 is formed through which contact
holes are formed thereby forming an electrode 60 of the amorphous silicon
diode to complete a circuit (FIG. 1E).
In the prior art method requiring such procedures, it is necessary to form
silicon films 52, 58I and the interlayer insulators 56, 59 each by two
layers, which requires film formation for long time and, in addition, the
N-type layer 58N and the p-type layer 58P have to be formed. Therefore, it
involves a problem that the throughput is reduced. Further, a plasma CVD
or vacuum CVD process used for forming such films, takes much dead time
for the maintenance of the apparatus and the presence of such additional
step further reduces the throughput.
Furthermore, since crystallization of the silicon film used in the
crystalline silicon TFT also requires a temperature higher than
600.degree. C. and needs a time as much as 24 hours or longer for
crystallization, many facilities for crystallization apparatus are
required in actual mass production, which results in enormous installation
cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique capable of
overcoming the foregoing problems by simultaneously forming a
semiconductor layer to form a TFT and a TFD using only a single interlayer
insulator, as well as crystallizing the silicon film at a temperature
lower than 800.degree. C. and in such a short period of time as causing no
substantial problems.
Another object of the present invention is to provide a method capable of
simplifying production processes and saving the number of film-forming
steps.
A further object of the present invention is to improve crystallization and
activation of amorphous silicon, in particular, in an impurity region of
TFT and TFD (source, drain or n-type or p-type region), thereby lowering
the resistivity.
A further object of the present invention is to lower the resistivity in an
impurity region by annealing at a lower temperature and for a shorter
period of time.
A further object of the present invention is to obtain crystalline silicon
by low temperature and short time annealing and then using the same to
TFT.
A further object of the present invention is to provide a semiconductor
circuit in which source, drain of TFT and N-type and p-type regions of TFD
are constituted with crystalline silicon, while an active region (channel
forming region) of TFT and an I-layer of TFD is constituted with amorphous
silicon, as well as a manufacturing method therefor.
A further object of the present invention is to provide a semiconductor
circuit in which the source, drain regions of TFT are constituted with
crystalline silicon, while an active region of TFT and TFD are constituted
with amorphous silicon, as well as a manufacturing method thereof.
A further object of the present invention is to provide a semiconductor
circuit, in which an active region of a TFT is constituted with
crystalline silicon, while an intrinsic region of a TFD is constituted
with amorphous silicon, as well as manufacturing method therefor.
A further object of the present invention is to provide a semiconductor
device/circuit in which TFT and/or TFD are formed from one semiconductor
film, as well as a manufacturing method thereof.
A further object of the present invention is to provide a method of
manufacturing a semiconductor device/circuit capable of attaining a
satisfactory light sensitivity.
A further object of the present invention is to provide a method of
manufacturing a semiconductor device/circuit capable of crystallizing an
active region not introduced with a catalyst element by laterally
proceeding crystallization.
A further object of the present invention is to provide a method of
manufacturing a semiconductor device/circuit capable of optionally
fabricating a crystalline semiconductor region, and an amorphous
semiconductor region.
A further object of the present invention is to provide a semiconductor
device/circuit containing TFT of extremely high mobility.
The primary feature of the present invention is to add a catalytic element
to a selected portion of a semiconductor film for reducing the
crystallization temperature in the selected portion and to subject the
semiconductor film to a heat annealing at such a temperature which is
enough high to crystallize the impurity added portion but not enough high
to crystallize the remaining portion of the semiconductor film, thereby,
crystallizing only the selected portion of the semiconductor film.
According to the study of the present inventor, it has been found that one
of most major problems of the amorphous silicon TFT is caused by that the
conductivity of source, drain regions is remarkably low. It has been found
that a satisfactory operation for driving a TFD is obtainable if the
conductivity of the source, drain regions of a TFT is comparable with that
of crystalline silicon. It has also been found that the problem in the
amorphous silicon TFD is attributable to that the conductivity of the
n-type and p-type regions is low.
The foregoing problems can be solved by proceeding crystallization and
activation thereby lowering the resistivity of amorphous silicon,
particularly, in impurity regions (source, drain regions or n-type and
p-type regions), of TFT and/or TFD. As a result of the studies conducted
by the present inventor, it has been found that crystallization can be
promoted by adding a trace amount of a catalyst material to a silicon film
in a substantially amorphous state thereby enabling to lower the
crystallization temperature and shorten the crystallization time. In the
present invention, the amorphous state and the substantially amorphous
state include a so-called amorphous state and an extremely degraded
crystalline state if it is present. As the catalyst element, nickel (Ni),
iron (Fe), cobalt (Co) or platinum (Pt) is suitable. Actually,
crystallization can be attained by forming a film, particles, cluster or
the like containing such a catalyst in the form of elemental metal or a
compound such as silicide in an intimate contact on or below an amorphous
silicon film or introducing such a catalyst element into the amorphous
silicon film by an ion implantation or like other method and,
subsequently, applying heat annealing at an appropriate temperature,
typically, at a temperature below 580.degree. C.
As a matter of fact, there is such a relation that the crystallization time
is shorter as the annealing temperature is higher. Further, there is also
a relation that the crystallization temperature is lower and the
crystallization time is shorter as the concentration of the catalyst
element is greater. According to the study of the present inventor, it has
been found that at least one of the elements has to be present at a
concentration of higher than 1.times.10.sup.17 cm.sup.-3, preferably
5.times.10.sup.18 cm.sup.-3. Also, depending upon the annealing
temperature and period, the catalytic element diffuses by 10-20 .mu.m and
the crystallization proceeds in a lateral direction.
On the other hand, since most of the catalyst materials described above is
not preferred for an electrical characteristics of silicon, it is
desirable that the concentration is as low as possible. According to the
study of the present inventor, it is desired that the concentration of the
catalyst material does not exceed 2.times.10.sup.20 cm.sup.-3, preferably,
1.times.10.sup.20 cm.sup.-3 in total in order to attain sufficient
reliability and characteristic, particularly, when it is utilized as an
active region. It has been found on the other hand that there is no
substantial problem in the source or drain region if the catalyst is
present relatively in a large amount. Particularly, it has been found that
the concentration of the catalyst element contained in the active region
(channel-forming region) of TFT is desirably smaller by more than one
digit as that in the source, drain regions in the first feature of the
present invention. In the same way, it is also desired in TFD that the
concentration of the catalyst element contained in the intrinsic region
(I-layer) is lower by more than one digit than that in the impurity region
(n-type or p-type region).
Further, it should be noted that the amorphous state can be maintained
without proceeding crystallization at all in such a region that the
catalyst material is not present. For instance, crystallization of
amorphous silicon not having such a catalyst material, usually starts at a
temperature higher than 600.degree. C. but it does not proceed at all at a
temperature lower than 580.degree. C. However, since hydrogen necessary
for neutralizing dangling bonds in amorphous silicon is dissociated, in an
atmosphere at a temperature higher than 300.degree. C., it is desirable
that annealing is applied in a hydrogen atmosphere in order to attain a
satisfactory light sensitivity.
Further, such a catalyst element has an effect of crystallizing a
peripheral area by diffusion during annealing. For instance, when
annealing is applied at 550.degree. C. for four hours, the catalyst
element diffuses to the periphery as far as by 10-20 .mu.m to cause
crystallization therein. Accordingly, if the width of the gate electrode
of TFT is less than 20 .mu.m, preferably, less than 10 .mu.m,
crystallization proceeds laterally, and an active region (channel-forming
region) not introduced with the catalyst element can also be crystallized
by introducing the catalyst element into the source, drain regions before
or after introduction of the n-type or p-type impurities and then applying
annealing. Further, in this method, the concentration of the catalyst
element in the active region is generally low as compared with the
concentration of the catalyst element in the source, drain regions. The
lateral crystallization depends on the temperature and the time of
annealing and the concentration of the catalyst element. Accordingly, the
crystalline silicon region and the amorphous silicon region can be
prepared optionally by optimizing them.
For instance, when two kinds of TFT gate electrodes having, respectively, 5
.mu.m and the 30 .mu.m width are provided, it is possible to prepare a
crystalline silicon TFT from the 5 .mu.m width electrode, while an
amorphous silicon TFT from the 30 .mu.m width electrode.
Taking notice on the effect of the catalyst element and by utilizing the
same, the present inventor has succeeded in lowering the resistivity in
the impurity region by low temperature and short time annealing thereby
obtaining crystalline silicon and using it for TFT.
In the first feature of the present invention, only the impurity region is
crystallized and activated by taking an advantageous feature of the
crystallization due to the catalyst material while the active region of
TFT and the intrinsic region of TFD are left as they are in the amorphous
state, thereby improving the function of the device. The present inventor
has made a further study and has found a method capable of simplifying the
process, that is, saving the number of film-forming steps as other object
described above. The outline of the method is shown below.
(1) Formation of an amorphous semiconductor (silicon) film
(2) Formation of an insulation film (gate insulation film)
(8) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example by ion implantation or ion
doping method)
(4') Formation or catalyst element-containing material on a semiconductor
(silicon) film
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(6) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT, or alternatively.
(1) Formation of an amorphous semiconductor (silicon) film
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(4') Introduction of catalyst element (for example by ion implantation or
ion doping method)
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(6) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT.
In the second feature of the present invention, only the impurity region of
TFT is crystallized and activated by taking an advantageous feature of the
crystallization due to the catalyst material while TFD is left as it is in
the amorphous state thereby improving the function of the device. The
present inventor has made a further study and has found a method capable
of simplifying the process, that is, saving the number of film-forming
steps as other object described above. The outline of the method is shown
below.
(1) Formation of an amorphous semiconductor (silicon) film
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(4') Formation of catalyst element-containing material on the semiconductor
(silicon) film in the TFT region
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(6) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT, or, alternatively,
(1) Formation of an amorphous semiconductor (silicon) film
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(4') Introduction of catalyst element into the semiconductor (silicon) film
in the TFT region (for example, by ion implantation or ion doping method)
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(6) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT.
In the third feature of the present invention, only the TFT is crystallized
and activated by taking an advantageous feature of crystallization due to
the catalyst material while TFD is left as it is in the amorphous state
thereby improving the function of the device. The present inventor has
made a further study and found a method capable of simplifying the
process, that is, saving the number of film-forming steps as other object
described above. The outline of the method is shown below.
(1) Formation of an amorphous semiconductor (silicon) film
(1') Formation of a catalyst element-containing material on or in contact
with a semiconductor (silicon) film in the TFT region
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(8) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT or, alternatively,
(1) Formation of an amorphous semiconductor (silicon) film
(1') Introduction of a catalyst element into the semiconductor (silicon)
film in the TFT region (for example, by ion implantation or ion doping
method)
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(6) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT.
In the fourth feature of the present invention, the present inventor has
found a method capable of simplifying the process, that is, saving the
number of film-forming steps as the object described above by
crystallizing and activating the impurity regions and the active region of
TFT and the intrinsic region of TFD at a temperature lower than that in
the prior art. The outline is shown below.
(1) Formation of an amorphous semiconductor (silicon) film
(1') Introduction of a catalyst element (for example, by ion implantation
or ion doping method) (catalyst element-containing material in the form of
a film may be provided on a silicon film)
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a mask material for a TFD
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(6) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT or, alternatively,
(1) Formation of an amorphous semiconductor (silicon) film
(2) Formation of an insulation film (gate insulation film)
(3) Formation of a TFT gate electrode and a TFD mask material
(4) Introduction of doping impurity (for example, by ion implantation or
ion doping method)
(4') Introduction of a catalyst element (for example, by ion implantation
or ion doping method) (catalyst element-containing material in the form of
a film may be provided on a silicon film)
(5) Activation of doped impurity (possible at a temperature lower than
600.degree. C. and within 8 hours)
(8) Formation of an interlayer insulator
(7) Formation of source and drain electrodes of TFT.
In the steps described above, the sequence for the steps of introducing the
doping impurity and the catalyst element conducted one after the other
(steps (4) and (4') in the first and the second features and the steps (4)
and (4') in the latter alternative steps in the fourth feature) can be
reversed. For strictly controlling the concentration of the catalyst
element, the ion implantation or like other means is desirable for the
step of introducing the catalyst element. Since the catalyst element is
present, the annealing temperature lower than 600.degree. C., typically,
lower than 550.degree. C. is sufficient for crystallization and
activation, as well as the annealing time within 8 hours, typically,
within 4 hours is sufficient. In particular, in a case where the catalyst
element is distributed homogeneously by the ion implantation or ion doping
method, crystallization proceeded extremely readily.
In the present invention, if a gate electrode is present on an active
region or a mask material is present on an intrinsic region, the catalyst
element is not brought into intimate contact with or implanted into the
active region directly in the step for introducing the catalyst element
(such as step (4') in the first and the second features of the invention).
Accordingly, characteristics of the active region and the intrinsic region
are not deteriorated.
Further, if annealing is applied under appropriate conditions for
temperature and time, crystallization proceeds from the source, drain
regions and the active region also becomes crystalline silicon. As a
result, TFT of extremely high mobility can be obtained.
Referring briefly to the structure of TFD in the present invention, the TFD
in the prior art has a laminate structure, whereas the present invention
has a feature of a planar structure. In the present invention, the active
region of TFT and the intrinsic region of TFD start from an identical
amorphous silicon film. However, since the catalyst element is not
introduced in the TFD region, the region is not crystallized by the
subsequent annealing step. This is attained since the annealing
temperature in the present invention can be lowered by more than
50.degree. C. than that in the prior art. Therefore, although two layers
of silicon films have to be formed in the prior art, it is suffice to form
a single silicon film layer in the present invention. Then, the n-type
layer and the p-type layer necessary so far can be obtained by forming
them simultaneously in a planar structure upon doping impurities in TFT.
That is, the n-type region of TFD is formed upon implantation of n-type
impurities to TFT, while the p-type region of TFD is formed upon
implantation of p-type impurities to TFT. As a result, the interlayer
insulator can also be a single layer.
Such a planar TFD has a novel feature not obtainable in the prior art. In a
case of using a conventional TFD (having a shape as shown in FIG. 1), for
example, as a light sensor, the direction of an electric field generated
at the inside of the semiconductor is vertical to a light irradiation
plane, so that the light irradiation intensity is not uniform in the
direction of the electric field and it has been impossible to efficiently
generate electrons and holes and take out them externally. In addition,
short-circuit may be caused sometimes to TFD due to pinholes through the
layers. In the present invention, since the direction of the electric
field generated in TFD is in parallel with the light irradiation plane,
the light intensity is constant in the direction of the electric field to
improve photoelectric conversion efficiency and, in addition, suppress
occurrence of short-circuit.
In the present invention, a thin amorphous silicon film with a thickness of
less than 1,000 .ANG., which is not crystallized by usual heat annealing,
is also crystallized due to the effect of the catalyst element. It has
been required that the thickness of the crystalline silicon film is less
than 1,000 .ANG., preferably, less than 500 .ANG. with a view point of
avoiding pinholes or insulation failure in the gate insulation film and
disconnection of the gate electrode at stepped portions of TFT. This can
not be attained so far by the method other than laser crystallization but
this can be attained in accordance with the present invention by heat
annealing even at a low temperature. This is naturally attributable to
further improvement of the yield. In addition, in a case of utilizing TFD
as a light sensor, S/N ratio and photoelectric conversion efficiency can
be improved by using a thin semiconductor film.
According to the present invention, it is possible to save the number of
processing steps for fabricating a semiconductor device/circuit having,
for example, crystalline silicon TFT and amorphous silicon TFD and
improving the productivity. Further, in the present invention, throughput
can be improved also by crystallizing silicon, for example, at a
temperature as low as 500.degree. C. and at a processing time as short as
four hours. In addition, in a case of adopting a process at a temperature
higher than 600.degree. C. in the prior art, there has been a problem of
causing shrinkage or warp in a glass substrate which leads to the
reduction of the yield, whereas such problems can be overcome altogether
by utilizing the present invention.
This means that a substrate of a large area can be processed at a time.
That is, unit cost can be reduced remarkably by cutting out a number of
integrated circuits, etc. from a single substrate by processing a
substrate of a large area. Thus, the present invention is of an industrial
advantage.
These and other novel features and advantages of the present invention are
described in or will become apparent from the following detailed
description of preferred embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
The preferred embodiments will be described with reference to the drawings,
wherein like elements have been denoted throughout the figures with like
reference numerals, and wherein:
FIGS. 1A-1E are cross sectional views illustrating an example of
fabrication steps in the prior art;
FIGS. 2A-2F are cross sectional views illustrating fabrication steps in
Example 1 of the first feature of the present invention;
FIGS. 3A-2F are cross sectional views illustrating fabrication steps in
Example 2 of the first feature of the present invention;
FIGS. 4A-2E are cross sectional views illustrating fabrication steps in
Example 3 of the second feature of the present invention;
FIGS. 5A-5F are cross sectional views illustrating fabrication steps in
Example 4 of the second feature of the present invention;
FIGS. 6A-6E are cross sectional views illustrating fabrication steps in
Example 5 of the third feature of the present invention;
FIGS. 7A-7F are cross sectional views illustrating fabrication steps in
Example 6 of the third feature of the present invention;
FIGS. 8A-8F are cross sectional views illustrating fabrication steps in
Example 7 of the fourth feature of the present invention;
FIG. 9A is a cross sectional view of a TFD obtained in the previous
example;
FIG. 9B is a band diagram of the TFD;
FIG. 9C is a cross sectional view illustrating a modified embodiment of the
TFD; and
FIGS. 10A-10F are cross sectional views illustrating fabrication steps in
Example 8 of the fourth feature of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Description will be made more specifically to the present invention by way
of examples.
Example 1
FIGS. 2A-F illustrate cross sectional views for fabrication steps in
Example 1 of the first feature according to the present invention. At
first, an underlying film 11 made of silicon oxide was formed to a
thickness of 2,000 .ANG. by a sputtering method on a substrate (Corning
(Trademark) 7059) 10. Further, an intrinsic (I) amorphous silicon film was
deposited to a thickness of 500 to 1,500 .ANG., for example, 1,500 .ANG.
by a plasma CVD process. Then, the thus obtained amorphous silicon film
was patterned by photolithography to form an island-like silicon regions
14a (for TFT) and 14b (for TFD). Further, a silicon oxide film 15 was
deposited to a thickness of 1,000 .ANG. as a gate insulation film by a
sputtering method. Sputtering was applied using silicon oxide as a target,
at a substrate temperature of 200.degree. to 400.degree. C., for example,
at 250.degree. C. in a sputtering atmosphere of oxygen and argon at an
argon/oxygen ratio of 0 to 0.5, for example, less than 0.1. Successively,
a silicon film (containing 0.1 to 2% phosphorus) was deposited to a
thickness of 6,000 to 8,000 .ANG., for example, 6,000 .ANG. by a vacuum
CVD process. The steps of forming the silicon oxide and the silicon film
are desirably conducted continuously. Then, the silicon film was patterned
to form gate electrodes 16a and 16b for TFT and a mask material 16c for
| | |
