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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor substrate,
especially, a thin film transistor substrate of, for example, a liquid
crystal display device of active matrix type using thin film transistors,
a liquid crystal display panel and a liquid crystal display device.
2. Description of Related Art
In a liquid crystal display device of active matrix type, non-linear
elements (e.g., switching elements) are disposed in a manner to correspond
to a plurality of pixel electrodes arranged in matrix, respectively. The
liquid crystal in each pixel is always driven, in principle, (at a duty
ratio of 1.0). Therefore, in comparison with the so-called "simple matrix
type" which employs a time division driving system, the active system has
better contrast and has become an indispensable technique particularly in
a color liquid crystal display device. A typical example of the switching
element is a thin film transistor (TFT).
In a conventional thin film transistor substrate of a liquid crystal
display device of active matrix type, pure Al, Al-Pd or Al-Si is used as a
material of the scanning signal lines and the gate electrodes, and an
anodized oxide layer of Al is formed on the scanning signal lines and gate
electrodes.
Examples of a liquid crystal display devices of active matrix type using
the thin film transistors are shown in JP-A-2-85826 or on pp. 193 to 210
of Nikkei Electronics entitled "Active Matrix Type Color Liquid Crystal
Display of 12.5 Type Adopting Redundant Construction" and issued on Dec.
15, 1986 by NIKKEI McGRAW-HILL.
Other prior art examples are shown U.S. Pat. No. 5,132,820 (Someya et al),
U.S. Pat. No. 4,786,148 (Sekimura et al) and JP-A-62-269120. None of them,
however, give a description of an arrangement wherein a scanning signal
line and a gate electrode are made of an alloy of Al and an insulating
film formed of an anodized oxide film of the scanning signal line or the
gate electrode is formed on the surface of at least one of the scanning
signal line and the gate electrode.
U.S. Pat. No. 5,028,122 (Hamada et al) and JP-A-2-106723 (Nagase) resemble
the present invention in point of describing an arrangement wherein a gate
electrode is made of Ta and an insulating film formed of an anodized oxide
film of the gate electrode is formed on the surface of the gate electrode.
However, these references fail to give a description of an alloy of Al and
Ta being used in a gate electrode to provide a higher insulating property
of the anodized oxide film than that obtained when Ta is used. In the
present invention one of the features is that a scanning signal line and a
gate electrode are made of an Al and Ta alloy and an anodized oxide film
of the scanning signal line or the gate electrode is formed on the surface
of at least one of the scanning signal line and the gate electrode to
thereby obtain a higher anodized oxide film insulating characteristic than
that obtained with Ta, as shown in FIG. 17.
In a thin film transistor substrate using pure Al as a material of a
scanning signal line and a gate electrode, a hillock occurs; in a thin
film transistor substrate using Al-Pd as a material of a scanning signal
line and a gate electrode, a hillock occurs and besides an anodized oxide
film has a low breakdown voltage; and in a thin film transistor substrate
using Al-Si as a material of a scanning signal line and a gate electrode,
a residue is generated after etching. Accordingly, in any of the above
thin film transistor substrates, the fabrication yield and reliability are
degraded and the production process becomes complicated for the purpose of
improving the fabrication yield, thus raising the cost of production.
SUMMARY OF THE INVENTION
The present invention is directed to solving the aforementioned problems,
and it is an object of this invention to provide high-fabrication yield
and a highly reliable thin film transistor substrate, a liquid crystal
display panel and a liquid crystal display device.
To accomplish the above object, according to the present invention, in a
thin film transistor substrate in which an anodized oxide film of Al is
formed on at least one of a scanning signal line and a gate electrode,
Al-Ta or Al-Ti is used as a material of the scanning signal line and the
gate electrode. The breakdown voltage of the anodized oxide film is
important. As a result of experiments conducted in connection with the
breakdown voltage, the present inventors determined that when a material
which cannot be anodized (for example, Pd or Si) is used as a material to
be added to Al, the resulting oxide film has a low breakdown voltage. On
the other hand, when a material which can be anodized (for example, Ta or
Ti) is added, the resulting oxide film has a remarkably high breakdown
voltage. The thickness of the anodized oxide film is set to 1,000
angstroms or more.
In this case, a material containing Cr is used for a gate terminal
connected to the scanning signal line.
Al-Ta or Al-Ti is used as a material of the gate terminal connected to the
scanning signal line, the side of the gate terminal is covered with an
insulating film and the top of the gate terminal is covered with another
conductive film.
The additive amount of Ta or Ti in the Al-Ta or Al-Ti is 0.5 to 2.5 at %
(atomic percentage; a ratio of the number of added atoms to the number of
total atoms in a certain volume).
A different insulating film is formed on the anodized oxide film formed on
the gate electrode.
In this case, a silicon nitride film is used as the different insulating
film.
Al-Ta or Al-Ti is used as a material of the video signal line.
Amorphous silicon hydride is used as a material of an active layer of the
thin film transistor.
The anodized oxide film, a different insulating film and an amorphous
silicon hydride film are formed between the scanning signal line and the
video signal line.
The anodized oxide film and different insulating film are used as a
dielectric film of a latching capacitor.
The anodized oxide film is used as the dielectric film of the latching
capacitor.
In a liquid crystal display panel having a thin film transistor substrate
in which an anodized oxide film of Al is formed on at least one of a
scanning signal line and a gate electrode, Al-Ta or Al-Ti is used as a
material of the scanning signal line and gate electrode and the thickness
of the anodized oxide film is set to 1,000 angstroms or more.
A liquid crystal display panel is provided having a thin film transistor
substrate in which an anodized oxide film of Al is formed on at least one
of a scanning signal line and a gate electrode, Al-Ta or Al-Ti is used as
a material of the scanning signal line and gate electrode and the
thickness of the anodized oxide film is set to 1,000 angstroms or more. In
conjunction with this, the invention also provides a video signal driving
circuit for applying a video signal to the liquid crystal display panel, a
scanning circuit for applying a scanning signal to the liquid crystal
display panel, and a control circuit for applying information for the
liquid crystal display panel to the video signal driving circuit and the
scanning circuit.
In the thin film transistor substrate, liquid crystal display panel and
liquid crystal display device formed using the invention, no hillock
occurs, no residue is generated after etching, the anodized oxide film has
a high breakdown voltage, and the production process does not become
complicated for the sake of improving the fabrication yield.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(A) and 1(B) present a plan view and a cross section showing the
vicinity of a connecting portion between a gate terminal GTM and a
scanning signal line GL;
FIG. 2 is a plan view showing an essential portion of one pixel of a liquid
crystal display of a color liquid crystal display device of active matrix
type, to which is applied the present invention, and the neighborhood of
the one pixel;
FIG. 3 is a cross section taken along the line 3--3 of FIG. 2 and shows one
pixel and its peripheral portion;
FIG. 4 is a cross section taken along the line 4--4 of FIG. 2 and shows a
latching capacitor Cadd;
FIG. 5 is a plan view showing an essential portion of a liquid crystal
display in which a plurality of pixels, one being shown in FIG. 2, are
arranged;
FIG. 6 is a plan view drawing only conductive film g2 and i-type
semiconductor layer AS of the pixel shown in FIG. 2;
FIG. 7 is a plan view drawing only conductive films d1, d2 and d3 of the
pixel shown in FIG. 2;
FIG. 8 is a plan view drawing only a pixel electrode layer, a
light-shielding film and a color filter layer of the pixel shown in FIG.
2;
FIG. 9 is a plan view showing an essential portion of only the pixel
electrode layer, the light-shielding film and the color filter layer of
the pixel arrangement shown in FIG. 5;
FIGS. 10(A) and 10(B) present a plan view and a cross section showing the
vicinity of a connecting portion between a drain terminal DTM and a video
signal line DL;
FIG. 11 is an equivalent circuit diagram showing a liquid crystal display
of a color liquid crystal display device of active matrix type;
FIG. 12 is an equivalent circuit diagram showing one pixel shown in FIG. 2;
FIG. 13 presents a flow chart showing sections of a pixel portion and a
gate terminal portion and shows fabrication steps A to C on the side of a
lower transparent glass substrate SUB1;
FIG. 14 presents a flow chart showing sections of the pixel portion and the
gate terminal portion and shows fabrication steps D to F on the side of
the lower transparent glass substrate SUB1;
FIG. 15 presents a flow chart showing sections of the pixel portion and the
gate terminal portion and shows fabrication steps g to I on the side of
the lower transparent glass substrate SUB1;
FIG. 16 is a graph showing breakdown voltage characteristics of anodized
oxide films;
FIG. 17 is a graph showing insulating characteristics of the anodized oxide
films; and
FIG. 18 is a section showing a gate terminal portion of another thin film
transistor substrate of liquid crystal display device according to the
invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Active Matrix Liquid Crystal Display Device
In the description which follows, the following embodiments of the present
invention will be applied to a color liquid crystal display device of
active matrix type. Incidentally, the parts having identical functions are
designated by identical reference numerals throughout all the Figures to
be referred to hereinafter and their repeated descriptions will be
omitted.
FIG. 2 is a plan view showing one pixel and its peripheral portion of the
active matrix type color liquid crystal display device to which the
present invention is applied. FIG. 3 is a section taken along the line
3--3 of FIG. 2. FIG. 4 is a section taken along the line 4--4 of FIG. 2.
On the other hand, FIG. 5 is a plan view showing the case in which a
plurality of pixels, one being shown in FIG. 2, are arranged.
Pixel Disposition
As shown in FIG. 2, each pixel is disposed in a region (surrounded by four
signal lines) defined by two adjacent scanning signal lines (e.g., gate
signal lines or horizontal signal lines) GL which cross two adjacent video
signal lines (e.g., drain signal lines or vertical signal lines) DL. Each
pixel includes a thin film transistor TFT, a transparent pixel electrode
ITO1 and a latching capacitor Cadd. The scanning signal lines GL are
extended in the column direction and arranged in plurality in the row
direction. The video signal lines DL are extended in the row direction and
arranged in plurality in the column direction.
Overall Sectional Structure of Display Unit
As shown in FIG. 3, relative to a liquid crystal layer LC, the thin film
transistor TFT and the transparent pixel electrode ITO1 are formed on the
side of a lower transparent glass substrate SUB1 and a color filter FIL
and a black matrix pattern BM for light shielding are formed on the side
of an upper transparent glass substrate SUB2. The lower transparent glass
substrate SUB1 is made to have a thickness of about 1.1 mm, for example.
On the both surfaces of each of the transparent glass substrates SUB1 and
SUB2, there are formed silicon oxide films SIO which are deposited by the
dip treatment. Accordingly, even if there exist sharp defects at the
surfaces of the transparent glass substrates SUB1 and SUB2, the sharp
defects can be covered with the silicon oxide films SIO and therefore,
film quality of the scanning signal lines GL and the light shielding film
BM to be deposited thereon can be kept to be uniform.
Although not illustrated, a seal pattern made of, for example, epoxy resin
is applied along the entire peripheral edge, excepting a liquid crystal
filling port, of each of the transparent glass substrates SUB1 and SUB2 so
that liquid crystal LC may be sealed. A common transparent pixel electrode
ITO2 on the side of upper transparent glass substrate SUB2 is connected at
least, at its part, to external outgoing wiring formed on the side of
lower transparent glass substrate SUB1, by a silver paste member. The
external outgoing wiring is formed through the same fabrication process as
that for gate terminal GTM and drain terminal DTM to be described later.
Orientation films ORI1 and ORI2, the transparent pixel electrode ITO1 and
the common transparent pixel electrode ITO2 are each formed inside the
seal pattern. Polarization plates POL1 and POL2 are formed on the outer
surfaces of the lower transparent glass substrate SUB1 and the upper
transparent glass substrate SUB2, respectively. The liquid crystal LC is
filled in a region between the lower and upper orientation films ORI1 and
ORI2 for setting the orientation of the liquid crystal molecules and is
sealed by the seal pattern. The lower orientation film ORI1 is formed on a
passivation film PSV1 on the side of the lower transparent glass substrate
SUB1.
Sequentially laminated on the inner (close to liquid crystal LC) surface of
the upper transparent glass substrate SUB2 are the light shielding film
BM, color filter FIL, passivation film PSV2, common transparent pixel
electrode ITO2 (COM) and upper orientation film ORI2.
This liquid crystal display device is assembled: by superposing the
individual layers on the side of the lower transparent glass substrate
SUB1 and the individual layers on the side of the upper transparent glass
substrate SUB2; by superposing the lower transparent glass substrate SUB1
and the upper transparent glass substrate SUB2; and by injecting the
liquid crystal LC into the region between the lower transparent glass
substrate SUB1 and upper transparent glass substrate SUB2.
Thin Film Transistor TFT
If a positive bias is applied to the gate electrode GT, the thin film
transistor TFT has its channel resistance reduced between its source and
drain. If the bias is reduced to zero, the thin film transistor TFT
operates to have its channel resistance increased.
The thin film transistor TFT of each pixel is divided into two (or
plurality) in the pixel, so that it is composed of thin film transistors
(or divided thin film transistors) TFT1 and TFT2. These thin film
transistors TFT1 and TFT2 are individually made to have a substantially
equal size (equal in the channel length and width). Each of these divided
thin film transistors TFT1 and TFT2 is composed of a gate electrode GT, a
gate insulating film GI, an i-type (i.e., intrinsic type not doped with a
conductivity type determining impurity) amorphous silicon (Si)
semiconductor layer AS, and a pair of source electrode SD1 and drain
electrode SD2. Incidentally, the source and drain are intrinsically
determined in dependence upon the bias polarity therebetween, and this
polarity is inverted during the operation in the circuit of the present
liquid crystal display device. Thus, it should be understood that the
source and drain interchange during the operation. In the following
description, however, one is fixed as the source whereas the other is
fixed as the drain, for convenience only.
Gate Electrode GT
The gate electrode Gt is formed to project perpendicularly (i.e., upward,
as viewed in FIGS. 2 and 6) from the scanning signal lines GL (or branched
in the "T-shape"), as shown in detail in FIG. 6 (presenting a plan view
showing the second conductive film g2 and i-type semiconductor layer AS of
FIG. 2 only). The gate electrode GT goes beyond the active region of each
of the thin film transistors TFT1 and TFT2. These thin film transistors
TFT1 and TFT2 have their individual gate electrodes GT integrated (as
their common gate electrode) to merge into the scanning signal line GL. In
this embodiment, the gate electrode GT is constituted by a monolayer of
the second conductive film g2.
Used as the second conductive film g2 is an Al-Ta film (the additive amount
of Ta being 1.5 at %) formed by, for example, sputtering in a thickness of
about 1,000 to 5,500 angstroms. On the gate electrode Gt, there is
provided an anodized oxide film AOF of Al and having a thickness of 1,800
angstroms.
Since in this manner the Al-Ta film is used as the second conductive film
g2, no hillock is generated, no residue remains after etching and the
anodized oxide film AOF has a high breakdown voltage, the fabrication
yield can be improved by 5%, thus promoting reliability. In addition,
since the fabrication yield can be improved without making the production
process complicated, the cost of production can be low.
When the additive amount of Ta in the Al-Ta film exceeds 0.5 at %, any
hillock and whisker are not generated at a temperature of about
300.degree. C., exhibiting excellent thermal stability. When the additive
amount of Ta in the Al-Ta film is below 2.5 at %, the second conductive
film g2 can be removed perfectly by etching, leaving behind no residue.
FIG. 16 is a graph showing breakdown voltages of anodized oxide films made
of different materials (2,000-angstrom thick). As is clear from FIG. 16,
when the materials are Al-Pd and Al-Si, the anodized oxide films have a
breakdown voltage of about 80 V, whereas when the material is Al-Ta, the
anodized oxide film has a breakdown voltage of about 140 V equal to that
of pure Al. FIG. 17 is a graph showing insulation characteristics of the
anodized oxide films, with curve a representing the case of the pure Al
anodized oxide film, curve b representing the case of the Al-Ta anodized
oxide film (the additive amount of Ta being 2.5 at %) and curve c
representing the case of the Ta anodized oxide film. As will be seen from
FIG. 17, the insulation characteristic of the Al-Ta anodized oxide film is
as excellent as that of the pure Al anodized oxide film. As the additive
amount of Ta in Al-Ta, the resistivity of the second conductive film g2
increases. But since the resistivity of a material of the scanning signal
line GL is designed to be limited to twice the resistivity of pure Al and
the resistivity of a material of the video signal line DL is designed to
be limited to five times the resistivity of pure Al, the additive amount
of Ta is desired to be 2.5 at % or less.
Then, for prevention of breakdown, the anodized oxide film AOF is designed
to have a thickness of 1,000 angstroms or more.
This gate electrode GT this made to be larger than the i-type semiconductor
layer AS so as to cover it completely (as viewed from below), as shown in
FIGS. 2 and 3 and FIG. 6. Therefore, in case back lights such as
fluorescent lamps are attached to the bottom of the lower transparent
glass substrate SUB1, this opaque Al gate electrode GT establishes a
shadow to shield the i-type semiconductor layer AS from back light, thus
substantially eliminating the conducting phenomenon due to the optical
irradiation, i.e., the deterioration of the OFF characteristics of the
thin film transistor TFT. Here, the intrinsic size of the gate electrode
GT is so determined as to have a width which can bridge, at the least, the
source electrode SD1 and drain electrode SD2 (including the positioning
tolerance between the gate electrode GT and each of the source electrode
SD1 and drain electrode SD2) and have a depth for determining channel
width W which is determined in dependence upon a factor W/L determining a
mutual conductance gm, i.e., the ratio of the depth to the distance (i.e.,
the channel length) L between the source and drain electrodes SD1 and SD2.
The size of the gate electrode GT in the liquid crystal display device is
naturally made to be larger than the aforementioned intrinsic size.
Scanning Signal Line GL
The scanning signal line GL is constituted by the second conductive film
g2. The second conductive film g2 of the scanning signal line GL is formed
through the same fabrication process as that for the second conductive
film g2 of the gate electrode GT and the former film g2 is integral with
the latter film g2. Moreover, the scanning signal line GL is also formed
thereon with the anodized oxide film AOF of Al.
Insulating Film GI
The insulating film GI is used as the gate insulating film of each of the
thin film transistors TFT1 and TFT2. The insulating film GI is formed on
the gate electrode GT and scanning signal line GL. The insulating film GI
is formed of, for example, a silicon nitride film prepared by the plasma
CVD, to have a thickness of 1,200 to 2,700 angstroms (e.g., about 2,000
angstroms in the present liquid crystal display device).
i-Type Semiconductor Layer AS
The i-type semiconductor layer AS is used as the channel forming region of
each of the divided plural thin film transistors TFT1 and TFT2, as shown
in FIG. 6. The i-type semiconductor layer As is formed of an amorphous
silicon hydride film or polycrystalline silicon film to have a thickness
of about 200 to 2,200 angstroms (e.g., about 2,000 angstroms in the
present liquid crystal display device).
This i-type semiconductor layer AS is formed successively to the formation
of an insulating film GI of Si.sub.3 N.sub.4 used as the gate insulating
film by changing components of supply gas through the use of a common
plasma CVD system, without being exposed to the outside of the plasma CVD
system. On the other hand, an N(+)type semiconductor layer d0 (shown in
FIG. 3) doped with phosphor (P) by 2.5% and used for ohmic contact is
likewise formed successively to have a thickness of about 200 to 500
angstroms (e.g., about 300 angstroms in the present liquid crystal display
device). After this, the lower transparent glass substrate SUB1 is taken
out of the CVD system, and the N(+)-type semiconductor layer d0 and the
i-type semiconductor layer AS are patterned into independent islands by
the photographic technology, as shown in FIGS. 2 and 3 and FIG. 6.
The i-type semiconductor layer As is also interposed at an intersecting
portion (or crossover portion) between the scanning signal line GL and the
video signal line DL, as shown in FIGS. 2 and 6. This i-type semiconductor
layer As at the intersecting portion is effective to reduce the
short-circuiting between the scanning signal line GL and the video signal
line DL at the intersecting portion.
Transparent Pixel Electrode ITO1
The transparent pixel electrode ITO1 constitutes one of sets of the pixel
electrodes of a liquid crystal display.
The transparent pixel electrode ITO1 is connected with both the source
electrode SD1 of the thin film transistor TFT1 and the source electrode
SD1 of the thin film transistor TFT2. Even if, therefore, one of the thin
film transistors TFT1 and TFT2 becomes defective, a suitable portion may
be cut by a laser beam in case the defect invites an adverse action; or
otherwise the situation may be left as it is because the other thin film
transistor is normally operating. Incidentally, both the two thin film
transistors TFT1 and TFT2 scarcely become defective concurrently, and the
probability of the point defect or line defect can be drastically reduced
by that redundant system. The transparent pixel electrode ITO1 is formed
of a first conductive film d1, which is made of a transparent conductive
film (of Indium-tin-Oxide, i.e., ITO or NESA film) to have a thickness of
1,000 to 2,000 angstroms (e.g., about 1,400 angstroms in the present
liquid crystal display device).
Source Electrode SD1 and Drain Electrode SD2
The source electrode SD1 and drain electrode SD2 of each of the divided
plural thin film transistors TFT1 and TFT2 are formed on the i-type
semiconductor layer AS and separately from each other, as shown in FIGS. 2
and 3 and FIG. 7 (presenting a plan view showing the first to third
conductive films d1 to d3 of FIG. 2 only).
Each of the source electrode SD1 and the drain electrode SD2 is formed by
overlaying a second conductive film d2 and a third conductive film d3
sequentially from the lower side contacting the N(+)-type semiconductor
layer d0. These second conductive film d2 and third conductive film d3 of
the source electrode SD1 are formed through the same fabrication process
as that for the second and third conductive films d2 and d3 of the drain
electrode SD2.
The second conductive film d2 is formed of a sputtered chromium (Cr) film
to have a thickness of 500 to 1,000 angstroms (e.g., about 600 angstroms
in the present liquid crystal display device). The Cr film is formed to
have a thickness not exceeding about 2,000 angstroms because it suffers
high stress if made excessively thick. The Cr film comes in good contact
with the N(+)-type semiconductor layer d0. The Cr film constitutes a
so-called "barrier layer" for preventing the Al of the third conductive
film d3 described hereinafter from diffusing into the N(+)-type
semiconductor layer d0. The second conductive film d2 may be made of not
only the aforementioned Cr film but also a refractory metal (e.g., Mo, Ti,
Ta or W) film or its silicide (e.g., MoSi.sub.2, TiSi.sub.2, TaSi.sub.2 or
WSi.sub.2).
The third conductive film d3 is formed by sputtering Al-Ta (additive amount
of Ta being 2 atomic %) to have a thickness of about 3,000 to 5,000
angstroms (e.g., about 4,000 angstroms in the present liquid crystal
display device). The Al-Ta film is less stressed than the Cr layer so that
it can be formed to have a larger thickness thereby to reduce the
resistances of the source electrode SD1, the drain electrode SD2 and the
video signal line DL.
After the second conductive film d2 and the third conductive film d3 have
been patterned with the same mask pattern, the N(+)-type semiconductor
layer d0 is removed by using the same photographic mask or by using the
second conductive film d2 and the third conductive film d3 as a mask.
Specifically, the N(+)-type semiconductor layer d0 left on the i-type
semiconductor layer AS is removed excepting a portion which is in
self-alignment with the second conductive film d2 and the third conductive
film d3. Since, during this removal, the N(+)-type semiconductor layer d0
is etched to lose its whole thickness, the i-type semiconductor layer AS
is also etched off slightly at its surface portion, but this removal may
be controlled by controlling the etching time.
The source electrode SD1 is connected with the transparent pixel electrode
ITO1. The source electrode SD1 is formed along a stepped shape (i.e., a
step corresponding to the sum of the thicknesses of the second conductive
film g2, the anodized oxide film AOF, the i-type semiconductor layer AS
and the N(+)-type semiconductor layer d0) of the i-type semiconductor laye
AS. More specifically, the source electrode SD1 is composed of the second
conductive film d2 formed along the stepped shape of the i-type
semiconductor laye AS and the third conductive film d3 formed on the
second conductive film d2. This third conductive film d3 of the source
electrode SD1 is formed to climb over the i-type semiconductor AS, because
the Cr film of the second conductive film d3 cannot be made to be so
thick, because of an increase in stress, as to climb over the stepped
shape of the i-type semiconductor laye AS. In short, the third conductive
film d3 is made to be thick to improve the step coverage. The third
conductive film d3 can be made to be thick so that it can highly
contribute to the reduction of the resistance of the source electrode SD1
(this holds true for the drain electrode SD2 and the video signal line
DL).
Passivation Film PSV1
On the thin film transistor TFT and the transparent pixel electrode ITO1,
there is formed a passivation film PSV1, which is provided mainly for
protecting the thin film transistor TFT against humidity or the like.
Thus, the passivation film PSV1 to be used is highly transparent and
humidity resistant. The passivation film PSV1 is formed of a silicon oxide
film or silicon nitride film prepared by, for example, the plasma CVD
system, to have a thickness of about 1 micron.
Light Shielding Film BM
On the side of the upper transparent glass substrate SUB2, there is
disposed the light shielding film BM for shielding any external light
(i.e., light coming from above in FIG. 3) from entering the i-type
semiconductor layer AS to be used as the channel forming region, having a
patterns as hatched in FIG. 8. Here, FIG. 8 is a plan view showing only
the first conductive film d1 comprised of the ITO film, the color filter
FIL and the light shielding film BM of FIG. 2. The light shielding film BM
is formed of a film having a high shielding property against light, e.g.,
an aluminum film or chromium film. In the present liquid crystal display
device, used as the light shielding film BM is a chromium film formed by
sputtering to have a thickness of about 1,300 angstroms.
As a result, the common i-type semiconductor layer AS shared by the thin
film transistors TFT1 and TFT2 is sandwiched between the upper light
shielding film BM and the lower, larger gate electrode GT, so that it can
be shielded from external natural light and back light. The light
shielding film BM is formed around the pixel, as hatched in FIG. 8.
Specifically, the light shielding film BM is formed in a lattice (of black
matrix) shape, which defines the effective display region of one pixel. As
a result, the contour of each pixel is clarified by the light shielding
film BM to improve the contrast. In other words, this light shielding film
BM has two functions, i.e., the function of shielding the i-type
semiconductor layer AS from light and the black matrix function.
Further, since a portion (a right below portion of FIG. 2) opposing an edge
at the foot of the transparent pixel electrode ITO1 in the rubbing
direction is shielded from light by the light shielding film BM, even if a
domain is induced at that portion, the display characteristics are hardly
deteriorated because the domain is shaded.
Incidentally, the back lights may be attached on the side of the upper
transparent glass substrate SUB2, whereas the lower transparent glass
substrate SUB1 may be used as the observation side (externally exposed
side).
Color Filter FIL
The color filter FIL is prepared by coloring a dyeing base, which is made
of a resin material such as acrylic resin, with a dye. The color filter
FIL are formed each in the shape of a stripe at a position opposing a
pixel (FIG. 9) and are dyed differently (FIG. 9 shows the first conductive
film d1, the light shielding film BM and the color filter FIL of FIG. 5
only, and the B, G and R color filters FIL are hatched at 45 degrees, at
135 degrees and in a crossing manner, respectively). The color filter FIL
is made to be slightly larger to cover the whole of the transparent pixel
electrode ITO1, as shown in FIGS. 8 and 9. The light shielding film BM is
so formed inside the peripheral edge of the transparent pixel electrode
ITO1 as to overlap edges of the color filter FIL and the transparent pixel
electrode ITO1.
The color filter FIL can be formed in the following manner. First of all,
the dyeing base is formed on the surface of the upper transparent glass
substrate SUB2, and the dyeing base is partly removed to leave behind its
region for formation of red color filter by the photolithographic
technology. After this, the dyeing base is dyed with red dye and fixed to
form the red filter R. Next, the green filter G and the blue filter B are
sequentially formed through similar steps.
Passivation Film PSV2
The passivation film PSV2 is provided for preventing the dyes used for
differently dyeing the color filters FIL from leaking into the liquid
crystal LC. The passivation film PSV2 is made of a transparent resin
material such as acrylic resin or epoxy resin.
Common Transparent Pixel Electrode ITO2
The common transparent pixel electrode ITO2 opposes the transparent pixel
electrode ITO1, which is provided for each pixel on the side of the lower
transparent glass substrate SUB1, so that the optical state of liquid
crystal lc changes in response to the potential difference (or electric
field) between each pixel electrode ITO1 and the common transparent pixel
electrode ITO2. This common transparent pixel electrode ITO2 is fed with
common voltage Vcom. The common voltage Vcom is intermediate potential
between a driving voltage Vdmin at low level and a driving voltage Vdmin
at low level and a driving voltage Vdmax at high level, both of which are
applied to the video signal line DL.
Gate Terminal GTM
FIGS. 1(A) and 1(B) present a connection structure from the scanning signal
line GL of the display matrix to a gate terminal GTM standing for its
external connection terminal, FIG. 1(A) showing a plan view and FIG. 1(B)
a cross section taken along the line B--B of FIG. 1(A). Incidentally,
FIGS. 1(A) and 1(B) depict the neighborhood of the left end of the lower
transparent glass substrate SUB1 in the matrix of FIG. 5.
Letter AO designates a photolithographic mask pattern, namely, a photo
resist pattern for selective anodization. Therefore, this photo resist is
anodized and then removed so that the shown mask pattern AO is not left as
a complete but remains as a trace because the anodized oxide film AOF is
selectively formed in the gate line GL, as shown in section. With
reference to the boundary line AO of the photo resist in the plan view,
the left hand side is a region which is covered with the resist and is not
anodized, whereas the right hand side is a region which is clear of the
resist and is anodized. The anodized second conductive film g2 has its
surface formed with its oxide Al.sub.2 O.sub.3 film or anodized oxide film
AOF and its lower conductive portion reduced in volume. Of course, the
anodization is so carried out for a proper time and at a proper voltage
that the conductive portion may be left. The mask pattern AO is made to
intersect the scanning line GL not in a straight line but in a folded
crank shape. Therefore, even if exfoliation begins at a photo resist
portion intersecting the stepped shape of the scanning signal line GL and
fusion of the second conductive film g2 due to anodization voltage takes
place, the fusion will proceed along end surface of the photo resist film
and consequently the fusion of the second co | | |
