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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a random access semiconductor memory, more
particularly to an electrically erasable programmable nonvolatile
semiconductor memory device such as a flash memory.
2. Description of the Related Art
At the present time, flash memories are coming under attention as low cost,
large capacity EEPROMs. Attempts are being made to realize ones of 16
Mbits. Further, improvements are being made so that instead of the
complete erasure as in the past, erasure of specific sectors is made
possible to thereby further increase the ease of use.
Flash memories, however, have a remarkably longer erasure time and write
time compared with the speed of the CPU to restrict excess erasure and
excess writing in addition to basic factors of writing/erasure.
At the present time, it takes 0.1 to 2 seconds for erasing 1 Mbit and 0.2
second/16 KB for writing.
A flash memory as a semiconductor memory device ideally should have no
erasure operation and should be able to perform writing at a speed
commensurate with the speed of the CPU like with an SRAM.
Also, a flash memory is limited in the number of rewriting. The number of
rewriting in the current art is about 10.sup.6 at a maximum. From the
application standpoint, however, there is a demand for use up to 10.sup.6
to 10.sup.9 times since even part of the capacity of the flash memory is
enough.
As explained above, a flash memory has a slow rewriting speed and a
durability of the number of rewriting of about 10.sup.4 to 10.sup.5.
Accordingly, in the past, there has been proposed a nonvolatile RAM (NVRAM)
comprised of an SRAM (or DRAM) and an EEPROM, coupled one-to-one in each
memory cell unit, which has the contents of the SRAM or DRAM written in
the EEPROM in accordance with need.
Further, as a semiconductor nonvolatile memory device achieving both a
higher speed of the write operation and a nonvolatile nature without the
use of a battery, as disclosed for example in Japanese Unexamined Patent
Publication (Kokai) No. 4-176091, there is known a device provided with a
flash EEPROM as a nonvolatile memory device, a DRAM as a volatile memory
device, a control circuit for making the contents of the two memory
devices match in accordance with an external signal, an internal address
bus electrically isolated from an external address bus by a signal from
the control circuit, and an internal data bus also electrically isolated
from the external data bus by a signal from the control circuit.
In this semiconductor nonvolatile memory device, data is transferred from
the flash EEPROM to the DRAM when the device is first assembled into the
processing unit. Normal reading and writing are performed with respect to
the DRAM. Upon instruction from the CPU, the contents of the DRAM are
cached in the flash EEPROM.
The conventional NVRAM, however, was comprised of an SRAM (or DRAM) and
EEPROM coupled one-to-one in memory cell units, so became larger in size
than the sum of the size of a simple DRAM (or DRAM) cell and size of an
EEPROM cell. Due to costs and other problems, further, realization of a
larger capacity was difficult.
Further, in the semiconductor nonvolatile memory device disclosed in
Japanese Unexamined Patent Publication No. 4-176091, the flash EEPROM and
DRAM are formed on different chips, so viewing the device as a whole, the
write and erasure times of the flash EEPROM are slow and the timing of the
writing and erasure and designation of commands become complicated.
SUMMARY OF THE INVENTION
The present invention was made in consideration of the above circumstances
and has as its object the provision of a semiconductor nonvolatile memory
device which is made simpler in circuit configuration, is able to perform
read and write operations at a high speed, and can store and hold data
without use of a backup power supply.
To achieve the above object, the semiconductor nonvolatile memory device of
the present invention including first and second bit lines, a buffer
memory connected to the first and second bit lines, an electrically
erasable programmable nonvolatile memory connected to the first and second
bit lines, a write latch circuit to which the first and second bit lines
are connected in parallel and having a differential sensor type sense
amplifier, and a switching circuit for switching the nonvolatile memory
and the latch circuit to a nonconnected state at the time of operation of
the buffer memory and switching the buffer memory and the latch circuit to
a nonconnected state at the time of a write or erasure operation on the
nonvolatile memory.
The semiconductor nonvolatile memory device of the present invention
preferably has at least two buffer memories and nonvolatile memories.
Further, the capacity of the buffer memory is preferably set to a whole
multiple of the size of the page to be written at one time in the
nonvolatile memory.
The semiconductor nonvolatile memory device of the present invention may
have the buffer memory comprised by a static RAM.
When the power is energized, the data may be written into and read from the
static RAM and when the power is deenergized, the data held in the static
RAM may be cached in the nonvolatile memory.
The semiconductor nonvolatile memory device of the present invention may
also have the buffer memory comprised by a dynamic RAM.
The semiconductor nonvolatile memory device of the present invention may
have the nonvolatile memory comprised of a first memory cell connected to
a word line and the first bit line, a second memory cell connected to the
word line common with the first memory cell and connected to the second
bit line, and a means for holding the potential of either of the first and
second bit lines at a first potential at a predetermined operation time
and for setting the potential of the other bit line to a second potential
given a difference with the first potential for a predetermined time.
The semiconductor nonvolatile memory device of the present invention may
also have the nonvolatile memory comprised of a plurality of memory cell
blocks connected to the first and second bit lines and have between the
memory cell blocks and bit lines two selection transistors connected in
cascade and selection gates provided to selectively connect the memory
cell blocks and bit lines.
According to the present invention, both the buffer memory and the
nonvolatile memory are of a so-called folded bit line type memory
configuration and the two are connected through the same bit line.
Further, data held in the buffer memory is latched once at a latch circuit
and then that latched data is transferred to and stored at the nonvolatile
memory.
Also, according to the present invention, by adopting a configuration in
which at least two buffer memories and nonvolatile memories are provided,
the data written in one buffer memory comprised of an SRAM or DRAM is
transferred to one of the nonvolatile memories. When writing data into the
buffer memory, the corresponding erasure units of the nonvolatile memory
are erased (first one time).
While data of another buffer memory is being transferred to the flash
memory, data is written in the first buffer memory.
Further, according to the present invention, the buffer memory may be
comprised of an SRAM. When the power is turned on, data is written into
and read from the SRAM. When the power is turned off, the data held in the
SRAM is evacuated to the nonvolatile memory.
That is, the SRAM of the buffer memory is used as an NVRAM.
Further, according to the present invention, the first and second bit lines
may be held at the same potential at the time of precharging for example,
but the second bit line is held at the first potential and the second bit
line is set to a second potential higher than the first potential when
reading from the first memory cell for example.
Further, according to the present invention, in a configuration where there
are a plurality of memory cell blocks connected to the first and second
bit lines, the state of connection between the blocks and the bit lines is
controlled by selection gates comprised of two selection transistors
connected in cascade.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and features of the present invention will become
clearer from the following description of preferred embodiments with
reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a first embodiment of a semiconductor
nonvolatile memory device according to the present invention;
FIG. 2 is a view of an example of the configuration of a DRAM cell;
FIG. 3 is a circuit diagram of an example of the configuration of a flash
memory able to adopt the folded bit line system without the use of dummy
cells;
FIG. 4 is a view of the fluctuation of the bit line voltage caused by
adjustment of the bit line voltage adjustment circuit at the time of a
read operation in the circuit of FIG. 3;
FIG. 5 is a circuit diagram of an example of the configuration of a flash
memoryable to use the folded bit line system using dummy cells;
FIGS. 6A and 6B are views of an example of the configuration of the memory
cell array of FIG. 5;
FIG. 7 is a circuit diagram of a second embodiment of a semiconductor
nonvolatile memory device according to the present invention;
FIG. 8 is a view of an example of the configuration of an SRAM cell;
FIG. 9 is a block diagram of a third embodiment of a semiconductor
nonvolatile memory device according to the present invention;
FIG. 10, comprised of FIGS. 10A and 10B is a view for explaining the
relationship between the SRAM size and write units (pages) in the circuit
of FIG. 9; and
FIG. 11 is a circuit diagram of key parts of a fifth embodiment of a
semiconductor nonvolatile memory device according to the present invention
.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The preferred embodiments of the invention will now be explained with
reference to the drawings.
FIG. 1 is a circuit diagram of a first embodiment of a semiconductor
nonvolatile memory device according to the present invention.
In FIG. 1, the MCA.sub.DRAM shows a DRAM cell array serving as a buffer
memory cell array, MCA.sub.FLS a flash memory cell array serving as the
nonvolatile memory cell array, SWG.sub.1 a first switching device group,
SWG.sub.2 a second switching device group, LTCG a latch circuit group,
BLD0 and BLD1 DRAM cell bit lines, BLD0.sub.-- an inverting bit line
taking a complementary level to the bit line BLD0, BLD1.sub.-- an
inverting bit line taking a complementary level to the bit line BLD1,
WL.sub.BF1 and WL.sub.BF2 DRAM cell array word lines, DWL.sub.1 and
DWL.sub.2 DRAM cell array dummy word lines, SEL a flash memory cell array
selection gate line, WLi a flash memory cell array word line, SLN.sub.1 a
first switching signal line, and SLN.sub.2 and SLN.sub.2-- a pair of
second switching signal lines.
The DRAM cell array MCA.sub.DRAM has a so-called folded bit line type
memory configuration, which is advantageous in terms of increasing speed.
That is, it is configured in a so-called differential (including flipflop
type) sense system with the bit lines BLD0 and BLD1 and the inverting bit
lines BLD0.sub.-- and BLD1.sub.-- taking complementary levels with the
same arranged diagonally. To produce the reference level of the
differential sense amplifier, the inverting bit lines BLD0.sub.-- and
BLD1.sub.-- at the opposite side to the side reading the data or the bit
lines BLD0 and BLD1 have arranged at them the reference dummy cells
DCL0.sub.-- and DCL1.sub.-- or DCL0 and DCL1 corresponding to the storage
cells SRG0 and SRG1 or SRG0.sub.-- and SRG1.sub.--.
The storage cells SRG0, SRG1, SRG0.sub.--, and SRG1.sub.-- and the dummy
cells DCL0, DCL1, DCL0.sub.--, and DCL1.sub.-- are each comprised, for
example, as shown in FIG. 2, of a capacitor C for storing a charge and an
nMOS transistor NT for controlling the charging and discharging of the
capacitor C. One electrode of the capacitor C is grounded or fixed to a
predetermined voltage. The other electrode is connected to the source of
the nMOS transistor NT. The drain of the nMOS transistor NT is connected
to the bit line BLD. The gate is connected to the word line WLD.
In such a configuration, if the potential of the word line is set to a high
level by X-decoder (not shown), the nMOS transistor NT is turned on and
becomes conductive and a charge is passed from the bit line BLD held to
the predetermined potential to the capacitor C.
If the level of the word line WLD is lowered to the low level, the nMOS
transistor NT is turned off and becomes non-conductive and the potential
of the bit line BLD at that time is fetched into the capacitor C. As a
result, data "1" or "0", each having the respective predetermined level,
is held.
The flash memory cell array MCA.sub.FLS is comprised of nMOS transistors,
that is, is composed of the memory transistors MT0i, MT0i.sub.--, MT1i,
and MT1i.sub.-- connected in series with the selection gates SG0,
SG0.sub.--, SG1, and SG1.sub.-- connected to the bit lines and inverting
bit lines BL0, BL0.sub.--, BL1, and BL1.sub.--. That is, for example, NAND
type memory cells are connected to the bit lines and the inverting bit
lines BL0, BL0.sub.--, BL1, and BL1.sub.--. Further, the gates of the
transistors forming the selection gates SG0, SG0.sub.--, SG1, and
SG1.sub.-- are connected to a common selection gate line SEL. The gates of
the memory transistors MT0i, MT0i.sub.--, MT1i, and MT1i.sub.-- are
connected to a common word line WLi.
Note that the flash memory in this embodiment is based on the assumption of
a memory of the Fowler-Nordheim (FN) tunnel erasure/FN tunnelwrite type.
The first switching device group SWG.sub.1 is comprised of the switching
devices SW1.sub.0, SW1.sub.0--, SW1.sub.1, and SW1.sub.1-- comprised of
nMOS transistors and serially connecting the bit lines and inverting bit
lines comprising the DRAM cell array MCA.sub.DRAM and the bit lines and
inverting bit lines comprising the flash memory cell array MCA.sub.FLS.
More specifically, the bit lines BLD0 and BL0 are connected by the
switching device SW1.sub.0, the inverting bit lines BLD0.sub.-- and
BL0.sub.-- are connected by the switching device SW1.sub.0--, the bit
lines BLD1 and BL1 are connected by the switching device SW1.sub.1, and
the inverting bit lines BLD1.sub.-- and BL1.sub.-- are connected by the
switching device SW.sub.1--. Further, the gates of the transistors forming
the switching devices SW1.sub.0, SW1.sub.0--, SW1.sub.1, and SW1.sub.1--
are connected to a common first switching signal line SLN.sub.1.
The second switching device group SWG.sub.2 is comprised of switching
devices SW2.sub.0, SW2.sub.0--, SW2.sub.1, and SW2.sub.1-- comprised of
nMOS transistors inserted serially at the bit lines and inverting bit
lines BL0, BL0.sub.--, BL1, and BL1.sub.-- between the first switching
device group SWG.sub.1 and the flash memory cell array MCA.sub.FLS.
Further, the gates of the transistors forming the switching devices
SW2.sub.0, SW2.sub.0--, SW2.sub.1, and SW2.sub.1-- are connected to common
second switching signal lines SLN.sub.2 and SLN.sub.2--.
The latch circuit group LTCG is comprised of a latch circuit LTC0
connecting in parallel the flash memory bit line BL0 and inverting bit
line BL0.sub.-- and the latch circuit LTC1 connecting in parallel the bit
line BL1 and inverting bit line BL1.sub.--, provided between the first
switching device group SWG.sub.1 and the second switching device group
SWG.sub.2. The latch circuits LTC0 and LTC1 are comprised of flipflop type
sense amplifiers SA.sub.f connecting cross-wise the inputs and outputs of
two CMOS inverters, for example, and function as flash memory sense
amplifiers and function as write data latch circuits for temporarily
holding write data of the buffer memory DRAM.
In this way, in this semiconductor nonvolatile memory device, even the
nonvolatile memory flash memory is comprised of a folded bit line type
memory advantageous for increasing speeds in the same way as a DRAM, said
to be impossible in the past, and has a circuit configuration of bit lines
and inverting bit lines comprising the DRAM cell array MCA.sub.DRAM and
the bit lines and inverting bit lines comprising the flash memory cell
array MCA.sub.FLS connected serially through the first switching device
group SWG.sub.1. Namely, the nonvolatile memory of the device is a
so-called differential (including flipflop) sense type with the bit lines
BL0 and BL1 and the inverting bit lines BL0.sub.-- and BL1.sub.-- taking
complementary levels with the same arranged diagonally. As mentioned
above, the latch circuits LTC0 and LTC1 function as differential type
sense amplifiers.
Next, an explanation will be made of examples of the specific circuit
configuration enabling use of the folded bit line system for a flash
memory or other semiconductor nonvolatile memory using FIGS. 3 to 6 and
the bit line BL0 and inverting bit line BL0.sub.-- as an example.
Note that here, FIG. 3 and FIG. 4 are used to explain an example of the
configuration for enabling use of a folded bit line system without use of
dummy cells, while FIG. 5 and FIG. 6 are used to explain an example of a
configuration for enabling use of a folded bit line system with use of
dummy cells.
FIG. 3 is a circuit diagram of an example of the configuration of a flash
memory able to use the folded bit line system without the use of dummy
cells.
This circuit is provided with a bit line voltage adjustment circuit BVA and
enables use of the folded bit line system.
The latch circuit LTC0 functioning as the sense amplifier SA.sub.f is
comprised, as shown in FIG. 3, of a flipflop sense amplifier comprised of
two CMOS inverters INV.sub.1 and INV.sub.2 with inputs and outputs
connected cross-wise. The output node of the inverter INV.sub.1 is
connected to the bit line BL0 and the output node of the inverter
INV.sub.2 is connected to the inverting bit line BL0.sub.--.
The bit line voltage adjustment circuit BVA is comprised of nMOS
transistors NT.sub.SW1 to NT.sub.SW4, a first voltage supply line VL.sub.1
which is a line for supplying a first voltage V.sub.P1 from a not shown
power supply, a second voltage supply line VL.sub.2 which is a line for
supplying a second voltage V.sub.P2 from a not shown power supply, and
first to fourth switching signal supply lines SWL.sub.1 to SWL.sub.4 which
are lines for supplying the first to fourth switching signals PSW.sub.1,
PSW.sub.2, SSW.sub.1, and SSW.sub.2 controlled in level by a not shown
control system.
The nMOS transistor NT.sub.SW1 is connected at its source to the first
voltage supply line VL.sub.1, at its drain to the bit line BL0, and at its
gate to the first switching signal supply line SWL.sub.1. The nMOS
transistor NT.sub.SW2 is connected at its source to the first voltage
supply line VL.sub.1, at its drain to the inverting bit line BL0.sub.--,
and at its gate to the second switching signal supply line SWL.sub.2. The
nMOS transistor NT.sub.SW3 is connected at its source to the second
voltage supply line VL.sub.2, at its drain to a point of connection
between the bit line BL0 and the nMOS transistor NT.sub.SW1, and at its
gate to the third switching signal supply line SWL.sub.3. The nMOS
transistor NT.sub.SW4 is connected at its source to the second voltage
supply line VL.sub.2, at its drain to a point of connection between the
inverting bit line BL0.sub.-- and the nMOS transistor NT.sub.SW2, and at
its gate to the fourth switching signal supply line SWL.sub.4.
The first voltage V.sub.P1 supplied to the first voltage supply line
VL.sub.1 and the second voltage V.sub.P2 supplied to the second voltage
supply line VL.sub.2 satisfy the following relationship when using the
power source voltage as V.sub.cc :
V.sub.P2 >V.sub.P1 =(V.sub.cc / 2) (1)
FIG. 4 is a graph of the fluctuation of the bit line voltage V.sub.BL
caused by adjustment of the bit line voltage adjustment circuit BVA at the
time of a read operation.
In FIG. 4, the horizontal axis shows the time and the vertical axis the
voltage. Curve A shows a bit line voltage in the case where no current is
passed by the memory cell MT0i, while curve B shows a bit line voltage in
the case where a current is passed by the memory cell MT0i.
When a read operation, the bit line BL0 (or the inverting bit line
BL0.sub.--) to which is connected the memory cell performing the read
operation is charged by the bit line voltage adjustment circuit BVA to the
second voltage V.sub.P2 higher than (V.sub.cc /2) and the inverting bit
line BL0.sub.-- (or bit line BL0) is charged to the first voltage V.sub.P1
of the level (1/2 V.sub.cc).
The read operation of the data of the memory cell MT0i is performed as
follows:
First, before the read operation, the signal levels are set as follows and
the standby state is maintained. Namely, the first and second switching
signals PSW.sub.1 and PSW.sub.2 are set to the high level by the not shown
control system, and the third and fourth switching signals SSW.sub.1 and
SSW.sub.2 are set to the low level. Further, the level of the word line
WLi and the level of the second switching signals SLN.sub.2 and
SLN.sub.2-- are set to the low level as well. As a result, the nMOS
transistors NT.sub.SW1 and NT.sub.SW2 of the bit line voltage adjustment
circuit BVA are turned on and the nMOS transistors NT.sub.SW3 and
NT.sub.SW4 and the switching devices SW2.sub.0 and SW2.sub.0-- are turned
off. The bit line BL0 and inverting bit line BL0.sub.-- are supplied with
the first voltage V.sub.P1 and are held to the (V.sub.cc /2) level.
Further, VSA=VSA.sub.-- =VSAL=VSAH=(V.sub.cc /2)
where, VSA is a voltage for driving the sense amplifier,
VSAL is a low voltage for driving the sense amplifier, and
VSAH is a high voltage for driving the sense amplifier.
When starting a read operation from the above standby state, the first
switching signal PSW.sub.1 is set to the low level and the third switching
signal SSW.sub.1 is set to the high level. Due to this, the nMOS
transistor NT.sub.SW1 is turned off and the nMOS transistor NT.sub.SW3 is
turned on. As a result, the supply of the first voltage V.sub.P1 to the
bit line BL0 is stopped and the supply of the second voltage V.sub.P2 is
started. That is, the charging of the voltage V.sub.BL of the bit line BL0
to V.sub.P2 is started. At this time, the inverting bit line BL0.sub.--
continues to be supplied with the first voltage V.sub.P1 and is held at
the V.sub.cc /2 level. Usually, V.sub.P2 =V.sub.P1 +0.2 to 0.5 V.
Next, the word line WLi is set to the high level (selection gate line SEL
also high level).
Next, after a predetermined time, for example, 5 to 20 ns, elapses from
when the word line WLi is set to the high level, the third switching
signal SSW.sub.1 is set to the low level. By this, the nMOS transistor
NT.sub.SW3 is turned off and the supply of the second voltage V.sub.P2 to
the bit line BL0 is stopped. In this state, if the memory cell MT0i passes
a current for a predetermined time, for example 5 to 20 ns, the standby
state is entered for the time where V.sub.BL <V.sub.P1.
After the elapse of this time, V.sub.BL <V.sub.P1 when the memory cell MT0i
passes a current and V.sub.BL =V.sub.P2 when it does not pass it.
On the other hand, the bit line voltage V.sub.BL-- of the inverting bit
line BL0.sub.-- is connected at this time to the first voltage supply line
VL.sub.1, so the first voltage V.sub.P1 is held regardless of if the
memory cell MT0i passes a current or does not pass it.
Here, the levels of the first switching signal lines SLN.sub.2 and
SLN.sub.2-- are set to the high level and the VSA and VSA.sub.-- are set
with binary data of high/low in accordance with the memory cell MT0i.
In this way, according to the configuration of FIG. 3, it is possible to
use the folded bit line system even when a memory cell MT0i connected to
the bit line BL0 and the memory cell MTOI connected to the inverting bit
line BL0.sub.-- are connected to a single word line WLi, without the use
of dummy cells.
As a result, the layout is easier, direct connection of the bit lines and
inverting bit lines of a folded bit line type DRAM is possible, and it is
possible to easily form a DRAM and flash memory in the same chip. Further,
various types of noise act in exactly the same way on the bit line BL0 and
inverting bit line BL0.sub.--, so it is possible to suppress to a minimum
the effect of the noise. Accordingly, it is possible to raise the
sensitivity of the sense amplifier and thereby increase the speed.
Note that in this embodiment, the current of the memory cell MT0i.sub.--
can be completely compensated for by the first voltage V.sub.P1, but
considering manufacturing variations etc., the above circuit can be
constructed if {current of memory cell MT0i>(current of memory cell
MT0i.sub.-- -current compensated by the first voltage V.sub.P1)}.
Further, the circuit according to this embodiment can be applied to any
type of flash memory whether the NAND type or NOR type.
Next, an explanation will be made of another example of the configuration
using FIG. 5 and FIGS. 6A and 6B.
FIG. 5 is a circuit diagram of an example of the configuration of a flash
memory able to use the folded bit line system using dummy cells.
In FIG. 5, MCA.sub.1h and MCA.sub.2h show memory cell arrays connected to
the bit line BL0, MCA.sub.1t and MCA.sub.2t show memory cell arrays
connected to the inverting bit line BL0.sub.--, DCL.sub.h shows a dummy
cell connected to the bit line BL0, DCL.sub.t shows a dummy cell connected
to the inverting bit line BL0.sub.--, and NT.sub.11 and NT.sub.12 show
nMOS transistors.
Two upper side selection transistors is provided in an NAND type flash
memory, one of them being a depletion transistor, so this circuit can use
the folded bit line system. Dummy cells are used as the reference cells.
This circuit has the same type of configuration as the folded bit line of
the known DRAM circuit except that two selection gates are provided at
each memory cell array.
FIG. 6 is a view of an example of the configuration of the memory cell
array according to this embodiment.
As shown in FIG. 6A, each memory cell array is comprised of the
series-connected so-called upper side first and second selection
transistors SL.sub.1 and SL.sub.2, a plurality of, for example, eight,
memory transistors MT.sub.0 to MT.sub.7, connected in series with the
second selection transistor SL.sub.2, and series-connected so-called lower
side selection transistors SL.sub.3 between the memory transistor MT.sub.7
and the ground. Further, one of the first and second selection transistors
SL.sub.1 and SL.sub.2 is comprised by a depletion transistor.
In the memory cell array, the first selection transistor SL.sub.1 is
connected to the bit line BL0 or inverting bit line BL0.sub.--.
The first and second selection transistors SL.sub.1 and SL.sub.2 of the
memory cell array connected to the same bit line BL0 or inverting bit line
BL0.sub.-- are alternately comprised by depletion transistors in the order
of connection from the sense amplifier side.
Note that in FIG. 5, for simplification of the illustration, the
configuration of FIG. 6A is shown simplified as in FIG. 6B.
In the circuit of FIG. 5, the read operation of the data of the memory
transistor connected to the selection gates SG.sub.11 and SG.sub.21 and
connected to the word line WLj is performed as follows:
First, as an initial state, the levels of the supply line of the
precharging signal PC and the first and second switching signal lines
SLN.sub.1 and SLN.sub.2 are set to the low level (0 V). As a result, the
nMOS transistors NT.sub.11 and NT.sub.12 and the switching devices
SW1.sub.0, SW1.sub.0--, SW2.sub.0, and SW2.sub.0-- are turned off.
Further, the inverted dummy selection gate signal DSG.sub.-- and the
inverted selection gate signal SG.sub.-- are set to the low level, the
word line WLj and the dummy word line DWL are set to the high level (5 V),
the inverted high and low sense amplifier drive signals VSAL.sub.-- and
VSAH.sub.-- are set to the inverted precharge signal V.sub.PC--, and the
bit line BLD0 and inverting bit line BLD0.sub.-- are set to (1/2)V.sub.cc.
In this state, the inverted precharge signal PC.sub.-- and the second
switching signal line SLN.sub.2 are set to the high level, and, the nMOS
transistors NT.sub.11 and NT.sub.12 and the switching devices SW2.sub.0
and SW2.sub.0-- are turned on. As a result, the bit line BL0 and inverting
bit line BL0.sub.-- are precharged to the precharge voltage V.sub.PC--.
Next, the word line of the substantially simultaneously selected cell is
set to the low level and the selection gate signal SG.sub.-- is set to the
high level. The dummy selection gate signal DSG.sub.-- of the dummy cell
DMC connected to the inverting bit line BL.sub.-- is set to the low level
and the signal SG.sub.-- is set to the high level. In this case, the
signals SG2 and DSG1 are set to the high level and the word line WL and
dummy word line DWL are set to the low level.
If the precharging ends, the signal PC.sub.-- is set to the low level. Due
to this, the nMOS transistors NT.sub.11 and NT.sub.12 are turned off and
the sense operation is started.
If the selected cell passes a current, the voltage V.sub.BL of the bit line
BL0 falls, while if it does not, there is no change. On the other hand,
the dummy cell DMC is set so as to pass an intermediate current, so the
voltage V.sub.BL of the inverting bit line BL0.sub.-- falls somewhat. That
is, if the selected cell passes a current, the voltage V.sub.BL of the bit
line BL0 falls by a large amount.
About when the potential difference of the bit line BL0 and inverting bit
line BL0.sub.-- becomes -0.1 V, VSAL.sub.-- and the second switching
signal SLN.sub.2 are set to the low level and VSAH.sub.-- is set to the
high level. Due to this, the sense amplifier SA becomes the low level (0
V) and the sense amplifier SA.sub.-- becomes the high level (5 V) due to
the operation of the flipflop type sense amplifier SAf.
Next, the first switching signal line SLN.sub.1 is set to the high level.
Due to this, the switching device SW1.sub.0 and SW1.sub.0-- turns on and
the sense amplifiers SA and SA.sub.-- are read out to the bit line BLD0
and inverting bit line BLD0.sub.-- of the DRAM memory serving as the
buffer memory.
In this way, even if dummy cells are used, it is possible to construct a
folded bit line type flash memory. Accordingly, in the same way as in the
circuit of FIG. 3, the layout becomes easy, it is possible to directly
connect the bit lines and inverting bit lines of the folded bit line type
DRAM, and it is possible to easily form a DRAM and flash memory on the
same chip.
Note that the circuit of this embodiment as well can be applied both to
NAND type and NOR type flash memories.
Next, an explanation will be made of an example of the write operation of
data in the configuration of FIG. 1.
For example, if the write operation to a normal DRAM ends, the level of the
first switching signal line SLN.sub.1 is set to the high level.
First, the memory cells SRG0 and SRG1 connected to the word line WL.sub.BF1
are read out and the data of the same latched to the latch circuits LTC0
and LTC1.
Next, the level of the first switching signal line SLN.sub.1 is set to the
low level and the level of the second switching signal line SLN.sub.2 is
set to the high level (SLN.sub.2-- remains at low level). Due to this, the
data latched at the latch circuits LTC0 and LTC1 are transferred to and
stored in the flash memory cells MT0i and MT1i.
In FIG. 5, the function of selecting a bit line when writing of the
SLN.sub.2 and SLN.sub.2-- in FIG. 1 is handled by the SG.sub.1, SG.sub.3,
and SG.sub.4 in FIG. 5.
As explained above, according to the present embodiment, a folded bit line
type flash memory is constituted and the bit lines BL0 and BL1 and
inverting bit | | |
