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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems including direct memory
access (DMA) controllers, and in particular, to portable computer systems
compatible with docking stations having controllers capable of providing
DMA.
2. Description of the Related Art
Computer systems having direct memory access (DMA) allow input/output (I/O)
units to access memory (e.g., such as a dynamic random access memory
(DRAM)) via a DMA controller rather than through a microprocessor. The DMA
controller includes logic, timers, registers, etc., which allow the I/O
unit to directly access memory circuits within the computer system. Memory
accesses made via a DMA controller are typically much faster than memory
accesses made via the microprocessor.
Typically, when an I/O device initiates an access to a memory via a DMA
controller, the I/O device issues a DMA request to the DMA controller,
and, subsequently, receives a DMA acknowledge signal from the DMA
controller if the memory is available to be accessed by the I/O device.
Once the DMA controller has acknowledged the DMA request, the I/O unit
begins to transfer data under control by the DMA controller. The DMA
controller manages the transfer of this data between the I/O unit and the
memory in a manner similar to a conventional bus master on the system bus.
Within a DMA controller a plurality of registers are assigned to separate
channels under the control of the DMA controller. That is, the registers
store address data associated with a hardware configured channel within
the computer system. Each channel corresponds to an I/O device which uses
the DMA controller. Specifically, the registers within the DMA controller
contain address and control information which are specifically assigned to
the I/O devices which use the DMA controller. Furthermore, these registers
are assigned a prespecified channel number which corresponds to
hardware-configured channel numbers in each I/O device. Thus, for example,
a disk drive storage system may have a hardware-configured channel number
of 4, corresponding to selected address and control information stored
within registers in the DMA controller, while a sound (audio) board or
other I/O device has a hardware-configured channel number of 7, which
corresponds to other specified address and control information stored
within registers of the DMA controller.
Although DMA is widely used in the PC-AT architecture, the PCI bus
architecture does not support DMA from a central DMA control unit. This is
because the PCI bus allows for only a single agent to operate on the bus
at one time. Thus, since a central DMA controller typically operates
(within the PC-AT architecture) by supplying address and request
information to a target, while another device (e.g., an I/O unit) supplies
the data to the target independent of the DMA controller, two agents would
operate on the bus at the same time. Since the PCI bus architecture does
not allow one device to send address and command signals over the bus
while another device sends data signals over the bus, some systems have
provided for the use of slave DMA controllers in addition to a central DMA
controller. A slave DMA controller is local to the agent which is to
transfer data over the PCI bus, and controls the transmission of data to
the target on the PCI bus so that the slave controller is the only agent
which the PCI bus sees. However, it has been found that the provision of
multiple DMA controllers (i.e., a central DMA controller and one or more
slave DMA controllers) on the PCI bus results in a further difficulty.
As long as there is a single central DMA controller within a given computer
system which receives channel assignments for each of the I/O units within
the computer system, this central DMA controller is able to provide direct
memory accesses for each of the I/O units configured to operate in the
computer system. However, as discussed above, multiple DMA controllers may
be necessary in certain applications such as when DMA is provided on a PCI
bus. Furthermore, in other applications, for example, a notebook computer
is connected to a docking station having DMA capability for one or more
I/O devices associated with the docking station. Under certain
circumstances, a slave DMA controller within the notebook computer or the
docking station may not receive information indicating the assignment of a
particular DMA channel to an I/O device in the docking station. This may
happen because operating system software within the computer system is
typically not capable of distinguishing among multiple DMA controllers.
Thus, all hardware configured I/O channels within the computer system are
usually assigned to the central DMA controller. Since the central DMA
controller hardware within the computer system is not informed about which
channels are to be assigned to which DMA controllers, the central DMA
controller is not capable of setting the appropriate DMA channels on the
slave controllers.
In such a configuration, I/O units which have DMA capability under the
control of one of the slave DMA controllers would not be able to employ
DMA without highly specialized software (e.g., software which
discriminates amongst multiple DMA controllers and all I/O devices
associated with each of the controllers). For example, in certain docking
systems, a notebook computer connects with the docking station via a PCI
bridge so that a PCI bus within the notebook computer is in communication
with a PCI bus within the docking station. The docking station further
includes an industry-standard architecture (ISA) bus in communication with
the PCI bus within the docking station. In such systems, I/O units mounted
in ISA expansion slots on the ISA bus within the docking station are not
under the control of the central DMA controller within the notebook
computer. Rather the I/O units in the ISA expansion slots communicate with
the devices on the PCI bus via a PCI-to-ISA bridge associated with a slave
DMA controller. This happens because the PCI and ISA busses are
incompatible and therefore require some kind of interface. Furthermore,
the PCI bus does not support DMA from the ISA bus in the docking station.
Thus, the central DMA controller within the notebook computer does not
receive DMA requests from the particular channels assigned to the I/O
devices connected on the ISA bus within the docking station.
In such systems, the slave DMA controller, which is the only DMA controller
able to control the I/O units on the ISA bus, does not receive the
necessary configuration information to allocate a channel to the I/O units
on the ISA bus. The reason for this is that the allocation software is
typically not sophisticated enough to detect the presence of the slave DMA
controller. Thus, the slave DMA controller may simply ignore DMA requests
from the I/O units on the ISA bus. Consequently, the DMA capability may
not operate correctly in a notebook computer using a central DMA
controller engaged with a docking station, as described above.
SUMMARY OF THE INVENTION
A microprocessor-based computer system provides distributed direct memory
access (DMA) for a plurality of peripheral units. The computer system
comprises a memory and a central DMA controller in communication with the
memory via a system bus. The central DMA controller includes registers
which store data defining a communication channel associated with one of
the peripheral units. The computer system further includes a slave DMA
controller in communication with the memory and the central DMA controller
via the system bus. The slave DMA controller includes registers for
storing data defining the communication channel. A plurality of the
peripheral units are configured to access the memory, some of the
peripheral units are in communication with the memory via the central DMA
controller and others of the peripheral units are in communication with
the memory via the slave DMA controller. The peripheral units are further
configured to include an assigned communication channel. Finally, the
computer system includes a hardware connection between the slave DMA
controller and the central DMA controller which allows the slave DMA
controller to request channel information in the registers within the
central DMA controller when one of the peripheral units in communication
with the memory via the slave DMA controller initiates a memory access.
In a preferred embodiment, the slave DMA controller includes a state
machine which initiates the request of channel information and the central
DMA controller includes a state machine which receives the request of
channel information and initiates transfer of the channel information to
the slave DMA controller.
According to a further aspect, the invention is a method of automatically
controlling distributed direct memory accesses (DMAs) in a distributed DMA
computer system including a memory, a central DMA controller, a slave DMA
controller, and a plurality of peripheral units. The peripheral units have
hardware configured channel data defining communication channels
associated with each of the peripheral units. The method includes the
steps of configuring the central DMA controller to control direct memory
accesses initiated by the peripheral units by storing information in the
central DMA controller corresponding to the hardware configured channel
data within the peripheral units; initiating a DMA request from one of the
peripheral units to the slave controller; requesting, from the central DMA
controller, channel data corresponding to a communication channel
associated with the one of the peripheral units; and transferring the
channel data corresponding to the communication channel associated with
the one of the peripheral units from the central DMA controller to the
slave DMA controller.
In a preferred embodiment, the method further comprises the step of masking
the channel data corresponding to the communication channel so that the
central DMA controller is no longer enabled to control DMA accesses
initiated by the peripheral unit associated with the communication
channel.
In another preferred embodiment, the method further comprises the step of
acknowledging the DMA request and controlling memory transfer between the
requesting peripheral unit and the memory.
Under a further aspect of the invention, a computer system for
automatically controlling direct memory accesses (DMAs) comprises a
microprocessor; a memory under the control of the microprocessor; a system
bus; and a central DMA controller in communication with the memory via the
system bus. The central DMA controller stores configuration information
which provides for control of direct accesses to the memory for selected
devices in communication with the system bus. The computer system
additionally includes a slave DMA controller in communication with the
system bus where the slave DMA controller is also in communication with
the central DMA controller via another hardware connection, and where the
hardware connection provides data to the central DMA controller which
designates selected portions of the configuration information which are to
be transferred to the slave DMA controller; and a peripheral unit in
communication with the memory via the slave DMA controller and the system
bus.
Yet another aspect of the invention is a computer system for automatically
controlling direct memory accesses (DMAs) comprising a notebook computer.
The notebook computer comprises a microprocessor; a memory under the
control of the microprocessor; a system bus; a central DMA controller in
communication with the memory via the system bus, where the central DMA
controller stores configuration information which provides for control of
direct accesses to the memory for selected devices in communication with
the system bus; and a peripheral unit which accesses the memory via the
central DMA controller. The computer system also includes a docking
station which communicates with the notebook computer via a connector. The
docking station comprises a slave DMA controller in communication with the
system bus via the connector where the slave DMA controller is also in
communication with the central DMA controller via a hardware connection,
and where the hardware connection provides data to the central DMA
controller which designates selected portions of the configuration
information which is to be transferred to the slave DMA controller; and a
peripheral unit in communication with the memory via the slave DMA
controller and the system bus.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a perspective view showing the physical layout of a docking
station which receives a notebook computer.
FIG. 2 is a simplified schematic block diagram which depicts the main
functional elements internal to the notebook computer and docking station
of FIG. 1.
FIG. 3 is a flowchart which shows the general method of operation of the
computer system depicted in FIGS. 1 and 2 when the notebook computer is
engaged within the docking station.
FIG. 4 is a flowchart which depicts the general method of transferring
channel information from the central DMA controller to a slave DMA
controller.
FIG. 5 is a flowchart which depicts the general method employed by the
state machine within the slave DMA controller to initiate a channel data
request to the central DMA controller.
FIG. 6 is a flowchart which depicts the general method employed by the
state machine within the central DMA controller to initiate a channel data
transfer upon receipt of a channel data request from the slave DMA
controller.
FIG. 7 illustrates the serial transmission between the slave DMA controller
and the central DMA controller in FIGS. 3 and 5.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a perspective view of a PCI notebook/docking station system 100
which shows a notebook computer 110 prepared for engagement with a docking
station 120 via an engagement slot 125 within the docking station.
Typically, docking stations are used to provide full-sized peripherals
and/or additional expansion capability to a notebook computer. For
instance, as depicted in FIG. 1, the docking station 120 includes
peripheral connections to a full-sized keyboard 125 and a full-sized
monitor 130. As represented by an arrow in FIG. 1, the notebook computer
110, which, in one embodiment, comprises an AST ASCENTIA notebook
computer, slides into the engagement slot 125 and electrically connects to
circuitry within the docking station 120 via a connector (not shown in
FIG. 1).
Once the notebook computer 110 is engaged within the docking station 120, a
user may operate the notebook computer 110 using the peripheral devices,
such as the keyboard 125 and the display 130, via the circuitry within the
docking station 120. The docking station 120 may also include additional
peripheral devices such as a hard disk drive, a printer, etc. (not shown).
FIG. 2 is a simplified schematic block diagram which illustrates the PCI
notebook/docking station architecture internal to the notebook computer
110 and the docking station 120. The notebook computer 110 (enclosed
within a dashed line in FIG. 2) includes a microprocessor, system
controller, and PCI interface, designated generally by the reference
number 200, in communication with a memory 205. In one preferred
embodiment, the microprocessor comprises a PENTIUM microprocessor chip
available from INTEL while the memory 205 is preferably implemented as a
DRAM which stores 4-8 megabytes of data. The microprocessor 200 and the
memory 205 have access to a PCI-to-ISA bridge 210, including a central
(also known as a "master") DMA controller 215, via a primary PCI bus 240.
The PCI bus 240 is preferably a 32-bit bus including address, control, and
data lines as is well known in the art. The central DMA controller 215
preferably comprises a modified eight-channel Legacy 8237 DMA controller,
available from INTEL. The central DMA controller 215 is specially
configured, in accordance with the teachings of the present invention, to
include an additional output pin connected to a state machine 217 within
the central DMA controller 215. The PCI-to-ISA bridge 210, also includes
an interrupt controller, and specific hardware for an IBM compatible PC.
The PCI-to-ISA bridge 210 is preferably constructed in accordance with the
specifications laid out in the PCI related specifications available from
PCI special interest group, N/SHS3-15A, 5200 N.E. Elam Young Parkway,
Hillsboro, Oreg. 97124-6497. The PCI-to-ISA bridge 210 acts as an
interface between the primary PCI bus 240 and an ISA bus 250. The ISA bus
250 is conventional and connects to, for example, a floppy disk
controller, serial and parallel ports, a PCMCIA card, etc. (not shown).
The PCI bus 240 also communicates with a PC-card controller 220. The
PC-card controller 220 also provides DMA capability and includes a state
machine 222. A PCI video controller 230 also connects to the PCI bus 240.
The notebook computer 110 engages with the docking station 120 (also shown
in FIG. 2 as enclosed within a dashed line) via a docking interface 255.
The docking interface 255 preferably comprises an electrical connector
which electrically connects the notebook computer 110 to the docking
station 120. A PCI-to-PCI bridge 260 within the docking station 120
connects to the docking interface 255 to provide an interface between the
primary PCI bus 240 within the notebook computer 110 and a secondary PCI
bus 262 within the docking station 120. The PCI-to-PCI bridge 260
preferably includes a repeater as well as other connector and conventional
interface circuitry to provide for error free communication between the
primary PCI bus 240 and the secondary PCI bus 262. The PCI-to-PCI bridge
260 is preferably constructed in accordance with the specifications laid
out in revision 1.0 of the PCI-to-PCI bridge architecture specification
available from PCI special interest group, N/SHS3-15A, 5200 N.E. Elam
Young Parkway, Hillsboro, Oreg. 97124-6497.
The secondary PCI bus 262 connects the PCI-to-PCI bridge 260 to PCI
expansion slots 263, 266, as well as to a PCI-to-ISA bridge 270. The
expansion slots 263, 266 are conventional expansion slots compatible with
PCI bus configuration. The PCI-to-ISA bridge 270 is preferably constructed
in accordance with the specifications laid out in the PCI architecture
related specifications available from PCI special interest group,
N/SHS3-15A, 5200 N.E. Elam Young Parkway, Hillsboro, Oreg. 97124-6497. The
PCI-to-ISA bridge 270 communicates with a slave DMA controller 280 (e.g.,
a modified Legacy 8237 DMA controller available from INTEL). The slave DMA
controller 280 is specially configured to include an additional output pin
which connects to a state machine 282 within the slave DMA controller 280.
Although the slave DMA controller 280 is depicted in FIG. 2 as separate
from the PCI-to-ISA bridge 270, it should be understood that the slave DMA
controller 280, with the state machine 282, are included within the
PCI-to-ISA bridge 270 in accordance with the teachings of the present
invention, and are not included in a "standard" PCI-to-ISA bridge.
The PCI-to-ISA bridge 270 also connects to conventional ISA expansion slots
283, 286 via an ISA bus 290 within the docking station 120. The ISA
expansion slots 283, 286 respectively communicate with the slave DMA
controller 280 via DMA request lines 292, 294.
In accordance with a feature of the present invention, the PC-card
controller 220 within the notebook computer 110, as well as the slave DMA
controller 280 (part of the PCI-to-ISA bridge 270) within the docking
station 120, communicate with the PCI-to-ISA bridge 210 (which includes
the central DMA controller) via slave DMA request lines 296, 298. As will
be described in greater detail below, the new hardware connections
provided between the slave DMA controllers 220, 280 and the central DMA
controller 210 via the lines 296, 298, allow for complete compatibility
between the central DMA controller 210 and the slave DMA controllers 220,
280.
In operation, the peripheral devices within the notebook computer 110
(e.g., the floppy disk controller, the serial and parallel ports, etc.)
transmit data to and request data from the memory 205 via the central DMA
controller 215 within the PCI-to-ISA bridge 210, and the primary PCI bus
240. As discussed briefly above, each of the peripheral units using DMA
built into the notebook computer 110 are assigned a hardware configured
channel which has corresponding memory address and control data stored
within registers of the central DMA controller 215. Thus, when the central
DMA controller 215 receives DMA requests from one of the peripheral units,
the central DMA controller 215 accesses the memory 205 via the primary PCI
bus 240 to transfer data from the peripheral unit to the memory 205 or
data from the memory 205 to the requesting peripheral unit on the ISA bus
250.
When the notebook computer 110 is connected to the docking station 120 so
that bi-directional communication is established between the notebook
computer 110 and the docking station 120, I/O units connected at the PCI
expansion slots 263, 266 communicate with the notebook computer 110 via
the secondary PCI bus 262 and the PCI-to-PCI bridge 260. Specifically, the
I/O units received by the PCI expansion slots 263, 266 can act as bus
masters to transfer information to and from the memory 205 within the
notebook computer 110 via the secondary PCI bus 262, the PCI-to-PCI bridge
260, and the primary PCI bus 240.
I/O units received within the ISA expansion slots 283, 286 are further
configured to access data within the memory 205 of the notebook computer
110. However, if the I/O units within the expansion slots 283, 286 request
DMA to the memory 205 (i.e., without mediation by the microprocessor and
system controller 200), then the I/O units within the ISA expansion slots
283, 286 must operate through the slave DMA controller 280.
As detailed above, unless specially-adapted, highly-complex software is
used to discriminate between each of the slave and central DMA controllers
within the computer system 100 comprising the notebook computer 110 and
the docking station 120, then the slave DMA controller 280 will not be
configured for the appropriate channels so that the slave DMA controller
will not be able to control memory accesses for I/O units assigned to
those channels. In accordance with the teachings of the present invention,
however, a special hardware implemented configuration provides a simple
and efficient method by which the I/O units received by the ISA expansion
slots 283, 286 may utilize DMA.
Specifically, the computer system 100 of the present invention includes the
specially configured DMA controllers 215, 220 and 280 having the state
machines 217, 222 and 282, respectively, which communicate via the lines
296, 298. As described in greater detail below with reference to FIGS.
3-6, the hardware implemented communication between the slave DMA
controllers 220, 280 and the central DMA controller 215, as provided for
by the state machines 217, 222 and 282, allow for proper configuration of
slave DMA controllers within a distributed DMA system without complicated
software.
FIG. 3 is a system flow chart which details the general method used in
accordance with the present invention to provide direct memory access
capability to I/O units connected to the ISA bus 290 without the use of a
specially-adapted, highly-complex operating system software that is aware
of this special hardware. The method starts, as represented by a "BEGIN"
block 300, and proceeds to an activity block 310 wherein the central DMA
controller 215 is initially set up by the conventional operating system
software for devices requiring DMA service. Thus, as represented within
the activity block 310, each of the I/O units having hardware configured
channels are assigned to the central DMA controller 215 during the
resource allocation method employed in the operating system (e.g., WINDOWS
95).
As is well known in the art, each DMA controller includes multiple
registers which store information defining the channels assigned to the
DMA controller. Typically, each channel assigned to a DMA controller is
defined by data stored within a 6-bit mode register and four 16-bit
registers which respectively hold a base address, a base count, a current
address, and a current count. The base address is the starting address
which is to be accessed in the memory, while the base count identifies the
initial number of bytes which are to be transferred. The current address
is the address which is currently being accessed by the DMA, while the
current count is the number of bytes remaining to be transferred. The
6-bit mode register stores control information which is used to define the
method of data transfer for a given channel.
Once the central DMA controller 215 has been set up as indicated within the
activity block 310 (i.e., the registers defining the channels assigned to
the central DMA controller 215 have been loaded), a slave DMA controller
(e.g., the slave DMA controller 280) receives a DMA request from a
peripheral device connected within one of the ISA expansion slots 283,
286, as indicated within an activity block 320. As is well known in the
art, whenever an I/O unit having DMA capability initiates a DMA request,
the I/O unit transmits a DMA request to the local DMA controller. If the
slave DMA controller 280 is not configured for the channel of the
requesting I/O unit, then the state machine 282 within the slave DMA
controller 280 causes the slave DMA controller 280 to transmit data, in a
serial fashion, to the central DMA controller 215 via the line 298 (as
indicated within an activity block 330). The serially transmitted data on
the line 298 includes an initial request signal, data which indicates the
channel which needs activation within the slave DMA controller 280, and
the address of the requesting slave DMA controller as illustrated in FIG.
7.
Once the slave DMA controller 280 has transmitted the appropriate data to
the central DMA controller 215, control passes to a sub-method block 340
wherein the central DMA controller 215, under the direction of the state
machine 217, transfers the appropriate channel data, including the channel
number, the base address and count data, and the data to be stored in the
mode register, to the slave DMA controller 280. This channel data is
transmitted to the slave DMA controller 280 via the primary PCI bus 240,
the PCI-to-PCI bridge 260, the secondary PCI bus 262, and the PCI-to-ISA
bridge 270. In addition, the central DMA controller masks out the
corresponding channel accessing information stored in the registers of the
central DMA controller 215 so that all further accesses to that channel
are ignored by the central DMA controller 215. This insures that, after
the channel data has been transferred to the slave DMA controller 280,
there is no conflict between the master DMA controller 215 and the slave
DMA controller 280 (i.e., only the slave DMA controller 280 responds to
DMA control signals associated with that channel as well as further data
written to that channel). The method employed within the sub-method block
340 to write and mask-out the appropriate channel data will be described
in greater detail below with reference to FIG. 4.
Control passes from the sub-method block 340 to an activity block 350
wherein the slave DMA controller 280 is configured to receive all further
DMA transactions to the designated channels. That is, all those channels
from which the slave DMA controller 280 receives DMA requests are now
assigned exclusively to the slave DMA controller 280. This
reconfiguration, or remapping, of the slave DMA controller 280 is
accomplished by storing the data transmitted from the central DMA
controller 215 in the corresponding registers within the slave DMA
controller 280. Thereafter, from the perspective of the system software,
all updates (i.e., reads or writes) to or from the slave channel registers
occur as though these updates were made to the central DMA controller
registers. Thus, once the overall system method is complete and control
passes to a final "END" block 360, the computer system 100 is configured
to operate with multiple DMA controllers without interference.
FIG. 4 is a flowchart which details the method employed in the sub-method
block 340 to transfer data associated with a channel originally assigned
to the central DMA controller 215 to the slave DMA controller 280. Thus,
the method represented in the flow chart of FIG. 4 remaps channel data
from the central DMA controller 215 to the slave DMA controller 280 so
that the remapped channels are assigned to the slave DMA controller 280
and are no longer assigned to the central DMA controller 215.
The method starts, as represented by a "BEGIN" block 400, and proceeds to
an activity block 410 wherein the central DMA controller 215 arbitrates to
gain control of the bus. As is well known in the art, a DMA controller 215
is a bus master so that the DMA controller 215 is able to obtain control
of the primary PCI bus 240. Once the central DMA controller 215 has
obtained control of the PCI bus 240, the central DMA controller 215
initiates a data transfer cycle, as indicated in an activity block 420, to
transfer channel data to the slave DMA controller 280. The registers
within the slave DMA controller 280 have associated system addresses so
that the central DMA controller 215 is able to simply write the data
stored in the channel registers (i.e., the data to be transferred) to the
addresses of the corresponding registers in the slave DMA controller 280.
Thus, the transfer of the channel data from the central DMA controller 215
to the slave DMA controller 280 is performed in a conventional data
transfer transaction along the PCI bus 240. The slave DMA controller
channel address is subsequently remapped to the same address as the
corresponding channel in the central DMA controller 215.
Once the appropriate channel data has been transferred to the slave DMA
controller 280, control of the method passes to an activity block 430,
wherein the channel associated with the data just transferred is masked
(i.e., disabled) in a conventional manner using a mask register within the
central DMA controller 215. Thereafter, the method terminates as
represented by an "END" block 440.
FIG. 5 is a flowchart which depicts the general method employed by the
state machine 282 within the slave DMA controller 280 (or the state
machine 222 within the controller 220) to generate a channel request
signal to the central DMA controller 215 in accordance with the present
invention. The state machine 282 begins in an idle state represented by
the "BEGIN" block 500, which is entered immediately after power-up or
after a power reset. The state machine 282 remains in the idle state until
a DMA request is received from one of the I/O units within the ISA slots
283, 286, as represented within a decision block 510. If a DMA request is
received from one of the I/O units, then a test is performed within the
state machine 282 to determine if the slave DMA controller 280 is
configured for the requesting channel, as indicated within a decision
block 520. If a slave DMA controller 280 is configured for the requesting
channel (i.e., the hardware configure channel of the requesting I/O unit
has corresponding channel data stored within the registers of the slave
DMA controller 280), then the state machine 282 enters a memory
transaction state (represented by activity blocks 520-535) wherein the
slave DMA controller 280 first obtains control of the PCI bus 240 and
subsequently transmits an acknowledge signal to the requesting I/O unit
and begins the memory access in a conventional manner. Specifically, the
slave controller 280 transmits a bus request, as indicated within an
activity block 525, and waits for an acknowledge that the PCI bus 240 has
been granted to the control of the slave DMA controller 280, as
represented in a decision block 527. Once control of the PCI bus 240 has
been granted to the slave DMA controller 280, the slave DMA controller
transmits an acknowledge signal to the requesting I/O unit, as indicated
within an activity block 530. The data is then transferred in a
conventional manner, as represented in an activity block 533, and control
passes to a decision block 535, wherein a determination is made if the
data transfer is complete. If multiple cycles of data are to be
transferred, then control returns to the activity block 533 until all of
the data is transferred, at which time control returns to the idle state
where the slave DMA controller waits for another DMA request.
If, however, it is determined within the decision block 520 that the slave
DMA controller 280 is not configured for the requesting channel, then the
state machine 282 enters a request channel state (represented by an
activity block 540), wherein the state machine 282 transmits a request
signal together with the requesting channel number and the address of the
slave DMA controller 280 to the central DMA controller 215. The data
transmitted from the state machine 282 to the central DMA controller 215
is transmitted in a serial manner, as illustrated in FIG. 7. Once the
appropriate data has been transmitted from the state machine 282 to the
central DMA controller 215, control passes to a decision block 550 wherein
the state machine 282 determines whether or not the slave DMA controller
280 has received the necessary channel data to be configured for the
requesting channel. This process repeats until the slave DMA controller
280 receives the necessary channel information from the central DMA
controller 215, as described above. Control then passes from the decision
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