Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices

The invention claimed is:

1. Programmable logic array integrated circuit device apparatus comprising:

a plurality of regular columns of programmable programming data memory cells disposed substantially side by side on said device, the cells in each of said columns being connected to one another in a series such that programming data applied at any point in said series flows from that point down the series in a direction from a top of said column toward a bottom of said column, adjacent cells in the series in each of said columns being grouped into a plurality of first groups and a plurality of second groups which are interspersed with said first groups in said series;

a spare column of programmable programming data memory cells disposed substantially side by side with one of said regular columns which is at an end of said plurality of said regular columns, the cells in said spare column being connected to one another in a series such that programming data applied at any point in said series flows from that point down the series in a direction from a top of said spare column toward a bottom of said spare column, adjacent cells in the series in said spare column being grouped into a plurality of second groups, each of which is associated with a respective one of the second groups in each of said regular columns;

first switching circuitry disposed in the series in each of said columns in advance of each of said second groups in said column for selectively connecting (1) any cell in said column which is immediately above said first switching circuitry to any cell in said column which is immediately below said first switching circuitry or (2) any cell in a first column adjacent to said column in a direction away from said spare column, which cell is immediately above the first switching circuitry in said first adjacent column, to any cell in said column which is immediately below said first switching circuitry; and

second switching circuitry disposed in the series in each of said columns below each of said second groups in said column for selectively connecting (1) any cell in said column which is immediately above said second switching circuitry to any cell in said column which is immediately below said second switching circuitry or (2) any cell in a second column adjacent to said column in a direction toward said spare column, which cell is immediately above the second switching circuitry in said second adjacent column, to any cell in said column which is immediately below said second switching circuitry.

2. The apparatus defined in claim 1 further comprising:

a programming data input terminal associated with each of said regular columns; and

third switching circuitry associated with each of said columns for selectively connecting (1) the input terminal associated with said column to a first cell in the series of cells in said column or (2) the input terminal associated with said first adjacent column to said first cell in said series.

3. The apparatus defined in claim 2 further comprising:

a source of fixed programming data, and wherein said third switching circuitry associated with each of said columns can alternatively selectively connect said source to said first cell in the series of cells in said column.

4. The apparatus defined in claim 3 wherein said second switching circuitry associated with each of said columns can alternatively selectively connect said source to said cell which is immediately below said second switching circuitry.

5. The apparatus defined in claim 1 wherein each of said regular columns further comprises:

a plurality of first regions of programmable logic functionality of a first type, each of said first regions being controlled by programming data stored in the cells in a respective one of said first groups in said column; and

a plurality of second regions of programmable logic functionality of a second type, each of said second regions being controlled by programming data stored in the cells in a respective one of said second groups in said column; and wherein said spare column further comprises:

a plurality of second regions of programmable logic functionality of said second type, each of said second regions in said spare column being controlled by programming data stored in the cells in a respective one of said second groups in said spare column.

6. The apparatus defined in claim 5 wherein each of said second regions comprises:

a plurality of logic modules, each of which receives a plurality of logic module input signals and produces a logic module output signal which is a programmable logical combination of said input signals.

7. The apparatus defined in claim 5 wherein each of said first regions comprises:

a plurality of programmable connections for selectively connecting logic module output signals to interconnection conductors which convey signals between logic modules.

8. The apparatus defined in claim 7 wherein each of said first regions further comprises:

a plurality of programmable interconnections for selectively making connections between interconnection conductors.

9. The apparatus defined in claim 8 wherein said interconnection conductors include:

a plurality of vertical conductors associated with each of said regular columns for conveying signals substantially parallel to the associated column.

10. The apparatus defined in claim 9 wherein, in addition to being included in each of said columns, said logic modules are disposed on said device in a plurality of substantially parallel rows that substantially perpendicularly intersect said columns, and wherein said interconnection conductors further include:

a plurality of horizontal conductors associated with each of said rows for conveying signals substantially parallel to the associated row.

11. The apparatus defined in claim 10 wherein said programmable connections of each first region in each regular column selectively connect logic module output signals to vertical conductors associated with that column, and further selectively connect logic module output signals to horizontal conductors associated with the logic modules producing those output signals.

12. The apparatus defined in claim 11 wherein each of said programmable interconnections selectively makes a connection between a horizontal conductor and a vertical conductor.

13. The apparatus defined in claim 12 further comprising:

logic module output signal switching circuitry associated with each of said logic modules in each of said regular columns for selectively applying either the logic module output signal of the associated logic module or the logic module output signal of a logic module in said second adjacent column to said programmable connections of said regular column.

14. The apparatus defined in claim 13 further comprising:

a plurality of programmable logic module input signal selection circuits associated with each of said logic modules for selectively applying signals on horizontal conductors associated with the row that includes said logic module to said logic module as the logic module input signals of said logic module.

15. The apparatus defined in claim 3 wherein each said source of fixed programming data comprises:

a logic zero signal originator circuit;

a logic one signal originator circuit; and

switching circuitry for selecting either the signal originated by said logic zero signal originator circuit or the signal originated by said logic one signal originator circuit as said fixed programming data.

16. The apparatus defined in claim 4 wherein each said source of fixed programming data comprises:

a logic zero signal originator circuit;

a logic one signal originator circuit; and

switching circuitry for selecting either the signal originated by said logic zero signal originator circuit or the signal originated by said logic one signal originator circuit as said fixed programming data.

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BACKGROUND OF THE INVENTION

This invention relates to programmable logic array integrated circuit devices, and more particularly to the provision and use of spare circuits for performing the functions of defective circuits in such devices.

Programmable logic array integrated circuit devices with spare circuits for performing the functions of defective circuits are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,434,514. In the arrangement shown in the Cliff et al. patent an entire column--including all the logic modules in the column, the circuits which switch logic signals into and out of those logic modules, the vertical interconnection conductors of the column and the connections between those vertical conductors and the horizontal interconnection conductors of the device, and even the connections between the vertical conductors and the input/output pins served by those vertical conductors--is functionally replaced when there is a defect anywhere in the column. This strategy works well in many cases, but there are some types of defects in a column that will cause the circuitry of that column to continue to render the device unusable even if that column is functionally replaced. For example, certain types of defects in the programmable memory cells of a column may cause input multiplexers in the column (which normally bring signals from selected horizontal interconnection conductors into the logic modules of the column) to be erroneously programmed so that two or more inputs of a multiplexer are short circuited via the output of that multiplexer. This may improperly short circuit two or more horizontal interconnection conductors to one another, thereby rendering the device unusable despite the availability of circuitry for use in replacing the defective column circuitry.

In view of the foregoing, it is an object of this invention to improve the provision and use of spare circuits in programmable logic array integrated circuit devices.

It is another object of this invention to provide programmable logic array integrated circuit devices with spare circuits that can be used to replace defective circuits on the device, and at the same time to improve control of the programming of the memory cells that determine how the replaced circuits operate to minimize adverse effects of the replaced circuits on the remainder of the device.

SUMMARY OF THE INVENTION

These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices in which one or more spare columns of logic modules are provided for use when it is necessary to replace the logic modules in a defective regular column. When there is such a defective regular column of logic modules, the logic modules from an adjacent column are used as replacement modules. This shifting of logic module functions to adjacent columns continues from column to column until a spare column of logic modules is used to perform the logic module functions that would otherwise be performed by the last regular column of logic modules. Although the functions of the various logic modules may thus be shifted from column to column, the vertical interconnection conductors of each column retain their original functions because there are no spare vertical conductors in the spare column. The same is true for the switching and/or driver circuits in each column that apply signals from the logic modules to the vertical and horizontal interconnection conductors, as well as the switching and/or driver circuits that provide connections between the vertical and horizontal interconnection conductors.

Because the programmable memory cells that control the logic modules in a column are interspersed in a series with memory cells for controlling the above-mentioned switching and/or driver circuits, the data which controls the programming of the memory cells is switched dynamically between adjacent columns in order to get the programming data for particular logic modules or drivers to the memory cells for the logic modules and drivers that are to be used. For example, if a column is not involved in any replacement of defective logic modules, programming data for all logic modules and drivers in that column may be loaded into the memory cells of that column without any re-routing of any of that data to an adjacent column. But if a column is involved in a replacement of defective logic modules, driver programming data is applied to the driver memory cells in that column, but logic module programming data is shifted to an adjacent column for storage in the logic module memory cells in that column. In conjunction with this aspect of the invention, circuits are provided in memory cell chains for selectively switching programming data around the logic module memory cells in each column. This is done by switching the programming data into the logic module memory cells in an adjacent column and then back to further memory cells in the original column. Still further circuitry is provided for selectively switching "fixed" programming data (e.g., binary zeroes) into memory cells that are not being used (either because they are in an unused spare column or because they are associated with unused circuitry in a regular column). This fixed programming data ensures that the unused circuitry is not erroneously programmed (due to a circuit defect) in such a way that it would continue to cause the device to malfunction even though the unused circuitry has been taken out of service.

Although it is assumed in the foregoing that certain types of regular column circuitry are duplicated in the spare column, while other certain types of regular column circuitry are not duplicated in the spare column, it will be understood that this is only exemplary. The types of regular column circuity that are or are not duplicated in the spare column may differ in different applications of the invention.

Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of an illustrative programmable logic array integrated circuit device which can be constructed in accordance with the principles of this invention.

FIG. 2 is a more detailed, but still simplified schematic block diagram of representative portions of the circuit of FIG. 1

FIG. 3 is a simplified schematic block diagram of other aspects of representative portions of the circuit of FIG. 1 in accordance with this invention.

FIG. 4 is similar to FIG. 3 but shows the use of particular programming data flow paths in the depicted circuitry.

FIG. 5 is again similar to FIG. 3 but shows the use of other programming data flow paths in the depicted circuitry.

FIG. 6 is once again similar to FIG. 3 but shows the use of still other programming data flow paths in the depicted circuitry.

FIG. 7 is a more detailed schematic diagram of an illustrative embodiment of certain components that are employed in the preceding FIGS.

FIG. 8 is a more detailed schematic diagram of an illustrative embodiment of certain other components that are employed in earlier FIGS.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

For purposes of illustration the invention will be described in the context of programmable logic array integrated circuits of the type shown in commonly assigned, co-pending U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, which is hereby incorporated by reference herein. It will be understood, however, that many details of the circuits shown in the '795 application that are not pertinent to the present invention are omitted from this discussion and the accompanying Figures to simplify the explanation of the invention and avoid obscuring the invention. For example, the '795 application shows a device having two halves that are separated by a column of random access memory ("RAM") regions. These RAM