The invention relates to a method and a circuit for rearranging output data of a variable-length decoder (VLD). The circuit for rearranging output data of a VLD has an internal memory, a first data processor for packing a variable-length decoded bit stream in a data unit having a predetermined number or bits, generating a write address for each packed data unit to store the packed data unit in the internal memory, and generating a request signal for transmitting the stored packed data unit to an external memory, when the number of packed data units stored in the internal memory exceeds a predetermined threshold value, and a second data processor for generating respective read addresses for reading out N packed data units from the internal memory, when an accept signal is generated in response to the request signal, and applying the generated read address to the internal memory, wherein the N packed data units stored in the corresponding read address are sequentially read out from the internal memory and are transmitted to the external memory. Therefore, timing margins can be ensured through request and acceptance, and an automatic byte-alignment by start code is possible. Further, memory writing and reading timing is stabilized, and write and read banks of the memory are efficiently switched during writing and reading operations.

The invention provides a picture data decompression apparatus which reduces the time required for decompression of picture data and operates at a high speed. The picture data decompression apparatus includes a module switching section for extracting code patterns in units of n bits the compressed picture data, m decoding and dequantization modules, and an inverse orthogonal transform section for inverse orthogonal transforming decoded and dequantized data from the m decoding and dequantization means. Each of the decoding and dequantization modules decodes and dequantizes, from a code pattern in units of n bits extracted by the module switching section, only a predetermined variable length code of a single unique code pattern of n bits from among m different predetermined patterns. Each of the decoding and dequantization modules performs storage into the dequantized data buffer in order of coded coefficients without performing scanning conversion, and the inverse orthogonal transform section reads out the stored data of the dequantized data buffer designating an address and performs inverse orthogonal transform processing of the thus read out data.

The invention provides a picture data decompression apparatus which reduces the time required for decompression of picture data and operates at a high speed. The picture data decompression apparatus includes a module switching section for extracting code patterns in units of n bits the compressed picture data, m decoding and dequantization modules, and an inverse orthogonal transform section for inverse orthogonal transforming decoded and dequantized data from the m decoding and dequantization means. Each of the decoding and dequantization modules decodes and dequantizes, from a code pattern in units of n bits extracted by the module switching section, only a predetermined variable length code of a single unique code pattern of n bits from among m different predetermined patterns. Each of the decoding and dequantization modules performs storage into the dequantized data buffer in order of coded coefficients without performing scanning conversion, and the inverse orthogonal transform section reads out the stored data of the dequantized data buffer designating an address and performs inverse orthogonal transform processing of the thus read out data.

An apparatus to determine a transform of a block of encoded data the block of encoded data comprising a plurality of data elements. An input register is configured to receive a predetermined quantity of data elements. At least one butterfly processor is coupled to the input register and is configured to perform at least one mathematical operation on selected pairs of data elements to produce an output of processed data elements. At least one intermediate register is coupled to the butterfly processor and configured to temporarily store the processed data. A feedback loop is coupled to the intermediate register and the butterfly processor, and where if enabled, is configured to transfer a first portion of processed data elements to the appropriate butterfly processor to perform additional mathematical operations and where if disabled, is configured to transfer a second portion of processed data elements to at least one holding register.

A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.