 |
Description  |
|
|
BACKGROUND OF THE INVENTION
This invention relates in general to power generation circuits for
integrated circuits ("ICs") and in particular, to power generation
circuits for ICs having flash electrically erasable and programmable
read-only-memory ("flash EEPROM") cells.
ICs having flash EEPROM cells require a high voltage Vpp for programming
and erasing the flash EEPROM cells in addition to a standard logic level
voltage Vdd for reading the flash EEPROM cells. Accordingly, conventional
systems employing such ICs (hereinafter referred to as "flash EEPROM
chips") include in addition to a power supply providing the standard logic
level voltage Vdd (e.g., 5.0 volts), either a second power supply
providing the high voltage Vpp (e.g., 12.0 volts), or a DC--DC converter
generating the high voltage Vpp from the standard logic level voltage Vdd.
FIGS. 1A-1B illustrate one example of a system employing flash EEPROM
chips. In FIG. 1A, a flash EEPROM system 20 is illustrated wherein the
flash EEPROM system 20 serves as a mass storage medium for a host computer
10 by emulating a hard disk system. The host computer 10 interfaces with
the flash EEPROM system 20 by communicating conventional hard disk drive
read and write commands through system bus 15 to a controller 40 in the
flash EEPROM system 20. The controller 40 interprets the disk drive
commands from the host computer 10, and translates them into corresponding
read and write operations for a flash EEPROM module 30 in the flash EEPROM
system 20, in a manner transparent to the host computer 10. Additional
details of the operation of such a flash EEPROM system are described, for
example, in U.S. patent application Ser. No. 07/736,733, filed Jul. 26,
1991, entitled "Solid-State Memory System Including Plural Memory Module
Mounts and Serial Connections," and naming Robert D. Norman, Karl M. J.
Lofgren, Jeffrey D. Stal, Anil Gupta, and Sanjay Mehrotra as inventors,
which is incorporated herein by this reference.
In FIG. 1B, the flash EEPROM module 30 is further detailed as containing a
plurality of flash EEPROM chips, 31-1 to 31-n, wherein each flash EEPROM
chip, e.g., 31-1, is further detailed as including a plurality of flash
EEPROM cells 33 and memory circuitry 34 for accessing selected ones of the
flash EEPROM cells 33. Although not shown, the flash EEPROM cells 33 can
be further organized in a matrix array and selectively accessed through a
plurality of word lines connected to their respective control gates and a
plurality of bit lines connected to their respective drains such as, for
example, the flash EEPROM cell 33-1 of FIG. 3A.
In systems where the host computer 10 only provides a logic level voltage
Vdd to the flash EEPROM system 20, such as, for example, in a personal
computer system, the high voltage Vpp required for programming and erasing
the flash EEPROM cells in the flash EEPROM system 20 is generated within
the flash EEPROM system 20 itself. Such generation of the high voltage Vpp
may be accomplished, for example, by including in the flash EEPROM system
20 a charge pump circuit or DC--DC converter device which generates the
high voltage Vpp from the logic level voltage Vdd provided by the host
computer 10.
FIGS. 2A-2C illustrate, as examples, three configurations for such an flash
EEPROM system 20. In each of the configurations, at least one DC--DC
converter is included within the flash EEPROM system 20 for generating the
high voltage Vpp from the logic level voltage Vdd provided by the host
computer 10. In FIG. 2A, the DC--DC converter device 46 is included in the
controller 40; in FIG. 2B, the DC--DC converter device 46' is included in
the flash EEPROM module 30; and in FIG. 2C, DC--DC converter devices 46-1"
to 46-n" are each respectively included in a corresponding one of the
flash EEPROM chips 31-1 to 31-n of the flash EEPROM module 30.
In flash EEPROM systems where the controller 40 and the flash EEPROM module
30 are combined on a single printed circuit board, such as, for example,
in a memory card adapted to be inserted into a slot provided in a personal
computer, FIGS. 2A and 2B are substantially equivalent configurations.
Such a configuration is described, for example, in U.S. Pat. No. 5,267,218
entitled "Non-volatile Memory Card with a Single Power Supply Input," and
issued to Elbert, which is incorporated herein by this reference.
One problem with such a configuration as described in U.S. Pat. No.
5,267,218 is that the DC--DC converter device 46 is typically a separate
component such as an LT1109-12 DC--DC converter manufactured by Linear
Technology Corp. of Milpitas, Calif. As a consequence, the cost of this
separate component must be added to the component costs of the processor
43 and flash EEPROM chips 31-1 to 31-n, thus increasing the component cost
for the flash EEPROM system. Also, additional board space is required on
the printed circuit board to accommodate such a separate component, thus
increasing the board cost for the flash EEPROM system. Further, failure of
this separate component results in failure of the entire flash EEPROM
system, thus reducing the reliability of the flash EEPROM system. Such a
problem is similarly experienced in configurations where the controller 40
and the flash EEPROM module 30 are on separate printed circuit boards.
In FIG. 2C, each of the flash EEPROM chips 31-1 to 31-n includes a
respective one of the DC--DC converters 46-1" to 46-n". By including a
DC--DC converter on each of the flash EEPROM chips 31-1 to 31-n, the
additional component cost of a separate DC--DC converter component is
avoided, the additional board space required for the separate DC--DC
converter component is avoided, and the reliability of the flash EEPROM
system is enhanced through such redundancy. However, a major problem with
including a DC--DC converter on each of the flash EEPROM chips 31-1 to
31-n is that this approach increases the die size of the flash EEPROM
chips and as a result, the costs of the flash EEPROM chips increases
accordingly. In particular, where each of the DC--DC converters 46-1" to
46-n" is formed of a charge pump including a plurality of charge storage
devices such as capacitors, the die area required for the charge storage
devices may be considerable relative to that required for the flash EEPROM
cells and memory circuitry on the flash EEPROM chip.
In certain flash EEPROM systems, a number of voltages V1 to Vk in lieu of
or besides the high voltage Vpp may be required for properly operating the
flash EEPROM cells of the flash EEPROM chips 31-1 to 31-n. Generally,
these voltages V1 to Vk may be generated from the high voltage Vpp and/or
logic level voltage Vdd by either on-chip circuitry such as circuits 32-1
to 32-n and 32-1' to 32-n' (FIGS. 2A-2C) respectively residing on flash
EEPROM chips 31-1 to 31-n and 31-1' to 31-n', or by off-chip circuitry
(not shown) residing, for example, on a printed circuit board of the flash
EEPROM module 30, 30' or 30" (FIGS. 2A-2C, respectively). Additional
details of certain flash EEPROM cells and their operational
characteristics for one such flash EEPROM system are described, for
example, in U.S. Pat. No. 5,198,380 entitled "Method of Highly Compact
EPROM and Flash EEPROM Devices," and issued to Harari, which is
incorporated herein by this reference.
In particular, FIGS. 3A and 3B illustrate one example of such voltages V1
to Vk required to operate one flash EEPROM cell 33-1 (e.g., FIG. 3A) of a
plurality of flash EEPROM cells 33. To selectively program the flash
EEPROM cell 33-1, its source "S" may be connected to ground "GND" (e.g., 0
volts), its drain "D" connected through bit line "BL" to 8.0 volts, its
control gate "CG" connected through word line "WL" to 11.0 volts, and its
erase gate "EG" connected to 2.0 volts. To read the flash EEPROM cell
33-1, its source "S" may be connected to ground "GND", its drain "D"
connected through bit line "BL" to 1.0 volts, its control gate "CG"
connected through word line "WL" to 5.0 volts, and its erase gate "EG"
connected to 2.0 volts. To erase the flash EEPROM cell 33-1, its source
"S", drain "D" and control "CG" gates may be connected to ground "GND",
and its erase gate "EG" connected to 20.0 volts. Thus, in this simple
example, to program, read, and erase the flash EEPROM cell 33-1, voltages
of 20.0, 11.0, 8.0, 5.0, 2.0, 1.0 and ground (e.g., 0 volts) are required.
In a more complicated example, additional voltages may also be required to
verify the programming or erasing of the flash EEPROM cell 33-1.
Although described as fixed values in the above example, in practice, the
optimal values for such operating voltages V1 to Vk may vary between
different flash EEPROM chips initially (i.e., for flash EEPROM chips which
have never been programmed and/or erased before), as well as for a given
flash EEPROM chip over its operational life (i.e., for an flash EEPROM
chip having increasing numbers of programming and erasing cycles). One
reason for the optimal values of such programming, reading, and erasing
voltages V1 to Vk to be different initially is that the optimal values for
such voltages V1 to Vk are at least partially determined by the flash
EEPROM chip's manufacturing process. Thus, flash EEPROM chips originating
from different flash EEPROM manufacturers may have different optimal
values and as a consequence, flash EEPROM systems employing flash EEPROM
chips from different flash EEPROM manufacturers may have flash EEPROM
chips having different optimal values initially. Although, this problem
may be solved by including only flash EEPROM chips from one manufacturer
in a flash EEPROM system, such a solution may often times be commercially
impractical.
One reason for such optimal values to vary for a given flash EEPROM chip
over the operational life of the flash EEPROM chip is that the optimal
values for such voltages V1 to Vk for each flash EEPROM cell of the flash
EEPROM chip are at least partially determined by the number of times that
that flash EEPROM cell has been programmed and erased over its operational
life. For example, as charge accumulates in an isolation region between a
floating gate and erase gate of a flash EEPROM cell through repeated
programming and erasures of the cell, it becomes increasingly difficult to
erase the cell and consequently, higher and higher erase voltages may need
to be applied to the erase gate to completely erase the cell within a
reasonable period of time.
Conventional power generation circuits, such as those depicted in FIGS.
2A-2C, for flash EEPROM chips, however, are not adapted to providing such
optimal programming, reading, and erasing voltages over the lifetime of
their respective flash EEPROM chips. Generally, the voltages that they
provide are fixed at the time of manufacture. Consequently, the voltages
are set at a fixed level which may exceed the optimal programming,
reading, and erasing voltages for each flash EEPROM cell early in the
cell's lifetime, thus overstressing and reducing the life of the cell, and
may fall short of the optimal programming, reading, and erasing voltages
for each cell as the cell matures, thus resulting in increasing numbers of
programming and erasure failures.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a power
generation circuit to be included in a flash EEPROM system without the
previously described drawbacks of the prior art. In particular, it is an
object of the present invention to provide a technique and apparatus
capable of providing optimal programming, reading, and erasing voltages to
a flash EEPROM chip over the lifetime of the flash EEPROM chip.
These and other objects are accomplished through the various aspects of the
present invention, wherein briefly stated, one aspect is a flash EEPROM
system comprising at least one flash EEPROM chip, a controller for
controlling operations of the chip, and a programmable power source for
supplying operating power to the chip, wherein the programmable power
source is programmed by the controller in response to predefined
parameters of the flash EEPROM system.
In another aspect, a programmable voltage generator circuit for a flash
EEPROM chip comprises means for generating a high voltage and current from
a low voltage source, a plurality of registers for storing information
indicative of a plurality of voltages for programming, reading, and
erasing the flash EEPROM chip, and a plurality of digital-to-analog
converters for converting the digital information stored in the plurality
of registers into a corresponding plurality of analog voltage signals
respectively related to the plurality of voltages for programming,
reading, and erasing the flash EEPROM chip.
In still another aspect, an on-chip method of generating a plurality of
voltages suitable for programming, reading, and erasing a plurality of
flash EEPROM cells comprises the steps of: respectively storing
information indicative of the plurality of voltages in a plurality of
registers; respectively converting the information stored in the plurality
of registers into a plurality of analog signals; and respectively
generating the plurality of voltages by amplifying and regulating the
plurality of analog signals.
In still another aspect, a charge pump circuit for generating a high
voltage and current suitable for programming a flash EEPROM chip,
comprises charge storage means connected to the flash EEPROM chip, and a
plurality of transistors formed on the flash EEPROM chip and connected to
the external charge storage means such that the plurality of transistors
generate from an input voltage, an output voltage and current sufficient
to program the flash EEPROM chip.
In still another aspect, a flash EEPROM system comprises a controller, and
a flash EEPROM module having at least one surface whereupon a plurality of
flash EEPROM chips and a charge storage means are mounted, wherein each of
the flash EEPROM chips includes a plurality of transistors connected to
the charge storage means such that the plurality of transistors in a
selected one of the flash EEPROM chips generates from an input voltage, an
output voltage and current sufficient to program its respective flash
EEPROM chip, or selectably another one of the plurality of flash EEPROM
chips.
In still another aspect, a voltage generator circuit providing voltages
suitable for programming, reading, and erasing a flash EEPROM chip,
comprises a first means connected to a low voltage source for generating,
in response to a first state of a mode select signal, a high voltage and a
high current suitable for programming selected flash EEPROM cells of the
flash EEPROM chip, and a second means connected to the low voltage source
for generating, in response to a second state of the mode select signal, a
high voltage and a low current suitable for generating voltages useful for
reading and erasing selected flash EEPROM cells of the flash EEPROM chip.
Additional objects, features and advantages of the various aspects of the
present invention will become apparent from the following description of
its preferred embodiment, which description should be taken in conjunction
with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B respectively illustrate, as examples, a block diagram of a
flash EEPROM system connected to a host computer, and additional detail on
a flash EEPROM module of the flash EEPROM system;
FIGS. 2A-2C illustrate, as examples, block diagrams for three different
flash EEPROM systems;
FIGS. 3A and 3B respectively illustrate, as one example, a flash EEPROM
cell and various voltages for programming, reading, and erasing the flash
EEPROM cell;
FIG. 4 illustrates, as an example, a block diagram of a flash EEPROM system
utilizing aspects of the present invention;
FIG. 5 illustrates, as an example, an on-chip programmable power generation
circuit utilizing aspects of the present invention;
FIG. 6 illustrates, as an example, a high voltage generator circuit
utilizing aspects of the present invention, which can be employed in the
on-chip programmable power generation circuit of FIG. 5;
FIG. 7 illustrates, as an example, a multi-voltage generator/regulator
circuit utilizing aspects of the present invention, which can be employed
in the on-chip programmable power generation circuit of FIG. 5;
FIGS. 8A-8C illustrate, as an example, a high current charge pump circuit
suitable for use in the high voltage generator circuits of FIGS. 5 and 6;
FIG. 9 illustrates, as an example, a flow diagram for automatically
adjusting a voltage to be applied to an erase gate of a flash EEPROM cell
each time the flash EEPROM cell is to be erased; and
FIG. 10 illustrates, as an example, certain features of a flash EEPROM chip
utilizing aspects of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 4 illustrates a flash EEPROM system 20' utilizing aspects of the
present invention. The flash EEPROM system 20' functions as a mass storage
medium for a host computer in a similar fashion as the flash EEPROM system
20 described in reference to FIG. 1A. Included within the flash EEPROM
system 20' are a controller 40' and an flash EEPROM module 466, wherein
devices having the same reference numbers in FIG. 4 and FIGS. 2A-2C are to
be understood as having identical functions and constructions. In
particular, the same reference number is used for the controller in FIG. 4
as the controllers in FIGS. 2B and 2C, because it is similarly constructed
and operated. On the other hand, a different reference number is used for
the flash EEPROM module in FIG. 4 from the flash EEPROM modules in FIGS.
2A-2C, because it is different in construction and operation.
The controller 40' includes a processor 43 and a memory 41 mounted on a
printed circuit board 472, wherein the functions of the processor 43 and
the memory 41 are substantially the same as their identically referenced
counterparts in FIGS. 2A-2C. The flash EEPROM module 466 includes a
plurality of flash EEPROM chips 468-1 to 468-n and a charge storage unit
464' mounted on a printed circuit board 470. The controller printed
circuit board 472 and the flash EEPROM module printed circuit board 470
are mounted on a third printed circuit board 471 which provides structural
support and electrical connectivity functions. Each of the flash EEPROM
chips 468-1 to 468-n includes an on-chip programmable power generation
circuit, e.g., 50-1 to 50-n, which generates the programming, reading, and
erasing voltages V1 to Vk required for the operation of flash EEPROM cells
on the flash EEPROM chip, e.g., 468-1 to 468-n. Each of the on-chip
programmable power generation circuits 50-1 to 50-n include a switching
circuit, e.g., 462-1 to 462-n, which in conjunction with the charge
storage unit 464' generate a high voltage Vpp from a logic level voltage
Vdd and supply that high voltage Vpp to other circuitry in its respective
programmable power generation circuit, e.g., 50-1 to 50-n, so that the
other circuitry can generate the programming, reading, and erasing
voltages V1 to Vk. Although the controller 40' and flash EEPROM module 466
are shown to be on different printed circuit boards, 472 and 470,
respectively, it is to be appreciated that the various aspects of the
present invention are equally applicable to embodiments wherein the
controller 40' is included on the same printed circuit board as the flash
EEPROM module 466.
To generate the high voltage Vpp (e.g., 12 volts) from the lower logic
level voltage Vdd (e.g., 5 volts or 3 volts), each of the switching
circuits, e.g., 462-1 to 462-n, combine with the charge storage unit 464'
to form a charge pump circuit, such as, for example, the charge pump
circuit depicted in FIGS. 8A-8C. In particular, discrete capacitors 3205,
3206, 3405, and 3406 of FIGS. 8A-8C are preferably mounted on the printed
circuit board 470 (or alternatively, on the printed circuit board 471) to
form the charge storage unit 464', and the remaining FET circuitry of
FIGS. 8A-8C are preferably included on each of the flash EEPROM chips
468-1 to 468-n to form the switching circuitry 462-1 to 462-n. As shown in
FIG. 4, each of the switching circuits, e.g., 462-1 to 462-n, not only
provides the high voltage Vpp to other circuitry in its respective
programmable power generation circuit, e.g., 50-1 to 50-n, but also
through a bus 52 formed on flash EEPROM module 466 to other programmable
power generation circuits, e.g., 50-1 to 50-n, formed on other flash
EEPROM chips 468-1 to 468-n within the flash EEPROM module 466.
The structure of flash EEPROM module 466 as illustrated in FIG. 4, has
numerous advantages over each of the flash EEPROM modules 30, 30', and 30"
as illustrated respectively in FIGS. 2A-2C. For example, with respect to
flash EEPROM modules 30 and 30', the separate DC--DC converters, 46 and
46', respectively depicted in FIGS. 2A and 2B, have been eliminated, and
functioning in their place in flash EEPROM module 466 are switching
circuitry 462-1 to 462-n respectively formed on flash EEPROM chips 468-1
to 468-n which selectably act in conjunction with common charge storage
unit 464' formed, for example, on the printed circuit board 470 of the
flash EEPROM module 466. Since the charge storage unit 464' is preferably
formed of discrete capacitors (e.g., 3205, 3206, 3405, and 3406 of FIGS.
8A-8C), the component costs of such a charge storage unit 464' is
considerably less than that of a typical DC--DC converter. Further, the
board space occupied by such a charge storage unit 464' is considerably
less than the board space occupied by a typical DC--DC converter. Although
switching circuitry 462-1 to 462-n are respectively added to flash EEPROM
chips 468-1 to 468-n, the die size of the flash EEPROM chips 468-1 to
468-n are negligibly increased by such addition. Further, redundancy of
such switching circuitry 462-1 to 462-n adds to the reliability of the
flash EEPROM module 466, as will be elaborated upon below.
Further, with respect to flash EEPROM module 30", the charge storage
portions of charge pumps 46-1" to 46-n" depicted in FIG. 2C have been
eliminated, and functioning in their place in flash EEPROM module 466 is a
common charge storage unit 464' mounted, for example, on the printed
circuit board 470 of flash EEPROM module 466 and shared by each of the
flash EEPROM chips 468-1 to 468-n through bus 52 of the flash EEPROM
module 466. The elimination of the charge storage portions from each of
the flash EEPROM chips significantly reduces the die size of these chips
since the charge storage portions are conventionally formed of a plurality
of capacitors or inductors which tend to require a relatively large
portion of the die area for their formation. On the other hand, by forming
the switching circuitry of the charge pumps on each of the flash EEPROM
chips, the advantages obtained by such redundancy are available at minimal
cost in terms of increased die size. Operational costs and reliability of
the flash EEPROM module 466 are also enhanced relative to the flash EEPROM
module 30", because the charge storage devices in the charge storage unit
464' are relatively inexpensive and can be easily replaced without
discarding any of the relatively expensive flash EEPROM chips 468-1 to
468-n in flash EEPROM module 466, which would be the case in the event
that one of the charge storage units became dysfunctional in charge pumps
46-1" to 46-n" of flash EEPROM chips 31-1' to 31-n' in flash EEPROM module
30". Further, an additional feature of the flash EEPROM module 466 is that
the high voltage Vpp can be not only generated in any selected one of the
flash EEPROM chips 468-1 to 468-n, but also, that the high voltage Vpp
generated by one of the flash EEPROM chips 468-1 to 468-n can be
selectively provided to any one of the other flash EEPROM chips 468-1 to
468-n via bus 52 of the flash EEPROM module 466.
FIG. 5 illustrates a block diagram including major components of the
programmable voltage generators 50-1 to 50-n (referred to hereinafter as
simply programmable voltage generator 50 since each of the programmable
voltage generators 50-1 to 50-n are identically constructed). The heart of
the programmable voltage generator 50 is a multi-voltage generator 400
which generates and regulates the voltages V1 to Vk for programming,
reading, and erasing selected ones of the flash EEPROM cells from
information stored in the multi-voltage generator 400 by the controller
40. Other major components include a high voltage generator 300 which
generates a high voltage Vpp for the multi-voltage generator 400, and
various logic 410-424 for storing the information indicative of the
voltages V1 to Vk into the multi-voltage generator 400 by the controller
40'.
In a preferred embodiment, the controller 40' serially provides voltage
information indicative of one of the voltages V1 to Vk followed by
information indicative of where such voltage information is to be stored
in the multi-voltage generator 400 to serial protocol logic 410, via
serial input SERIAL IN and clock signal CLOCK of bus 42". In response, the
serial protocol logic 410 latches the voltage information into data latch
416, via bus 412 and control signal PCMD, and provides the information
indicative of where the latched voltage information is to be stored in the
multi-voltage generator 400 to address decoder 414, via bus 420 and
control signal PPWR. The address decoder 414 in turn, decodes the
information indicative of where the latched voltage information is to be
stored in the multi-voltage generator 400, and enables an appropriate
register in the multi-voltage generator 400 by activating a corresponding
one of the enabling connections REGe-1 to REGe-n.
FIG. 6 illustrates a block diagram further detailing the high voltage
generator circuit 300. The high voltage generator circuit 300 generates
the high voltage Vpp from one of three sources, as selected by the
controller 40'. The first source Vpp(opt) is an off-chip source preferably
provided from another flash EEPROM chip in the same flash EEPROM module.
For example, as shown in FIG. 4, each of the flash EEPROM chips 468-1 to
468-n on flash EEPROM module 466 has a programmable voltage generator 50-1
to 50-n respectively residing on it which can generate the high voltage
Vpp and make the generated high voltage Vpp available to any one of the
other flash EEPROM chips 468-1 to 468-n via common bus 52. One advantage
of such an arrangement is that if for some reason the other two sources
for generating the high voltage Vpp in a high voltage generator circuit
300 are not functioning, then the high voltage generator 300 can still
provide the high voltage Vpp to other circuitry on its chip from the
external source.
The second of the three sources for generating the high voltage Vpp is a
high current charge pump circuit 3000 which is connected to external
capacitors CAP1 to CAPn. An example of such a high current charge pump
circuit 3000 is depicted in FIGS. 8A-8C, wherein the external capacitors
CAP1 to CAPn are shown as capacitors 3205, 3206, 3405, and 3406 and the
high current charge pump circuit 3000 comprises the remainder of the FET
circuitry depicted in FIGS. 8A-8C which are connected to the external
capacitors 3205, 3206, 3405, and 3406 at nodes 3207 and 3209, 3208 and
3210, 3407 and 3409, and 3408 and 3410, respectively. By placing the
capacitors 3205, 3206, 3405, and 3406 off-chip (i.e., not including them
on the flash EEPROM chips 468-1 to 468-n), the physical size of these
capacitors can be relatively large without impacting the die size of the
flash EEPROM chips 468-1 to 468-n and as a consequence, their current
providing capacity which is proportional to their physical size, can be
relatively large without impacting the die size of the flash EEPROM chips
468-1 to 468-n.
The third of the three sources for generating the high voltage Vpp is a low
current charge pump circuit 3800 which, unlike the high current charge
pump circuit 3000, includes internal capacitors (not shown). The low
current charge pump circuit 3800 can be formed of any one of numerous
conventional charge pump types. Because the capacitors of the low current
charge pump circuit 3800 are formed on-chip (i.e., including them on each
of the flash EEPROM chips 468-1 to 468-n), in order to maintain reasonable
die sizes for the flash EEPROM chips 468-1 to 468-n, they are relatively
smaller than their external capacitor counterparts CAP1 to CAPn of the
high current charge pump circuitry 3000 and as a consequence, they provide
correspondingly less current. Although generally inadequate for flash
EEPROM cell programming purposes, the current provided by the low current
charge pump circuit 3800 is adequate, however, for flash EEPROM cell
reading and erasing purposes. For flash EEPROM cell programming purposes,
the higher current provided by the high current charge pump circuit 3000
is required.
The controller 40' activates one of the three sources for generating the
high voltage Vpp through control signals Vpp, and SVpp/SVdd. When low
current capability is required, for example, when reading or erasing the
flash EEPROM cells, the controller 40' may activate any one of the three
sources for generating the high voltage Vpp, although preferably the low
current charge pump circuit 3800 would be activated to reduce power
consumption. On the other hand, when high current capability is required,
for example, when programming the flash EEPROM cells, the controller 40'
deactivates the low current charge pump circuit 3800 by making control
signal Svpp/SVdd HIGH which causes an enabling circuit 3710 of
conventional construction to disable the low current charge pump circuit
3800. The high current Vpp is then selectably provided from either the
external source Vpp(opt) or the high current charge pump circuit 3000 by
the controller 40' making control signal Vppe either LOW or HIGH,
respectively, which causes an enabling circuit 3700 of conventional
construction to dis | | |
