Serial scan chain architecture for a data processing system and method of operation

Claims

What is claimed is:

1. A data processor having a scan chain architecture, the scan chain architecture comprising:

a plurality of scan chains wherein each scan chain in the plurality of scan chains has a plurality of serially connected storage elements, each scan chain having a first storage element which has a scan input and a last storage element which has a scan output;

a multiplexer having a plurality of inputs wherein each input in the plurality of inputs is coupled to one scan output from the plurality of scan chains, the multiplexer having a multiplexer output wherein the multiplexer output is selectively coupled to one of the inputs in the plurality of inputs via the multiplexer;

a demultiplexer having a plurality of outputs wherein each output in the plurality of outputs is coupled to one scan input from the plurality of scan chains, the demultiplexer having a demultiplexer input wherein the demultiplexer input is selectively coupled to one output in the plurality of outputs via the demultiplexer; and

an output scan chain having an input coupled to the output of the multiplexer and an output coupled to an output terminal of the data processor, the multiplexer serially coupling the output scan chain to a selected one of the plurality of scan chains to form a total scan chain comprising the selected one of the plurality of scan chains and the output scan chain.

2. The data processor of claim 1 wherein one of the scan chains in the plurality of scan chains is used to serially scan binary data for a circuit module selected from a group consisting of: an operand cache unit, and instruction cache unit, a bus interface unit, an integer processing unit, and a floating point unit.

3. The data processor of claim 1 wherein the demultiplexer is part of a test controller which receives a plurality of test address signals wherein the plurality of test address signals selects one scan chain in the plurality of scan chains to receive a serial bit stream via a serial data input coupled to the demultiplexer input.

4. A data processor comprising:

a plurality of circuit modules;

a plurality of internal storage elements in each circuit module, the plurality of internal storage elements in each circuit module being connected in a serial manner to form an internal scan chain in each circuit module, each internal scan chain having an input and an output wherein the input of each internal scan chain is coupled to a test controller and the output of each internal scan chain is coupled to a multiplexer; and

a plurality of output storage elements in each circuit module, the plurality of output storage elements in each circuit module being different from the plurality of internal storage elements in each circuit module, the plurality of output storage elements in each circuit module being connected in a serial manner to form an output scan chain which is continuous through each circuit module, the output scan chain in each circuit module having an input and an output wherein the inputs and outputs of each of the output scan chains are coupled so that all the output scan chains in the circuit modules are coupled in a serial manner wherein the multiplexer selectively couples one internal scan chain and at least one output scan chain together in a serial manner to a scan data output terminal.

5. The data processor of claim 4 wherein the output scan chain comprises both output storage elements from the circuit modules and storage elements which are coupled to input and output terminals of the data processor.

6. The data processor of claim 4 wherein the test controller has a demultiplexer which is used to direct a serial bit stream from a serial input to one internal scan chain in the data processor.

7. The data processor of claim 6 wherein other internal scan chains which are different from the one internal scan chain in the data processor receive deasserted signals while the one internal scan chain in the data processor receives the serial bit stream, the deasserted signals being used in order to reduce power consumption in the data processor.

8. The data processor of claim 6 wherein other internal scan chains are kept in a serial shift mode to keep deasserted signals shifting through the other internal scan chains while the one internal scan chain in the data processor is functioning in a mode other than the serial shift mode.

9. The data processor of claim 4 wherein the test controller receives as input a serial data stream from an input terminal of an integrated circuit package which contains the data processor.

10. The data processor of claim 4 wherein the test controller receives as input a serial data stream from an the internal scan chains and routes the serial data stream to a terminal of an integrated circuit package which contains the data processor.

11. The data processor of claim 10 wherein the serial data stream is logically altered by a logic circuitry coupled to the multiplexer.

12. The data processor of claim 4 wherein the test controller receives as input an address which is used to select one internal scan chain among internal scan chains as a destination for a serial stream of input data.

13. The data processor of claim 4 wherein the output storage elements of a selected circuit module are time-sequential last storage elements in the circuit module which communicate signals external to the circuit module.

14. The data processor of claim 4 wherein the output storage elements of a selected circuit module are a set of last storage elements encountered within the selected circuit module before a signal exits the selected circuit module.

15. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element;

a second multiplexer having a first input coupled to the output of the local storage element, a second input coupled to a data input, a select input, and an output coupled to the first input of the first multiplexer; and

a logic gate having a first input for receiving an enable signal, a second input for receiving a speed path control signal, and an output coupled to the select input of the second multiplexer.

16. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output; and

a multiplexer having a first input coupled to receive a serial stream of data, a second input coupled to receive data signals, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element.

17. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive an enable signal, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element; and

a second multiplexer having a first input coupled to the data output of the local storage element, a second input coupled to a data input, a select input coupled to a serial data input, and an output coupled to the first input of the first multiplexer.

18. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output; and

a logic gate for clearing a value stored in the local storage element.

19. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element;

a second multiplexer having a first input coupled to the output of the local storage element, a second input coupled to a data input, a select input coupled to a control signal, and an output coupled to provide output data; and

a third multiplexer having a first input coupled to the data input, a second input coupled to the data output of the storage element, a select input for receiving an output control signal, and an output coupled to the second input of the first multiplexer.

20. The data processor of claim 4 wherein a storage element in one of either the internal scan chains or the output scan chains comprises:

a local storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input coupled to the data output of the local storage element, a select input for receiving a select control signal, and an output coupled to the data input of the local storage element; and

a second multiplexer having a first input coupled to a data input, a second input coupled to the output of the storage element, a select input for receiving an output control signal, and an output.

21. The data processor of claim 4 wherein a circuit module contains a memory wherein the memory has memory outputs, the memory outputs being coupled to memory storage elements wherein the memory storage elements are coupled in series and coupled within one output scan chain.

22. A data processor comprising:

a scan chain having a plurality of serially connected storage cells, each serially connected storage cell comprising:

a storage element having a clock input for receiving a clock signal, a data input, and a data output;

a first multiplexer having a first input coupled to receive a serial stream of data, a second input, a select input for receiving a select control signal, and an output coupled to the data input of the storage element;

a second multiplexer having a first input coupled to the output of the storage element, a second input coupled to a data input, a select input, and an output coupled to the first input of the first multiplexer; and

a logic gate having a first input for receiving an enable signal, a second input for receiving a speed path control signal, and an output coupled to the select input of the second multiplexer.

23. A method for providing a serial data stream to a data processor, the method comprising the steps of:

providing an address to a test controller, the address coupling one serial scan chain from a plurality of scan chains internal to the data processor to an input terminal, each scan chain in the plurality of scan chains having a plurality of serially connected storage elements, the serially connected storage elements of each scan chain defining a circuit module boundary wherein all the serially connected storage elements of each scan chain are within the circuit module boundary;

using the address to couple the one serial scan chain selectively to an output scan chain wherein the output scan chain is a serially connected plurality of storage elements from a plurality of different circuit modules defined by the circuit module boundaries; and

serially shifting the serial data stream into both the output scan chain and the one serial scan chain via the input terminal.

24. The method of claim 23 wherein the step of serially shifting comprises:

serially shifting deasserted values into an unselected serial scan chain, which is different from the one serial scan chain, while the serial data stream is being shifted into the one serial scan chain.

25. The method of claim 23 further comprising the step of:

placing the data processor into a serial shift mode to perform the step of serially shifting.

26. The method of claim 25 further comprising the step of:

placing the data processor into a parallel normal mode of operation after the step of serially shifting to alter a state of the data processor.

27. The method of claim 26 wherein the step of placing comprises:

serially shifting deasserted values into an unselected serial scan chain, which is different from the one serial scan chain, while the serial data stream is being shifted into the one serial scan chain; and

continuing to serially shift deasserted values into the unselected serial scan chain during a time that the one serial scan chain is operating in the parallel normal mode of operation.

28. The method of claim 23 wherein the step of serially shifting comprises:

reducing logic transitions in other serial scan chains which are not selected by the step of providing an address.

FIELD OF THE INVENTION

The present invention relates generally to data processing systems, and more particularly, to serial scan chains in a data processing system.

BACKGROUND OF THE INVENTION

In modern integrated circuit design, a microprocessor is designed in functional blocks, each of which perform a certain task. Some functional blocks are, for example, a prefetch unit, a pipeline execution unit, a cache, a bus interface unit, a floating point execution unit, and the like. These functional blocks have many inputs and output which are coupled to other inputs and outputs of other functional blocks which are not accessible by external pins/terminals. Therefore, if one would want to test, for example, an operand cache unit in isolation, the task would be very complex since the inputs and outputs of the operand data cache (or any functional block for that matter) cannot be accessed readily via the integrated circuit external pins/terminals. In addition, since the external pins/terminals do not have direct access to a functional block's inputs and outputs, setting initial test conditions and reading test results or output values is extremely complicated. A method for testing functional blocks in an efficient manner is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in a block diagram, a serial scan chain architecture in accordance with the present invention;

FIG. 2 illustrates, in a block diagram, the a data processor having a serial scan chain architecture in accordance with the present invention;

FIGS. 3-10 illustrate, in circuit diagrams, serial scan chain storage cells which are used to form the scan chains illustrated in FIGS. 1-2;

FIG. 11 illustrates, in a circuit diagram, the MUX 24 of FIG. 1;

FIG. 12 illustrates, in a timing diagram, the scan and test operation of the system of FIGS. 1-2 for speed path testing;

FIG. 13 illustrates, in a block diagram, the low power mode operation of the circuit of FIG. 1; and

FIG. 14 illustrates, in a block diagram form, a circuit which is speed path tested using the method and apparatus from FIGS. 1-13.

It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the FIGURES have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the FIGURES to indicate corresponding or analogous elements.

DESCRIPTION OF A PREFERRED EMBODIMENT

In order to understand the present invention, the next several pages will discuss scan architecture and methods in an overview manner. In addition, in the following first few paragraphs, the prior art is compared to the method taught herein in order to differential on a global scale some major differences without going into exact detail. Following these introductory paragraphs, the FIGURES are discussed in detail to specifically discuss the novel scan method and structure.

The present invention provides a scan test architecture for use with a full-scan partitioned logic design (a plurality of functional circuit blocks within a single integrated circuit) implementation that is based upon a single serial scan access port with a single scan shift control port and can conduct scan tests at or above the rated frequency of the integrated circuit in such a manner that frequency dependent faults can be detected and isolated within any targeted partition block within the integrated circuit (IC).

Generally, a FULL-SCAN TEST ARCHITECTURE can be designed into any integrated circuit that is structured so that all of the sequential elements (flip-flops or latches) in the circuit have both a normal data input for a normal mode of computational operation and a scan data input wherein all scan data inputs are coupled in series via a scan path. The serial connection of all the flip-flops or latches via a scan path forms a typically large scan shift register which may be anywhere from two flip-flops in length to thousands of flip-flops in serial length. This serial coupling of storage elements (flip-flops, latches, registers, and the like) allows the state of the integrated circuit to be set to any initial state by serially shifting data into the sequential elements. Once the state is set via the serially shifting through scan data in pins, the circuit can be run in the normal mode of operation (not the scan mode of initial state set-up) for one or more clock cycles to capture the circuits response to the previously scanned-in state.

In many integrated circuits, the scan mode is changed to the normal mode of parallel operation by transitioning a control signal that makes the sequential elements capture data from their functional inputs (normal data inputs) instead of the scan shift inputs. The application of serial state data, transitioning of the control signal or signals, and the collection of the serial response data (i.e., the output of the circuit in response to the initial state) is usually conducted by a tester external to the circuit (such as an Advantest or a Teradyne tester) although built in self test (BIST) is possible and more autonomous.

Therefore, the minimum requirements of a simple FULL-SCAN TEST ARCHITECTURE is to (1) provide the serial input to the internal serial scan shift register, (2) to provide the scan shift/sample control signal, (3) to provide the connections between sequential elements that allow the scan shift register to be constructed, and (4) to provide the serial output of the scan shift register.

Since the inclusion of a simple FULL-SCAN TEST ARCHITECTURE in an integrated circuit design has significant circuit costs in: (1) physical substrate area; (2) transistor and/or logic element count; and (3) performance, there must be some advantage to using it as opposed to other test architectures and methodologies. The most common reasons for newer ICs being designed having a scan architecture are consistency of design and use and independence of application (i.e., any digital circuit regardless of function can be tested by a scan test methodology and tested in a consistent fashion regardless of function). The reduction of test vector generation time by the use of software automatic-test-pattern-generation tools (ATPG), and the reduction of test pattern application time on the tester (thereby reducing the cost of testing) are also advantages of a scan architecture.

There are, however, some cases and conditions that exist where the simple FULL-SCAN TEST ARCHITECTURE is not sufficient to provide the advantages stated above. For example: (1) the number of logic gates on the IC is so large that an ATPG tool cannot operate on the whole device as a single unit; (2) the placing of all sequential elements into a single scan shift register would create a serial sequential depth that exceeds the reasonable memory depth of the tester and requires a long time period to shift in the individual vectors; (3) the existence of non-standard logic constructs such as global chip distributed three-state busses or tri-state buses that can have multiple drivers "in contention" during scan testing; (4) the requirement to speed sort the device by verifying that certain "speed paths" meet their clock-edge to clockedge window; and (5) the requirement to support fault classes other than the single stuck-at fault model that is predominantly associated with scan testing (for example bridging faults, gate AC delay faults, current leakage faults, and path AC delay faults). The above criterion render many prior art scan methods less desirable.

Therefore, a true all-encompassing, widely accepted, and advantageous FULL-SCAN TEST ARCHITECTURE must provide the capability to not only scan test the device, but to provide solutions to all of the adverse conditions listed above. The scan architecture described in the FIGURES herein provides all of these capabilities in a manner wherein many functional elements are shared with scan test elements so that far fewer logical circuit elements are used than the current known state of the art scan implementations.

In overview, the system and method described herein uses a functionally partitioned, multiple selectable, scan chain architecture with a common concatentable "functional" boundary (or partitioning) scan chain, where all of the sequential elements and three-state drive devices used are from a specific restricted set of logic elements. This specific FULL-SCAN TEST ARCHITECTURE provides the capability to independently test a plurality of functional blocks from a single scan test port, one block at a time, where testing occurs at the rated device frequency (or in excess of the rated frequency) of the processor. Therefore, this method and scan architecture minimizes the pin impact of the IC and the test interface requirements to the tester while keeping the logic-under-test size reasonable for an automatic-test-pattern-generation (ATPG) software tool. In addition, the scan chain methodology taught herein incorporates various low power options not available in previous scan methods. The scan method taught herein is significantly different from scan chain architectures that are based on the LSSD methodology which requires a latched base scan chain and multiple test clocks, or clocked flip-flop based scan that relies on gated clock signals to perform the logic partitioning.

In the method/architecture taught herein, the overall IC device is partitioned into smaller disjoint functional blocks where each functional block has its own independent scan chain. All of these independent scan chains are coupled in a parallel manner as illustrated in FIG. 1 herein. Each functional block can undergo testing separately and independently and allows a level of diagnostic isolation within that block. The partitioning of the IC device into disjoint functional blocks for test purposes is problematic in itself since it now creates a set of input and output signals that are buried within the device and are not directly accessible to the external package pins. For example, a bus interface unit (BIU) may be one internal functional block while a operand cache unit (OCU) may be a different functional isolated block wherein each have their own scan chains. Each of the BIU and the OCU may have block inputs and block outputs that are not accessible by I/O pins, input pins, and/or output pins of the integrated circuit (IC) package. In order to conduct scan testing on a partitioned block, the internal sequential elements must be set to a known state by the scan shift operation while simultaneously applying logic signals to the block input signals which may come from some other functional block. This problem is solved herein by the addition of a "partitioning" block output scan chain to the architecture.

After the scan sample cycle (i.e., the testing of the IC by applying clock cycle(s) after scanning in initial data), the state of the scan chain must be shifted out while the state of the partitioned block's outputs are being observed. The problem of providing the inputs to the block was solved by unders