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This application is related to copending applications Ser. Nos. 08/073,005
filed Jun. 7, 1993 Pat. No. 5,408,190; 08/124,899 filed Sep. 21, 1993,
Pat. No. 5,495,179; 08/046,675 filed Apr. 14, 1993, Pat. No. 5,367,253;
08/073,003 filed Jun. 7, 1993; 08/120,628 filed Sep. 13, 1993; 08/192,023
filed Feb. 3, 1994; 07/896,297 filed Jun. 10, 1992, Pat. No. 5,424,652;
08/192,391 filed Feb. 3, 1994, Pat. No. 5,483,174; and, 08/137,675 filed
Oct. 14, 1993.
FIELD OF THE INVENTION
This invention relates to semiconductor manufacture and to methods for
testing the operability of unpackaged semiconductor dice having raised or
bumped bond pads. In addition, this invention relates to methods for
fabricating an interconnect suitable for testing the operability of
integrated circuitry on an unpackaged semiconductor die formed with raised
or bumped bond pads.
BACKGROUND OF THE INVENTION
Because of a trend towards multi-chip modules, semiconductor manufacturers
are required to supply unpackaged dice that have been tested and certified
as known good die (KGD). Known good die is a collective term that denotes
unpackaged die having the same reliability as the equivalent packaged die.
The need for known good die has led to the development of test apparatus in
the form of temporary carriers suitable for testing discrete, unpackaged
semiconductor dice. As an example, test apparatus for conducting burn-in
tests for discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett
et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to
Micron Technology, Inc. Other test apparatus for discrete die are
disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No.
5,073,117 to Malhi et al., which are assigned to Texas Instruments.
With this type of test apparatus, a non-permanent electrical connection
must be made between contact locations on the die, such as bond pads, and
external test circuitry associated with the test apparatus. The bond pads
provide a connection point for testing the integrated circuitry formed on
the die.
In making this temporary electrical connection, it is desirable to effect a
connection that causes as little damage as possible to the bond pad. If
the temporary connection to a bond pad damages the pad, the entire die may
be rendered as unusable. This is difficult to accomplish because the
connection must also produce a low resistance or ohmic contact with the
bond pad. A bond pad typically includes a metal oxide layer that must be
penetrated to make an ohmic contact.
Some prior art contact structures, such as probe cards, scrape the bond
pads which wipes away the oxide layer and causes excessive damage to the
bond pads. Other interconnect structures such as probe tips may pierce
both the oxide layer and the metal bond pad and leave a deep gouge. Still
other interconnect structures, such as microbumps, may not even pierce the
oxide layer preventing the formation of an ohmic contact.
Another important consideration in testing of known good die is the effect
of thermal expansion during the test procedure. As an example, during
burn-in testing, a die is heated to an elevated temperature and maintained
at temperature for a prolonged period. This causes thermal expansion of
the die and temporary interconnect. If the die and the temporary
interconnect expand by a different amount, stress may develop at the
connection point and adversely effect the electrical connection. This may
also lead to excessive damage of bond pads.
One type of semiconductor dice having a raised topology is referred to as a
"bumped" die. A "bumped" semiconductor die includes bond pads formed with
a bump of solderable material such as a lead-tin alloy. Bumped dice are
often used for flip chip bonding wherein the die is mounted face down on a
substrate, such as a printed circuit board, and then attached to the
substrate by welding or soldering. Typically the bumps are formed as balls
of material that are circular in a cross sectional plane parallel to the
face of the die. The bumps typically have a diameter of from 50 .mu.m to
100 .mu.m. The sides of the bump typically bow or curve outwardly from a
flat top surface. The flat top surface forms the actual region of contact
with a mating electrode on the printed circuit board or other substrate.
In the past, following testing of a bumped die, it has been necessary to
reflow the bumps, which are typically damaged by the test procedure. This
is an additional process step which adds to the expense and complexity of
the testing process. Furthermore, it requires heating the tested die which
can adversely affect the integrated circuitry formed on the die.
OBJECTS OF THE INVENTION
In view of the need in the art for improved methods for testing unpackaged,
bumped, semiconductor dice, it is an object of the present invention to
provide an improved method of testing unpackaged semiconductor dice having
raised or bumped bond pads.
It is a further object of the present invention to provide an improved
method for forming a temporary interconnect adapted to test semiconductor
die having raised or bumped bond pads.
It is a further object of the present invention to provide an improved
method for fabricating temporary interconnects for bumped semiconductor
dice that uses semiconductor manufacturing techniques and that provides an
improved contact structure.
Other objects, advantages and capabilities of the present invention will
become more apparent as the description proceeds.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method of testing,
and an improved method for fabricating a temporary interconnect for
testing unpackaged semiconductor dice having raised contact locations
(e.g., bumped bond pads) are provided. The improved method of testing
includes a temporary interconnect adapted to establish an electrical
connection with raised contact locations on the die without damage to the
contact locations. The interconnect includes a substrate (e.g., silicon)
having contact members formed in a pattern that matches the size and
spacing of the contact locations on the die. The contact members on the
interconnect include one or more sharpened projections. The sharpened
projections are adapted to penetrate the raised contact locations on the
die and to pierce any residual insulating material to establish an ohmic
connection.
The sharpened projections are formed integrally with the substrate using an
etching process or using an oxidation growth process. The sharpened
projections are formed either on a surface of the substrate, or in a
recess in the substrate which is sized to retain the raised contact
locations on the die. In addition, the sharpened projections are formed
with a size and shape which permits penetration into the contact locations
but with a self-limiting penetration depth. In an illustrative embodiment,
the sharpened projections are formed as an array of parallel elongated
blades. Depending on the method of formation, the elongated blades can be
formed in a variety of cross sectional configurations (e.g., triangular,
rounded profile, flat tops). In addition, the elongated blades can be
formed in a spaced array or with no spaces therebetween.
The sharpened projections are formed on an insulating layer of the
interconnect substrate and are covered with a conductive layer. The
conductive layer can be formed as a single layer of a highly conductive
metal such as aluminum or iridium, or a conductive material such as
polysilicon. Conductive traces or runners are formed in electrical contact
with the conductive layer to establish an electrical pathway to and from
the contact members of the interconnect.
The conductive layer for the contact members can also be formed as a stack
comprising two different layers of material. An outer layer of the stack
is preferably a metal such as platinum, which is chemically inert and
provides a barrier layer that will not react with the raised material
(e.g., bump) at the contact location on the die. The inner layer of the
stack can be a metal such as aluminum or titanium which can be easily
bonded to conductive traces. The inner layer and conductive traces can
also be formed of a same material.
The conductive layer can also be formed as a metal silicide. A metal
silicide can be formed by depositing a silicon containing layer and a
metal layer on the sharpened projections and reacting these layers to form
a metal silicide. The unreacted portions of the silicon containing layer
and metal layer are then etched selective to the metal silicide using a
salicide process.
A method for fabricating a temporary interconnect in accordance with the
invention, includes the steps of: forming a substrate; forming an array of
contact members on the substrate as one or more elongated sharpened
projections adapted to penetrate a raised contact location (e.g., bump) on
a die to a limited penetration depth; forming an insulating layer (e.g.,
SiO.sub.2, Si.sub.3 N.sub.4) over the entire substrate including the
sharpened projections; forming a conductive layer over the sharpened
projections; and then forming conductive traces on the substrate in
electrical communication with the conductive layer. Optionally, the
sharpened projections can be mounted within an indentation formed in the
substrate that is adapted to retain the raised contact location on the
die.
Preferably a large number of interconnects are formed on a single substrate
or wafer. This substrate can then be diced (e.g., saw cut) to singulate
the interconnects. In use, the temporary interconnect is placed in a
temporary carrier (i.e., test apparatus) along with the die, and an
electrical path is established between the conductive traces on the
interconnect and external test circuitry associated with the test
apparatus.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross sectional view illustrating a substrate and a
mask layer during an initial process step for forming an interconnect in
accordance with the invention;
FIG. 2 is a schematic cross sectional view of the substrate taken along
section line 2--2 of FIG. 3 showing the mask layer after patterning and
etching to form a mask having solid areas and openings;
FIG. 3 is a perspective view of FIG. 2;
FIG. 4 is a cross sectional view showing formation of the sharpened
projections on the substrate using the mask layer and an etch process;
FIG. 5A is a cross sectional view taken along section line 5A--5A of FIG. 6
showing the sharpened projections formed on the substrate with a
triangular cross section using an anisotropic etch process;
FIG. 5B is a cross sectional view, equivalent to FIG. 5A, showing the
sharpened projections formed on the substrate with a rounded profile using
an isotropic etch process;
FIG. 5C is a cross sectional view equivalent to FIG. 5A showing the
sharpened projections formed on the substrate with a truncated pyramidal
cross section, using an anisotropic etch process;
FIG. 5D is a cross sectional view equivalent to FIG. 5A showing the
sharpened projections formed on the substrate using an anisotropic etch
with no spaces in between the projections;
FIG. 5E is a cross sectional view showing the sharpened projections formed
on the substrate using an oxidation growth process;
FIG. 6 is a perspective view of the substrate and sharpened projections
shown in FIG. 5;
FIG. 7 is a cross sectional view of the substrate and sharpened projections
showing the formation of an insulating layer over the substrate;
FIG. 8 is a cross sectional view of the substrate and sharpened projections
showing the formation of a conductive layer on the sharpened projections;
FIG. 8A is a cross sectional view of the substrate and sharpened
projections showing the formation of a conductive layer on the sharpened
projections comprising a stack of two different metal layers;
FIG. 8B is a cross sectional view of the substrate and sharpened
projections showing the formation of a conductive layer on the projections
formed of a metal silicide;
FIG. 9 is a plan view of an interconnect formed in accordance with the
invention;
FIG. 10 is a cross sectional view illustrating testing of an unpackaged
semiconductor die using an interconnect formed in accordance with the
invention and showing the sharpened projections electrically engaging a
bumped contact location of the die; and
FIG. 10A is a cross sectional view illustrating testing of an unpackaged
semiconductor die in accordance with the invention using an alternate
embodiment contact structure in which the sharpened projections are
mounted within an indentation formed in the substrate.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 1, a process for forming an interconnect 10 for
testing unpackaged semiconductor dice having raised contact locations,
such as bumped bond pads, is shown. The interconnect 10 includes a
substrate 12 formed of a material having a coefficient of thermal
expansion (CTE) that closely matches the CTE of a silicon die. Suitable
materials for the substrate include monocrystalline silicon,
silicon-on-glass, silicon-on-sapphire, germanium, or ceramic.
The substrate 12 includes a planar outer surface 14 having a mask layer 16
of a material such as silicon nitride (Si.sub.3 N.sub.4) formed thereon. A
typical thickness for the mask layer 16 is about 500 .ANG. to 3000 .ANG..
The mask layer 16 may be formed using a suitable deposition process such
as CVD.
Next, as shown in FIG. 2, the mask layer 16 is patterned and etched
selective to the substrate 12 to form a hard mask that includes masking
blocks 18, 20, 24, 26 and openings therebetween. Depending on the
materials used for the mask layer 16, this etch step may be performed
using a wet or dry etch. As an example, a layer of silicon nitride may be
etched with a pattern of openings using hot (e.g., 180.degree. C.)
phosphoric acid.
As shown in the perspective view of FIG. 3, the masking blocks 18, 20, 24,
26 are elongated rectangular blocks. In addition, the masking blocks 18,
20, 24, 26 are formed in a parallel spaced array. The peripheral
dimensions of the array are selected to accommodate the dimensions of a
raised contact location on a semiconductor die. As an example, the raised
contact location can be a bond pad having a metal bump with a diameter of
from 1 .mu.m-500 .mu.m. As is apparent however, such a parallel spaced
array is merely exemplary and other configurations are possible. Other
suitable arrangements for the masking blocks include enclosed rectangles,
squares, triangles, T-shapes and X-shapes.
Next, as shown in FIG. 4, elongated sharpened projections 40, 42, 44, 46
are formed on the substrate 12. The sharpened projections 40, 42, 44, 46
can be formed using an etching process (anisotropic or isotropic), using
an oxidation process, or using a deposition process.
With etching, a wet or dry isotropic, or anisotropic, etch process is used
to form the sharpened projections 40, 42, 44, 46 as the material under the
masking blocks 18, 20, 24, 26 is undercut by the etchant reacting with the
substrate 12. In other words, the exposed substrate 12 between the masking
blocks 18, 20, 24, 26 etches faster than the covered substrate 12 under
the blocks 18, 20, 24, 26.
Following the etching process the masking blocks 18, 20, 24, 26 are
stripped using a wet etchant such as H.sub.3 PO.sub.4 that is selective to
the substrate 12. For an anisotropic etch, in which the etch rate is
different in different directions, an etchant solution containing a
mixture of KOH and H.sub.2 O can be utilized. As shown in FIG. 5A, this
results in the formation of triangular shaped sharpened projections 40,
42, 44, 46. This triangular shape is a function of the different etch
rates of monocrystalline silicon along the different crystalline
orientations. The surface of the substrate 12 represents the (100) planes
of the silicon which etches faster than the sloped sidewalls that
represent the (110) plane. For a silicon substrate 12, the slope of the
sidewalls of the sharpened projections is about 54.degree. with the
horizontal. For forming the triangular shaped sharpened projections 40,
42, 44, 46 the width of the masking blocks 18, 20, 24, 26 and the
parameters of the etch process are controlled to form a pointed tip 58 on
each projection 40, 42, 44, 46.
For an isotropic etch, in which the etch rate is the same in all
directions, an etchant solution containing a mixture of HF, HN03 and H20
can be utilized. As shown in FIG. 5B, this results in sharpened
projections 40B, 42B, 44B, 46B having a pointed tip 58B and a rounded
sidewall contour. In this embodiment the sidewalls of the sharpened
projections 40B, 42B, 44B, 46B are undercut below the masking blocks 18,
20, 24, 26 (FIG. 4) with a radius "r". The value of the radius "r" is
controlled by the etch parameters (i.e., time, temperature, concentration
of etchant) and by the width of the masking blocks 18, 20, 24, 26 (FIG.
4).
FIG. 5C illustrates another embodiment wherein the sharpened projections
40C, 42C, 44C, 46C are formed with a cross section of a truncated pyramid
with a flat tip 58C. In this embodiment an anisotropic etch is used. In
addition, the width of the masking blocks 18, 20, 24, 26 and parameters of
the etch process (e.g., time, temperature, concentration of etchant) are
controlled to form the flat tip 58C.
FIG. 5D illustrates another embodiment wherein the sharpened projections
40D, 42D, 44D, 46D are formed in a saw tooth array with no spaces between
the base portions. In this embodiment an anisotropic etch is used and the
process parameters, including the etch time and width of the masking
blocks 18, 20, 24, 26 are controlled to provide a desired height and tip
58D to tip 58D spacing.
Alternately, in place of an isotropic or anisotropic etch process, the
sharpened projections can be formed using an oxidizing process. This is
shown in FIG. 5E. With an oxidizing process the substrate 12E may be
subjected to an oxidizing atmosphere to oxidize exposed portions of the
substrate 12 not covered by the masking blocks 18E, 20E, 24E, 26E. As an
example, the oxidizing atmosphere may comprise steam and O.sub.2 at an
elevated temperature (e.g., 950.degree.C.). The oxidizing atmosphere
oxidizes the exposed portions of the substrate 12 and forms an oxide layer
49 (e.g., silicon dioxide). At the same time, sharpened projections 40E,
42E, 44E and 46E are formed under the masking blocks 18E, 20E, 24E, 26E.
With an oxidizing process, the oxide layer 49 can also be stripped using a
suitable wet etchant such as HF.
The sharpened projections can also be formed by a deposition process out of
a different material than the substrate 12. As an example, a CVD process
can be used to form the sharpened projections out of a deposited metal.
Referring now to FIG. 6, which represents the structure after completion of
the process illustrated by FIG. 5A, the sharpened projections 40, 42, 44,
46 are formed in an array of parallel spaced, elongated, knife edges which
form a contact member 43. The contact member 43 has an overall peripheral
dimension adapted to accommodate the size of a raised contact location
(e.g., bumped bond pad) on a semiconductor die. Although multiple
sharpened projections are formed for each contact member 43, it is to be
understood that a single sharpened projection per contact member 43 would
also be suitable.
The sharpened projections 40, 42, 44, 46 project from a surface 56 of the
substrate 12 and include pointed tips 58 and bases 60. The bases 60 of
adjacent sharpened projections 40, 42, 44, 46 are spaced from one another
a distance sufficient to define a penetration stop plane 62 there between.
The function of the penetration stop plane 62 will be apparent from the
continuing discussion. Example spacing between bases 60 would be 10 .mu.m,
while an example length of the bases 60 and tips 58 would be from 3 to 10
.mu.m. The height of each sharpened projections 40, 42, 44, 46 is
preferably about one-thousandth (1/1000) to one-quarter (1/4) the diameter
of a bumped bond pad on a semiconductor die. This height is selected to
allow good electrical contact and at the same time provide minimum damage
to raised contact locations (e.g., bumps) on dice that are typically
tested using the interconnect 10 and then used for flip chip bonding. As
an example, this projecting distance of the sharpened projections 40, 42,
44, 46, from the substrate 12 will be on the order of 1 to 3 .mu.m.
Subsequent to formation of the sharpened projections 40, 42, 44, 46,
additional etching may be used to further sharpen the tips 58.
Following the formation of the sharpened projections 40, 42, 44, 46 and as
shown in FIG. 7, an insulating layer 64 is formed over the entire
substrate 12 including the contact member 43. The insulating layer 64 can
be formed of a material such as SiO.sub.2 by exposing the substrate 12 to
an oxidizing atmosphere for a short time or by using a CVD process. The
insulating layer 64 can also be formed of a material such as Si.sub.3
N.sub.4.
Next, as shown in FIG. 8, a conductive layer 66 is formed on the insulating
layer 64 and in an area of the substrate overlying each contact member 43.
The conductive layer 66 can be formed of a highly conductive metal, such
as aluminum (Al), iridium (Ir), copper (Cu), titanium (Ti), tungsten (W),
tantalum (Ta), molybdenum (Mo) or alloys of these metals. A suitable
metallization process to form the conductive layer 66 can include the
steps of deposition (e.g., sputter, CVD), patterning (e.g.,
photopatterning) and etching (e.g., wet or dry etch).
The conductive layer 66 can also be formed of a conductive material such as
doped polysilicon. As an example, an LPCVD process can be used to form a
conductive layer 66 out of polysilicon doped with phosphorus.
As shown in FIG. 8A, a conductive layer 66A can also be formed as a stack
of two materials. The stacked conductive layer 66A includes a barrier
layer 68 and a bonding layer 70. The barrier layer 68 is formulated to
prevent formation of an oxide layer that would change the resistivity of
the contact member 43. In addition, the barrier layer 68 is formulated to
prevent reaction of the conductive layer 66A with the contact location
(e.g., metal bump 88--FIG. 10) on the die and prevent the diffusion of
impurities from the contact location on the die to the bonding layer 70
and vice versa.
The barrier layer 68 is preferably a metal that will not easily form a
"permanent" or "chemical" bond with a raised metal contact location on the
die even under a large mechanical force (e.g., 10 lb./interconnect) and at
high temperatures. In addition, this metal must be chemically stable
(i.e., non reactive) for temperatures up to about 200.degree. C. By way of
example, the barrier layer 68 can be formed of a metal such as platinum
(Pt), titanium (Ti) or a titanium alloy (e.g., TiN, TiW).
The bonding layer 70 is formulated to provide a good mechanical bond with
conductive traces 72A that are subsequently formed on the substrate 12 out
of a highly conductive material. By way of example, the bonding layer 70
can be formed of aluminum (Al), tungsten (W) or titanium (Ti). In some
applications the bonding layer 70 can be formed of a same material as the
conductive traces 72A using a single masking step.
As shown in FIG. 8B, a conductive layer 66B can also be formed by
depositing a silicon containing layer 76 (e.g., polysilicon, amorphous
silicon) and a metal layer 78, and reacting these layers to form a metal
silicide 78A. A typical thickness of the silicon containing layer 76 would
be from about 500 .ANG.to 3000 .ANG..
The metal layer 78 is formed of a metal that will react with the silicon
containing layer 76 to form a metal silicide. Suitable metals include the
refractory metals, such as titanium (Ti), tungsten (W), tantalum (Ta),
platinum (Pt) and molybdenum (Mo). In general, silicides of these metals
(WSi.sub.2, TaSi.sub.2, MoSi.sub.2, PtSi.sub.2 and TiSi.sub.2) are formed
by alloying with a silicon surface. Other suitable metals include cobalt
(Co), nickel (Ni), molybde | | |
