Video game card having interrupt resistant behavior

Claims

We claim all modifications and variation coming within the spirit and scope of the following claims:

1. A video game card for interfacing a game controller having one or more analog input devices to a personal computer including a microprocessor having digital data and control buses and a card slot for receiving I/O cards, the game card comprising:

a circuit board for mounting electrical components and connectors thereupon, the circuit board sized to fit in the card slot of the personal computer;

a game card connector for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device;

a bus connector for connecting the circuit board to the computer data and control bus; and

a game card circuit for providing to the microprocessor a digital signal corresponding to the analog signal level, the circuit including means for asserting the digital signal responsive to a "write" to the game card by the personal computer microprocessor and means for deasserting the digital signal responsive to a number of "reads" sent to the game card by the personal computer, the "read" at which the digital signal is deasserted being determined from the analog signal level.

2. A video game card according to claim 1 wherein the circuit includes:

means for converting the analog signal to a binary count; and

means for counting the number of "reads" sent to the game card by the personal computer microprocessor;

the means for deasserting the digital signal being operative to deassert said signal when the number of "reads" is equal to or greater than the binary count.

3. A video game card according to claim 2 wherein the converting means includes an analog to digital converter.

4. A video game card according to claim 3 wherein the converting means includes a resistance to voltage circuit interposed between the analog signal and the analog to digital converter for receiving the analog signal and converting the analog signal to an analog voltage signal.

5. A video game card according to claim 2 wherein the circuit includes a means for storing the binary count.

6. A video game card according to claim 2 wherein the deasserting means includes a comparator for comparing the binary count to the number of "reads."

7. A video game card according to claim 1 wherein the game card connector receives a plurality of said analog signals from the game controller, each analog signal having a signal level corresponding to the state of a corresponding game controller input device; the game card further comprising one of said game card circuits for each analog signal.

8. A video game card according to claim 7 wherein the game card circuits comprise:

a plurality of latches, each latch storing a binary count corresponding to each analog signal level;

means for counting the number of "reads" sent to the game card by the personal computer microprocessor; and

a plurality of comparators having first and second inputs and an output, the first input of each comparator being coupled to the counting means and the second input of each comparator being coupled to a corresponding latch for comparing the counter count to the binary count of the corresponding latch, the output of each comparator indicating the result of the comparison.

9. A video game card according to claim 8 wherein the game card circuit includes a means for providing the comparator outputs to the personal computer microprocessor responsive to a "read" sent to the game card by the microprocessor.

10. A video game card according to claim 1 wherein the circuit for providing a digital signal to the microprocessor corresponding to the analog signal level includes:

means for establishing a ramp voltage, the ramp voltage being increased responsive to a "read" by the personal computer microprocessor; and

means for comparing the ramp voltage to the analog signal level, the comparing means asserting the digital signal when the ramp voltage is equal to or greater than the analog signal level and deasserting the digital signal when the ramp voltage is less than the analog signal level.

11. A video game card according to claim 10 wherein the means for establishing a ramp voltage includes:

a counter for counting the number of reads by the personal computer microprocessor; and

a voltage generator coupled to the counter, the voltage generator generating a ramp voltage proportional to the counter count.

12. A video game card according to claim 11 wherein the means for comparing the ramp voltage to the analog signal level includes:

a comparator having a first input coupled to the voltage generator for receiving the ramp voltage, a second input coupled to the game card connector for receiving the analog signal from the game controller, and an output for producing the digital signal; and

a current sink coupled to the second input.

13. A video game card according to claim 12 wherein the comparator includes:

an operational amplifier having a first input, a second input, and an output; and

an impedance network coupled to the operational amplifier.

14. A method of signalling to a digital personal computer a state of a controller input device having an analog signal corresponding to said state via a digital signal on a game card, the method comprising:

sampling the analog signal;

converting the sample to a binary count;

detecting a "write" sent by the personal computer to the game card;

asserting the digital signal responsive to the detected "write";

detecting a "read" sent by the personal computer to the game card;

counting the number of "reads" since the "write";

comparing the number of "reads" to the binary count; and

deasserting the digital signal when the number of "reads" is equal to or exceeds the binary count.

15. A method of signalling to a digital personal computer the state of a controller input device according to claim 14 wherein the step of sampling the analog signal includes converting the analog signal to an analog voltage signal.

16. A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of converting the sample to a binary count includes storing the binary count.

17. A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of counting the number of "reads" since the "write" includes incrementing a counter responsive to each detected "read."

18. A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of asserting the digital signal responsive to the detected "write" includes setting a flip-flop to an asserted state.

19. A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of deasserting the digital signal when the number of "reads" is equal to the binary count includes setting a flip-flop to a deasserted state.

20. A method of signalling to a digital personal computer the state of a controller input device according to claim 15 wherein the step of detecting a "write" sent by the personal computer to the game card includes:

assigning a game card address to the game card;

comparing an address received from the personal computer with the assigned game card address; and

detecting a "write" when the received address is equal to the game card address.

21. A method of signalling to a digital personal computer the state of a controller input device according to claim 20 wherein the step of assigning a game card address to the game board includes selecting one of a plurality of game card addresses.

22. A method of signalling to a digital personal computer the state of a controller input device according to claim 15 further including repeating each step for a plurality of analog signals corresponding to a plurality of controller input devices.

23. A video game/simulation system for simulating operation of a complex system having a plurality of user-controlled functions, the system comprising:

a computer having a microprocessor operable under control of a video game/simulation program, a display for displaying images produced by the program, and an input/output bus for connecting peripheral input and output devices to the microprocessor by producing a peripheral address and exchanging data therewith;

a video game/simulator controller having a plurality of input devices, each input device having an analog signal line for transmitting an analog signal corresponding to the state of the input device;

an interrupt resistant game card coupled to the input/output bus and having a game card connector coupled to the analog signal lines for receiving the corresponding analog signals from the video game/simulator controller, the game card having means for converting each analog signal to a corresponding digital signal, and means for asserting the digital signals responsive to a "write" sent to the game card by the computer microprocessor and deasserting the digital signals responsive to a number of "reads" sent to the game card by the computer, the "read" at which a digital signal is deasserted being determined by a level of the corresponding analog signal;

means in the computer for writing to the game card;

means in the computer for reading from the game card to receive the plurality of digital signals corresponding to the plurality of input devices of the video game/simulator controller; and

means for effecting a corresponding change in the displayed images produced by the program responsive to the received digital signals.

24. A video game/simulation system according to claim 23 wherein the means for converting the analog signals to corresponding digital signals includes, for each analog signal:

means for asserting the corresponding digital signal responsive to the "write" sent to the game card by the computer microprocessor;

means for converting the analog signal to a binary count;

means for counting the number of "reads" sent to the game card by the computer microprocessor; and

means for deasserting the digital signal when the number of "reads" is equal to or greater than the binary count.

25. A video game/simulation system according to claim 23 wherein the means for converting the plurality of analog signals to a corresponding plurality of digital signals includes:

means for establishing a ramp voltage, the ramp voltage being increased responsive to a "read" by the computer microprocessor; and

means for comparing the ramp voltage to the analog signal level, the comparing means asserting the digital signal when the ramp voltage is equal to or greater than the analog signal level and deasserting the digital signal when the ramp voltage is less than the analog signal level.

26. A video game/simulation system according to claim 23 wherein the interrupt resistant game card includes:

a first connector coupled to the analog signal lines of the input device for receiving the corresponding plurality of analog signals from the controller; and

a second connector for receiving a plurality of analog signals from a second controller.

27. A video game card for interfacing a game controller having one or more input devices to a computer including a microprocessor having data and control buses and a card slot for receiving I/O cards, the game card comprising:

a circuit board for mounting electrical components and connectors thereupon, the circuit board sized to fit in the card slot of the personal computer;

a game card connector for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device;

a bus connector for connecting the circuit board to the computer data and control bus;

means for converting the analog signal to a corresponding numeric representation responsive to a "write" sent to the game card by the computer; and

means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer, computer responsive to a "read" sent to the game card by the computer;

the game card connector including a plurality of analog signals from the game controller; and

the means for converting the analog signal to a corresponding numeric representation including means for converting each analog signal to a corresponding numeric representation; and

means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer includes means for providing the plurality of said numeric representations at a single address;

the means for providing the plurality of numeric representations of said analog signals at a single address including:

a loadable counter;

logic means for loading the counter with an initial count responsive to a "write" sent to the game card by the computer and incrementing the counter responsive to a "read" sent to the game card by the computer; and

means for selecting one of the plurality of numeric representations corresponding to the counter count responsive to a "read" sent to the game card by the computer.

28. A video game card according to claim 27 wherein the means for selecting one of the plurality of numeric representations includes:

a plurality of latches, each latch storing a numeric representation for a corresponding analog signal; and

a decoder interposed between the counter and the plurality of latches, wherein the decoder receives the counter count and enables one the plurality of latches specified by the count responsive to a "read" sent to the game card by the computer.

29. A video game card according to claim 27 wherein the means for converting each analog signal to a corresponding numeric representation includes:

an analog multiplexer having a plurality of inputs coupled to the game card connector for receiving the plurality of analog signals from the game controller and an output for providing a selected one of the plurality of analog signals as a multiplexer output signal; and

a converter circuit coupled between the analog multiplexer and the analog to digital converter for converting the multiplexer output signal to a voltage signal and providing the voltage signal to the analog to digital converter.

30. A game controller interface for interfacing the game controller to a computer, the computer being capable of executing "write" operations to the interface and "read" operations from the interface, the interface comprising:

a connector connectable to the game controller for receiving an analog signal from the game controller, the analog signal having a signal level corresponding to a state of a corresponding game controller input device;

means for converting the analog signal to a corresponding numeric representation;

means for providing the numeric representation of the analog signal to the computer responsive to a "read" sent to the game card by the computer during a first mode; and

a circuit for providing to the computer a digital signal corresponding to the analog signal level during a second mode, the circuit including means for asserting the digital signal responsive to a "write" sent to the interface by the computer and means for deasserting the digital signal responsive to a number of "reads" sent to the interface by the computer, the "read" at which the digital signal is deasserted being determined from the analog signal level.

31. A game controller interface according to claim 30 further comprising means for switching between the first mode and the second mode.

32. A game controller interface according to claim 30 wherein the means for switching between the first mode and the second mode includes an address decoder for decoding a first address during the "write" corresponding to the first mode and a second address during the "write" corresponding to the second mode.

33. A game controller interface according to claim 32 wherein the means for switching between the first mode and the second mode includes:

means for selecting the first address; and

means for selecting the second address.

34. A game controller interface according to claim 33 wherein the means for selecting the first address and the means for selecting the second address include a jumper block.

35. A game controller interface according to claim 30 wherein the means for deasserting the digital signal responsive to a number of "reads" includes means for recording the number of "reads" since the last "write."

36. A game controller interface according to claim 35 wherein the recording means includes a voltage ramp generator, the voltage ramp generator generates a ramp voltage that is proportional to the number of "reads" since the last "write."

37. A game controller interface according to claim 36 wherein the voltage ramp generator includes:

a digital-to-analog converter; and

a counter coupled to the digital-to-analog converter for providing a count thereto, the counter count being incremented responsive to a "read" and being cleared responsive to a "write."

38. A game controller interface according to claim 35 wherein the recording means includes a counter for storing a read count, the read count being incremented responsive to a "read" and being cleared responsive to a "write."

39. A game controller interface according to claim 38 further comprising a comparator having a first input coupled to the counter for receiving the read count, a second input coupled to the converting means, and an output for providing a result signal corresponding to the results of the comparison.

40. A game controller interface according to claim 39 wherein the comparator is a greater-than or equal-to comparator.

41. A game controller interface according to claim 39 wherein the comparator is an equal-to comparator and wherein the circuit further includes a memory element coupled to the comparator, the memory element being asserted responsive to a "write" and being deasserted responsive to a positive result from the comparator.

BACKGROUND OF THE INVENTION

This invention relates generally to video game systems and more particularly to game cards therefor.

A game card is used to interface external game controllers to personal computers. These game controllers are typically used to provide input to a video game or simulation program running on the personal computer. The game card provides a standard interface to the game controllers as described in U.S. Pat. No. 5,245,320 issued to Bouton. The standard game card interface includes four discrete inputs and four analog or variable inputs. The discrete inputs are used to input discrete digital signals, such as produced by switches, to the personal computer. The analog inputs are used to input continuously variable inputs such as those generated by potentiometers.

The personal computer periodically polls the discrete inputs of the game card to determine the state of the corresponding discrete input devices. Reading these discrete inputs directly presents no problem because the discrete switch outputs are in fact digital signals that can be read directly by the personal computer microprocessor on its data bus. The microprocessor, however, cannot directly determine the state of the input devices coupled to the analog inputs because the purely digital microprocessor cannot accept analog signals.

To allow the microprocessor to determine the state of the input devices coupled to the analog inputs, the game card includes a timer circuit that converts the analog signal level to corresponding pulse width. The timer signal is initially asserted responsive to a "write" to the game card by the microprocessor. A "write" is an output operation performed by the microprocessor responsive to execution of a write instruction ("OUT") fetched from memory. A write to the game card, which is located at a predetermined address in the PC's memory map, generates a plurality of control signals that enable the game card to receive the written data. Similarly, a "read" is an input operation performed by the microprocessor responsive to the execution of a read instruction ("IN") fetched from memory. A read from the game card, i.e., at the predetermined address, enables the game card to provide the requested data to the microprocessor.

The "write" sets a one shot RC circuit in the timer which causes the timer signal to be asserted. The signal thereafter decays as a decaying exponential function of the analog signal level. Thus, the higher the analog signal level, the longer the decay of the timer signal. The microprocessor thereafter continuously polls the timer signal until it detects the timer signal deasserted. The personal computer can then determine the analog signal level from the pulse width of the timer signal. This sequence is shown in FIG. 1.

FIG. 1 shows a conventional method employed by the microprocessor for processing the analog input signals of the game card. First, a counter is initialized to zero in 12. Next, the usual microprocessor interrupts are disabled in 14 to ensure that the routine is not preempted by an interrupt service routine. If the interrupts were not disabled, the computer would lose its frame of reference during an interrupt service routine and thereby compromise the accuracy of the pulse width determination. Next, the microprocessor fires the single shots of the timer at 16 by writing to a predetermined address in the game card. In an IBM-compatible personal computer this address is equal to 0201H. The microprocessor then enters a loop comprising steps 18 and 20 where the timer signal is read and, if asserted, i.e. high, the counter is incremented. This sequence continues until the timer signal is deasserted, at which point the interrupts are reenabled in 22. Thereafter, the analog signal level is calculated based on the counter value. This calculation is in two steps. First the timer signal pulse width is determined. This pulse width is determined by multiplying the counter value by the time per loop iteration. Once the timer signal pulse width is determined, the corresponding analog signal level is ascertained by a predetermined function, typically residing in a lookup table.

There are several problems with the above-described method. The first is that the interrupts must be disabled to maintain accuracy. If the interrupts were not disabled, and the procedure was interrupted in its inner loop, for example, the timer signal would continue to decay while the microprocessor was servicing the interrupt. This lost time would compromise the accuracy of the resulting analog signal level calculation. The problem with disabling interrupts is that other tasks that are interrupt driven go unserviced while the interrupts are disabled. For example, in a video game, the screen is typically updated responsive to an interrupt. Thus, while the microprocessor is processing the timer signals, the screen goes unupdated. This can result in choppy images being displayed, which compromises the life likeness and continuity of the video game. This problem is exacerbated by modern pre-emptive multi-tasking operating systems which depend heavily on interrupts.

Another problem with the prior art approach is that the counter value can become extremely large in fast personal computers. The increase in clock rates and I/O speeds means the personal computer can read the game card rapidly, thereby increasing the counter value accordingly. As the counter value gets above a certain point, the computations involved in determining the analog signal level become complex as well. In particular, full 32-bit multiplication is required to determine the timer pulse width. This added complexity further increases the time required to process the analog inputs of the game card.

Accordingly, a need remains for a game card that does not need to disable interrupts and yet maintains a high degree of accuracy in determining the analog input signal levels.

SUMMARY OF THE INVENTION

It is, therefore, an object of the invention to provide a game card for a personal computer which can operate without disabling interrupts while achieving precision accuracy.

The game card according to the invention includes a circuit board for mounting electrical components and connectors thereon which is adapted to be received by the personal computer. The game card includes a game card connector for receiving analog signals from a game controller as well as discrete signals therefrom. The analog signals indicate the variable state of a corresponding controller input device such as a joystick handle. The circuit board includes a bus connector for connecting the circuit board to the personal computer data and control busses. In the preferred embodiment, this bus connector is a male edge type connector. The game card further includes a circuit means for providing a digital signal to the microprocessor corresponding to the signal level of a respective analog signal. The digital signal is asserted responsive to a "write" to the game card by the personal computer microprocessor and is deasserted responsive to a number of "reads" by the microprocessor. The number of "reads" which is required before the digital signal is deasserted is determined by the analog signal level.

Thus, the pulse width of the resulting digital signal is a function of the number of reads and not decay rate of the analog signal level. This aspect of the invention permits operation of the personal computer microprocessor to read the game card outputs to be interrupted for one or more microprocessor cycles while maintaining accuracy in pulse width determination. This feature allows the game card to be used without the interrupts being disabled.

In another aspect of the invention, the game card includes means for converting the analog signals to a corresponding numeric representation and providing the numeric representation to the personal computer responsive to a "read" to the game card by the personal computer. In the preferred embodiment, the game card includes an analog to digital converter which samples the analog signal level and produces a corresponding numeric representation. The numeric output of the analog to digital converter is then provided to the personal computer microprocessor over the personal computer data bus. Because the game card occupies but a single address in the personal computer address space, this embodiment of the invention further includes a means for providing a plurality of different numeric representations corresponding to different analog signals at the same single address. This means includes, in the preferred embodiment, a loadable counter which is loaded with an initial address responsive to a "write" to game card by the microprocessor. The game card then provides a numeric value corresponding to the initial address responsive to a "read" from the game card by the microprocessor. The game card thereafter provides the numeric value of a subsequent analog input responsive to subsequent "reads" by the microprocessor. In this manner, all of the plurality of numeric values are provided over a single address.

An advantage of the present invention is an increase in speed and accuracy in determining the analog signal levels.

Another advantage of the present invention is to simplify the computations that are required to compute the analog signal levels.

A further advantage of the present invention is the elimination of the non linearity of the RC timer circuit in the prior art timer circuit.

The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart for a prior art method of processing the analog signals of a prior art game card.

FIG. 2 is a pictorial drawing of a video game system using a game card according to the invention.

FIG. 3 is a block diagram of the game card according to the invention.

FIG. 4 is a schematic of a resistance to voltage converter of FIG. 3.

FIG. 5 is a schematic of a logic block of FIG. 3.

FIG. 6 is a flow chart for a method of processing analog input signals of the game card according to a first aspect of the invention.

FIG. 7 is a schematic of a logic block of FIG. 3.

FIG. 8 is a flow chart of a method of processing analog signals of a game card according to a second aspect of the invention.

FIG. 9 is a schematic of an alternative embodiment of a game card according to the invention.

FIG. 10 is a schematic of the bus interface logic of FIG. 9.

DETAILED DESCRIPTION

Referring now to FIG. 2, a video game system 26 according to the invention is shown. This system includes a personal computer 28, which includes a microprocessor (not visible) for executing a video game application program and other software operating thereon. Although in the preferred embodiment, the personal computer is an IBM compatible computer, the invention hereinafter described can be interfaced to any computer operable under the control of a video game or simulation program. The term "computer" as used herein includes all computers, regardless of the underlying operating system, e.g., DOS, Windows, UNIX, etc., or the number and/or type of processor, as well as video game platforms such as those manufactured by Nintendo, SEGA, Atari, 3DO, etc.

A display 30 is coupled to the personal computer (PC) via a display cable 31, as is known in the art. The system includes a joystick controller 32 which has a handle 34 and a plurality of discrete input devices 36. The handle 34, as known in the art, is coupled to a potentiometer which produces a variable or analog signal responsive to movement of the handle. The level of the resulting analog signal indicates the position of the handle. The system 26, as shown in FIG. 2, also includes a second throttle controller 38, which also includes a handle 40 and a plurality of discrete input devices 42. The discrete input devices 42 are discrete switches that generate a discrete or digital signal responsive to actuation thereof.

The throttle controller 38 is coupled to the PC 28 by a game card 44, which is the focus of the current invention. The game card 44 includes a printed circuit board 46 which is adapted to be received in a slot of the PC, as is known in the art. The slot in the PC includes guide rails (not visible) that receive the lateral ends of the game card 44 and guide the game card into the PC. The game card 44 includes a bus connector 47, which in the preferred embodiment is a male edge connector that mates with a compatible female connector in the PC. The game card further includes two game card connectors 48 and 50, which are adapted to receive a mating connector 51 of the controller 38. Although the joystick controller 32 is shown connected to the throttle controller 38, the joystick 32 can be connected to the game card connector 48 as well. The game card 46 is referred to as a dual ported game card because it has two game card connectors.

In the preferred embodiment, the controller 38 is coupled to a keyboard interface port 54 of the PC 28, while the PC keyboard 52 is connected to the throttle controller 38. This configuration allows the throttle controller to transmit key codes to the personal computer that correspond to the discrete and/or analog inputs of the controllers 32 and 38. However, some or all of the analog game controllers 32 and 38 are coupled to the game card 44 via a cable 53. The cable 53 includes at least 8 conductors. Four of these conductors are dedicated to providing discrete signal inputs to the game card while the other four are for providing analog input signals thereto.

In operation, the personal computer 28 generates images on the display 30 according to the video game program executing thereon. The video game receives discrete and analog inputs via the game card and modifies or adjusts the displayed images responsive thereto. An example of such a video game is "Falcon" manufactured by Spectrum Holobyte.

Referring now to FIG. 3, a block diagram of the electrical components mounted on the game card 44 is shown generally at circuit 56. The block diagram is a simplified block diagram in that it only shows the components necessary to support a single game card connector or port. The invention hereinafter described can readily be extended to support both connectors by one having ordinary skill in the art. As will be apparent to those having such skill, extending the invention to cover both connectors requires essentially duplicating the circuitry shown in FIG. 3.

The game card circuit 56 has several inputs. The first set of inputs are the analog inputs 58. These analog inputs receive the analog input signals produced by the game controller. Another set of inputs and outputs are the discrete inputs 60, which receive the discrete input signals of the controller. The inputs 58 and 60 are included in the game card connector 50, as shown in FIG. 2. Another set of inputs are the PC data and control busses 62 and 64, respectively. The busses 62 and 64 are coupled to the edge connector 47. The data bus 62 is an 8-bit bidirectional bus, as defined by the bus architecture of the PC. The control bus 64 includes not only the standard control lines, as are known in the art, but also the address lines of the PC bus.

The analog inputs 58 are coupled to an analog multiplexer 66. This multiplexer includes a plurality of inputs (0-3), a select input (MUXSEL) and a single multiplexer output (MUXOUT). The multiplexer 66 provides one of the analog inputs to the multiplexer output responsive to an address applied to a multiplexer select input (MUXSEL). In the preferred embodiment, the analog multiplexer 66 includes eight analog switched, e.g., 74LS4051, selectable by a 3-to-8 decoder such as a 74LS138.

The output of the analog multiplexer 66 is connected to a circuit 68 which will develop a voltage signal that is proportional over a specific range of resistances to the resistance of the analog input 58. A schematic of the resistance to voltage converter is shown in FIG. 4. This circuit includes two major subsections. The first section includes a bipolar transistor Q1 having a base, a collector and an emitter and a set of four resistors, R.sub.B1, R.sub.B2, R.sub.C, R.sub.E.

This section is a fixed-current sink set up to draw constant current I