 |
Claims  |
|
|
What is claimed is:
1. A voltage detector circuit for detecting whether a first supply voltage
exceeds a predetermined voltage as the first supply voltage ramps towards
its final value comprising:
a first transistor having a first terminal coupled to the first supply
voltage, a second terminal coupled to a first node, and a control
electrode coupled to receive a first voltage that varies as the first
supply voltage ramps towards its final value, the first transistor being
operative to set the first node to a logic high level in response to the
first voltage when the first supply voltage exceeds the predetermined
voltage; and
a second transistor having a first terminal coupled to the first node, a
second terminal coupled to system ground, and a control electrode coupled
to receive a second voltage that varies as the first supply voltage ramps
towards its final value, the second transistor being operative to set the
first node to a logic low level when the first supply voltage is less than
the predetermined voltage, wherein the first and second voltages are such
that a difference in potential between the control electrode of the first
transistor and the first terminal of the first transistor is always
approximately equal to a difference in potential between the control
electrode of the second transistor and the second terminal of the second
transistor.
2. The voltage detector circuit of claim 1, further comprising:
a voltage divider circuit including a plurality of resistive devices
coupled in series between the first supply voltage and system ground,
wherein each of the first and second voltages is received from a different
node between resistive devices.
3. A voltage detector circuit for determining when a first supply voltage
exceeds a predetermined voltage as the first supply voltage ramps towards
its final value, comprising:
a plurality of resistive devices coupled in series between the first supply
voltage and system ground;
a first transistor coupled to the first supply voltage and an output node,
the first transistor receiving a first biasing voltage that varies as the
first supply voltage ramps towards its final value from a first node
defined between a first pair of resistive devices, the first transistor
being operative to set the output node to a logic high level when the
first supply voltage exceeds the predetermined voltage;
a second transistor coupled to system ground and the output node, the
second transistor receiving a second biasing voltage that varies as the
first supply voltage ramps towards its final value from a second node
defined between a second pair of resistive devices, wherein a difference
between the second biasing voltage and system ground is equal to a
difference between the first biasing voltage and the first supply voltage,
the second transistor being operative to set the output node to a logic
low level when the first supply voltage is less than the predetermined
voltage; and
a third transistor coupled between the second transistor and system ground,
the third transistor receiving a third biasing voltage from a third node
defined between a third pair of resistive devices.
4. The voltage detector circuit of claim 3 wherein the plurality of
resistive devices comprises:
a first resistive device coupled between the first supply voltage and the
first node;
a second resistive device coupled between the first node and the second
node;
a third resistive device coupled between the second node and the third
node; and
a fourth resistive device coupled between the third node and system ground.
5. The voltage detector circuit of claim 4, wherein a resistance value for
each of the plurality of resistive devices is equal.
6. The voltage detector circuit of claim 5, wherein each of the resistive
devices is a transistor.
7. The voltage detector circuit of claim 6, wherein a fourth transistor is
coupled in parallel with the first resistive device between the first
supply voltage and the first node, the fourth transistor for setting the
first node to the first supply voltage when the first supply voltage is
approximately equal to a second supply voltage.
8. The voltage detector circuit of claim 3, further comprising:
a fourth transistor coupled to a second supply voltage, the output node,
and a fourth node, the fourth transistor setting the fourth node to the
second supply voltage in response to the output node being at a logic low
level; and
a fifth transistor coupled to system ground, the output node, and the
fourth node, the fifth transistor setting the fourth node to system ground
when the output node is at a logic high level; and
a sixth transistor coupled to the first supply voltage, the second supply
voltage, and the fourth node, the sixth transistor for setting the fourth
node to the second supply voltage when the second supply voltage exceeds
the first supply voltage by at least a threshold voltage of the sixth
transistor.
9. The voltage detector circuit of claim 3, wherein the first transistor is
a p-channel field effect transistor and the third transistor is an
n-channel field effect transistor, the predetermined voltage being set by
threshold voltages and beta values of the first and third transistors.
10. A nonvolatile memory device comprising:
an array of memory cells;
a first input for receiving a first supply voltage for programming the
array of memory cells, wherein the first supply voltage is selectively
coupled to the array of memory cells;
a second input for receiving a second supply voltage for operating
circuitry of the nonvolatile memory device, wherein the second supply
voltage is selectively coupled to the array of memory cells;
a voltage detector circuit coupled to the first and second inputs for
determining when the first supply voltage exceeds a predetermined voltage
as the first supply voltage ramps towards its final value, the voltage
detector circuit comprising:
a plurality of resistive devices coupled in series between the first supply
voltage and system ground;
a first transistor coupled to the first supply voltage and an output node,
the first transistor receiving a first biasing voltage that varies as the
first supply voltage ramps towards its final value from a first node
defined between a first pair of resistive devices, the first transistor
being operative to set the output node to a logic high level when the
first supply voltage exceeds the predetermined voltage;
a second transistor coupled to system ground and the output node, the
second transistor receiving a second biasing voltage that varies as the
first supply voltage ramps towards its final value from a second node
defined between a second pair of resistive devices, wherein a difference
between the second biasing voltage and system ground is equal to a
difference between the first biasing voltage and the first supply voltage,
the second transistor being operative to set the output node to a logic
low level when the first supply voltage is less than the predetermined
voltage; and
a third transistor coupled between the second transistor and system ground,
the third transistor receiving a third biasing voltage from a third node
defined between a third pair of resistive devices.
11. The nonvolatile memory device of claim 10 wherein the plurality of
resistive devices comprises:
a first resistive device coupled between the first supply voltage and the
first node;
a second resistive device coupled between the first node and the second
node;
a third resistive device coupled between the second node and the third
node; and
a fourth resistive device coupled between the third node and system ground.
12. The nonvolatile memory device of claim 11, wherein a resistance value
for each of the plurality of resistive devices is equal.
13. The nonvolatile memory device of claim 12, wherein each of the
resistive devices is a transistor.
14. The nonvolatile memory device of claim 13, wherein a fourth transistor
is coupled in parallel with the first resistive device between the first
supply voltage and the first node, the fourth transistor for setting the
first node to the first supply voltage when the first supply voltage is
approximately equal to a second supply voltage.
15. The nonvolatile memory device of claim 10, the voltage detector circuit
further comprising:
a fourth transistor coupled to a second supply voltage, the output node,
and a fourth node, the fourth transistor setting the fourth node to the
second supply voltage in response to the output node being at a logic low
level; and
a fifth transistor coupled to system ground, the output node, and the
fourth node, the fifth transistor setting the fourth node to system ground
when the output node is at a logic high level; and
a sixth transistor coupled to the first supply voltage, the second supply
voltage, and the fourth node, the sixth transistor for setting the fourth
node to the second supply voltage when the second supply voltage exceeds
the first supply voltage by at least a threshold voltage of the sixth
transistor.
16. The nonvolatile memory device of claim 10, wherein the first transistor
is a p-channel field effect transistor and the third transistor is an
n-channel field effect transistor, the predetermined voltage being set by
threshold voltages and beta values of the first and third transistors.
17. A voltage detector circuit for detecting whether a supply voltage
exceeds a predetermined voltage comprising:
a plurality of resistive devices coupled to define a first node, a second
node, and a third node between the supply voltage and system ground;
a first transistor having a gate coupled to the first node, a source
coupled to the supply voltage, and a drain coupled to a first output node;
a second transistor having a gate coupled to the second node, a source
coupled to the first output node, and a drain;
a third transistor having a gate coupled to the third node, a source
coupled to system ground, and a drain coupled the drain of the second
transistor;
a fourth transistor having a gate coupled to the first output node, a
source coupled to a second supply voltage, and a drain coupled to a second
output node;
a fifth transistor having a gate coupled to the first output node, a
source, and a drain coupled to the second output node;
a sixth transistor having a gate coupled to the third node, a drain coupled
to the source of the fifth transistor, and a source;
a seventh transistor having a gate coupled to the supply voltage, a source
coupled to system ground, and a drain coupled to the source of the sixth
transistor; and
an eighth transistor having a gate coupled to the supply voltage, a source
coupled to the second supply voltage, and a drain coupled to the second
output node. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
FIELD OF THE INVENTION
The present invention relates generally to power management of integrated
circuits and more particularly to the power management of nonvolatile
memory devices.
BACKGROUND
The use of computer systems has grown so pervasive that the power consumed
by computer systems has become a concern for computer system designers and
consumers. To reduce the cost of providing power to operate computer
systems and the corresponding consumption of energy resources, the goal of
designing a "green PC" that consumes less power has been pursued by
several manufacturers. Manufacturers of mobile or "portable" computer
systems that operate using rechargeable batteries as power supplies have
also attempted to reduce power consumption so that the mobile computer
system may be used for extended periods of time without recharging the
batteries.
To reduce power consumption and to extend battery life, much of the
integrated circuitry used as components of computer systems is being
designed to operate at low voltage levels. For example, the circuitry and
components used in portable computers are being designed to operate at
exclusively at voltage levels such as five volts and 3.3 volts. This
reduces power consumption and allows more components to be placed closer
to one another in the circuitry.
Unfortunately, the movement towards reducing the power consumption of
computer systems may conflict with the desire to provide after-market
upgrades and add-on devices for portable computer systems. One type of
device that may be used to increase the versatility of a portable computer
system is the flash electrically erasable programmable read only memory
("flash EEPROM"). Flash EEPROMs are nonvolatile memory devices that can be
programmed and erased by the user, and flash EEPROMS may be used, for
example, as BIOS ROMs or as part of a plug-in memory card. Flash EEPROMs
typically require higher voltages for programming and erasing data than
can be provided directly by the reduced voltage power supplies of green
PCs and portable computers.
One solution for allowing flash EEPROMs to be used in reduced voltage
computer system designs is to provide charge pump circuits external to the
flash EEPROMs for boosting the supply voltage levels of the computer
system to the higher voltage levels required by the flash EEPROM. A
difficulty with this solution is that the use of separate charge pump
circuits requires printed circuit board space that may be at a premium in
a portable computer system.
An alternative solution is to design flash EEPROMs that include charge pump
circuits for internally generating the higher voltage levels required by
the flash EEPROM. One difficulty with this solution is that charge pumps
internal to the flash EEPROM require semiconductor die space, which may
require an increase in the semiconductor die size for the flash EEPROM.
Another difficulty is that internal charge pump circuits may not be able
to provide sufficient current to program and erase the memory cell array
as quickly as external charge pumps, and operation of the flash EEPROM may
be slowed.
SUMMARY AND OBJECTS OF THE INVENTION
Therefore, one object of the present invention to provide circuitry for
detecting the external supply voltages supplied to an integrated circuit.
A further object of the present invention is to provide circuitry for
detecting the external supply voltages that operates at a reduced power
consumption level.
These and other objects of the invention are provided by a voltage detector
circuit for detecting whether a supply voltage exceeds a predetermined
voltage. The voltage detector circuit includes a first transistor having a
first terminal coupled to the operating supply voltage, a second terminal
coupled to a first node, and a control electrode coupled to receive a
first voltage that depends on the supply voltage. The voltage detector
circuit also includes a second transistor having a first terminal coupled
to the first node, a second terminal coupled to system ground, and a
control electrode coupled to receive a second voltage that depends on the
supply voltage. The first transistor is operative to set the first node to
a logic high level when the supply voltage exceeds the predetermined
voltage. The second transistor is operative to set the first node to a
logic low level when the supply voltage is less than the predetermined
voltage. The first and second voltages are selected such that a first
difference in potential between the control electrode of the first
transistor and the first terminal of the first transistor is equal to a
second difference in potential between the control electrod of the second
transistor and the second terminal of the second transistor. Further, the
first and second transistors are sized such that equal currents flow
through the first transistor and the second transistor when the supply
voltage is equal to the predetermined voltage.
Other objects, features, and advantages of the present invention will be
apparent from the accompanying drawings and from the detailed description
which follows below.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example and not limitation
in the figures of the accompanying drawings, in which like references
indicate similar elements, and in which:
FIG. 1 shows a computer system that includes one or more components having
novel circuitry.
FIG. 2 shows a flash EEPROM that includes novel circuitry.
FIG. 3A and 3B show smart voltage circuitry of the flash EEPROM according
to different embodiments.
FIG. 4 shows a latch mode VCC detector.
FIG. 5 shows the behavior of the latch mode VCC detector.
FIG. 6 shows a continuous mode VCC detector.
FIG. 7 shows the behavior of the continuous mode VCC detector.
FIG. 8 shows a VCC detector capable of operating in both the latch mode and
the continuous mode.
FIG. 9 shows a drain bias control circuit for the VCC detector in more
detail.
FIG. 10 shows a clocked voltage detector circuit.
FIG. 11 shows one 5/12 v VPP level detector circuit.
FIG. 12 shows a second 5/12 v VPP level detector circuit.
FIGS. 13A and 13B show internal power supplies according to different
embodiments.
FIG. 14 shows an internal power supply as including regulation circuitry
and a charge pump.
FIG. 15 shows a charge pump in more detail.
FIG. 16 shows clock signals that may be provided to the charge pump of FIG.
15.
FIG. 17 shows the internal power supplies wherein three charge pump
circuits share the same charge pump.
FIG. 18 shows the internal power supplies wherein four charge pump circuits
share the same charge pump.
FIG. 19 shows the regulation circuitry of a stand-by charge pump.
FIG. 20 shows the output of the pulse generator and the corresponding
current consumption of a charge pump enabled in response to a pulse
generated by the pulse generator.
FIG. 21 shows the pulse generator circuit in more detail.
FIG. 22 shows an oscillator of the pulse generator circuit that uses
subthreshold biasing.
FIG. 23A and 23B are flow charts illustrating a method of operation for the
flash EEPROM 20 that includes the smart voltage circuitry shown in FIG.
3A.
FIG. 24A and 24B are flow charts illustrating a method of operation for the
flash EEPROM 20 that includes the smart voltage circuitry shown in FIG.
3B.
DETAILED DESCRIPTION
FIG. 1 shows a general purpose computer system 10 that includes a power
supply 11, a central processing unit ("CPU") 12, a main memory 13, a read
only memory 14, a mass storage device 15, a frame buffer 16, and an input
device 17, all of which are coupled to a bus 19. The bus 19 includes a
data bus and acts as a primary interconnect for the components of the
computer system 10 so that data may be transferred among the various
components. The computer system 10 also includes a display device 18 that
is coupled to the frame buffer 16 for receiving image data for display.
The read only memory 14 may be a flash EEPROM, and the mass storage device
may be a "solid state disk drive" that includes a plurality of flash
EEPROMs for emulating the operation of a magnetic hard disk drive.
The computer system 10 may be a portable computer, a workstation, a
minicomputer, a programmable digital assistant ("PDA"), a mainframe, or
any other type of computer, and the power requirements of the computer
system 10 are defined accordingly. For example, if the computer system 10
is a workstation, the system operating voltage VCC may be 5.0 volts,
wherein if the computer system 10 is a portable computer operating from a
rechargeable battery, the system operating voltage VCC may be 3.3 volts.
It may also be possible that the computer system 10 is a portable computer
system that provides different operating voltage levels depending on
whether power is supplied by the rechargeable battery or by an AC adapter.
The power supply 11 therefore includes a VCC supply output for supplying
the operating voltage VCC of the computer system 10 to the components of
the computer system via power conductors of the bus 19. Wherein the
computer system 10 is a portable computer, the power supply 11 may be a
rechargeable battery. The power supply 11 may also include a VPP supply
output for supplying a twelve volt programming voltage VPP to the read
only memory 14 or the mass storage device 15. If the power supply 11 does
not include a separate VPP supply output, the VPP input of flash EEPROMs
included in the computer system 10 may be coupled to receive the VCC
operating voltage.
The flash EEPROMs of the computer system 10 includes circuitry that allows
the flash EEPROMs to operate when VCC is equal to 3.3 volts or 5.0 volts
and VPP is equal to 5.0 volts or 12.0 volts. Each flash EEPROM therefore
includes circuitry for detecting the supply voltages supplied by the power
supply 11, wherein each flash EEPROM configures itself for operation in
response to the detected voltages. Not all the flash EEPROMs of the
computer system 10 need to include such circuitry.
FIG. 2 shows a flash EEPROM that includes circuitry for detecting system
supply voltages. The flash EEPROM 20 is an integrated circuit that may be
formed on a single semiconductor substrate and that typically includes a
memory cell array 21 comprising a plurality of flash memory cells 22, each
of which is a floating gate transistor device having a select gate, a
floating gate, a drain, and a source. The flash memory cells 22 of the
memory cell array 21 are arranged in a matrix of rows and columns, wherein
a common "wordline" is coupled to the select gate of each flash memory
cell of a row and a common "bitline" is coupled to the drain of each flash
memory cell of a column.
A flash memory cell 22 is programmed by placing excess charge on the
floating gate, which increases the threshold voltage V.sub.t of the flash
memory cell 22. The flash memory cell 22 may be placed in two or more
analog states that can be represented by one or more bits. Programming may
be accomplished by applying 12.0 volts to the gate, 6.0 volts to the
drain, and grounding the source such that electrons are placed on the
floating gate by hot electron injection. The flash memory cell 22 is
erased by removing the excess charge from the floating gate, and erasure
may be accomplished by applying 12.0 volts to the source, grounding the
gate, and allowing the drain to float such that electrons are removed from
the floating gate via electron tunneling. It is possible to erase several
flash memory cells simultaneously, and the operation of erasing several
flash memory cells simultaneously is known as a "block erase."
To determine whether the flash memory cell 22 is in the erased state or in
a programmed state, a constant voltage is applied to the select gate of
the flash memory cell to sense the amount of drain-source current IDS for
the flash memory cell 22. Such a read operation may be accomplished by
applying 5.0 volts to the gate, grounding the source, and applying 1.0
volt to the drain. To perform read, program, and erase operations on a
selected set of flash memory cells, the flash EEPROM 20 includes wordline
switches and decoders 23, source switches and decoders 24, and bitline
switches and decoders 25, all of which are controlled by the control
engine 26 to select the desired flash memory cells and to apply the
appropriate voltages to the selected flash memory cells. The smart voltage
circuitry 27 is coupled to the VCC and VPP input pins of the flash EEPROM
20 and is used to supply the required voltages to the wordline switches
and decoders 23, the source switches and decoders 24, and the bitline
switches and decoders 25 in response to the detected supply levels and the
mode of operation for the flash EEPROM 20.
The smart voltage circuitry 27 includes internal power supplies (shown in
FIGS. 3A and 3B) that may be selected to supply the necessary voltages for
operating the flash EEPROM if the external supply levels are determined to
be less than the required values for programming, erasing, or reading the
memory cell array 21. For example, an internal power supply may be enabled
to supply a 5.0 volt output if the external operating supply voltage VCC
is detected to be at 3.3 volts, but if the external operating supply
voltage VCC is detected to be at 5.0 volts, the internal power supply is
disabled and the external operating supply voltage VCC is delivered to the
memory cell array 21. Similarly, an internal power supply may be enabled
during programming and erase operations to supply a 12.0 volt output if
the external programming supply voltage VPP is detected to be at 5.0
volts, but if the external programming supply voltage VPP is detected to
be at 12.0 volts the internal power supply is disabled and the external
programming supply voltage VPP is delivered to the memory cell array.
The smart voltage circuitry 27 thus allows the same flash EEPROM 20 to be
used in computer systems that operate at either high or low voltages.
Wherein printed circuit board space is at a premium, the system designer
can use the internal power supplies of the flash EEPROM 20 to provide the
voltages required for programming and erasing, and an external charge pump
circuit is not required. Alternatively, wherein memory performance is at a
premium, the system designer can use a power supply or external charge
pump circuit to provide the programming and erase voltages.
The smart voltage circuitry 27 may find application for many different
types of integrated circuits and more particularly memory devices. For
example, the smart voltage circuitry described herein may be used in
dynamic random access memories (DRAMs), eraseable programmable read only
memories (EPROMs), and electrically eraseable programmable read only
memories (E.sup.2 PROMs). The smart voltage circuitry 27 may also be used
to detect and select the voltages for the different modules of a
multi-chip module. The internal power supplies may be provided as one
module, and the voltage detection and selection circuitry may be provided
as a second module. The voltage detection and selection circuitry can be
used to detect the external power supply voltages and selectively enable
the appropriate outputs of the internal power supplies, if necessary.
The flash EEPROM 20 has three modes of operation, including an active mode,
a stand-by mode, and a deep power down mode. The stand-by and deep power
down modes are both reduced power modes. To define the mode of operation
of the flash EEPROM 20, the control engine 26 receives the control signals
chip enable CE, output enable OE, write enable WE, and power down PWD.
Chip enable signal CE is the power control and is used for device
selection of the flash EEPROM 20. The output enable signal OE is the
output control for flash EEPROM 20 and is used to gate data from the
output pins from flash EEPROM 20, dependent on device selection. Both of
the control signals CE and OE must be at a logic low level to obtain data
at the outputs of flash EEPROM 20. The write enable signal WE0 allows
writes to control engine 26 while the chip enable signal CE is active low.
Addresses and data are latched on the rising edge of the write enable
signal WE.
The flash EEPROM 20 is in the active mode of operation when both control
signals CE and OE are at a logic low level and PWD is at a logic high
level. When both the chip enable signal CE and the power down signal PWD
are logic high, the flash EEPROM 20 enters the stand-by mode. The power
down signal PWD causes the flash EEPROM 20 to enter the deep power down
mode when the power down signal PWD is at a logic low level.
For the active mode of operation, the flash EEPROM 20 may draw sufficient
power from the power supply 11 to perform read, program, and erase
operations. For the stand-by mode of operation, the flash EEPROM 20 is
prevented from performing any operations on the memory cell array 21, and
the amount of power that the flash EEPROM 20 may consume is reduced. For
the deep power down mode of operation, all memory cell array operations
are disabled and the amount of power that the flash EEPROM 20 may consume
is less than that of the stand-by mode. For example, the flash EEPROM 20
may consume 100 microamperes of current while in the stand-by mode and
only two microamperes of current while in the deep power down mode. For
prior flash EEPROMs that do not include internal power supplies, the deep
power down mode results in the disabling of all the circuits of the flash
EEPROM.
When the flash EEPROM 20 transitions from either the stand-by mode or the
deep power down mode to the active mode, it is desirable for the flash
memory cell array 21 be ready to perform for read operations, which means
that the wordline switches 23 should be charged to 5.0 volts. If the
detected external supply voltage VCC is 5.0 volts, the wordline switches
may be maintained at 5.0 volts by the external supply voltage VCC during
the stand-by and deep power down modes through the use of a simple pull-up
device, which may be a transistor or a resistor. If the detected external
supply voltage is VCC 3.3 volts, an internal power supply may be used to
charge the wordline switches 23 to 5.0 volts.
If the external supply voltage VCC is equal to 3.3 volts and the internal
power supplies are only enabled to charge wordline switches 23 when the
flash EEPROM 20 operates in the active mode, the access time for the flash
EEPROM 20 is increased when the flash EEPROM transitions from the stand-by
or deep power down modes to the active mode to allow the wordline switches
23 to be charged to the appropriate voltage. The wordline switches 23 are
discharged due to leakage, and, given sufficient amount of time, the
wordlines switches 23 may be discharged to the value of the external
supply voltage VCC. Further, wherein the memory cell array 21 is quite
large, the capacitance of the wordline switches 23 is increased, which may
result in significant voltage and current transients internal to the flash
EEPROM 20 when the flash EEPROM 20 transitions between operating modes.
Such transients must be accounted for, which typically results in a
further increase in access time. Therefore, to decrease the amount of time
required to access the flash EEPROM 20 and to reduce internal transients,
it may be desirable for the appropriate internal power supply to remain in
operation during the stand-by and deep power down modes; however, the
design of the smart voltage circuitry may be constrained by the power
consumption requirements of the flash EEPROM and by the amount of
semiconductor die space that can be provided for the smart voltage
circuitry.
FIGS. 3A and 3B show the smart voltage circuitry 27 according to two
different embodiments. FIG. 3A shows an example of the smart voltage
circuitry 27a wherein the wordline switches 23 are maintained at 5.0 volts
by the internal power supplies while the flash EEPROM 20 is operating in
both the stand-by and deep power down modes. The smart voltage circuitry
27a of FIG. 3A results in a greatly reduced access time, but may require
more die space. FIG. 3B shows an example of the smart voltage circuitry
27b wherein the wordline switches 23 are maintained at 5.0 volts by the
internal power supplies during the stand-by mode, but are maintained at
the external supply voltage VCC during the deep power down mode. The smart
voltage circuitry 27b of FIG. 3B typically requires less die space than
the circuitry of FIG. 3A, but access time may be increased.
FIG. 3A shows smart voltage circuitry 27a that includes a VCC ramp detector
30, a 3.3 v/5 v VCC level detector 35, a low VCC detector 40, a current
source 45, a pulse generator 50, a 5 v/12 v VPP level detector 55, and
internal power supplies 60a. The operation of the internal power supplies
60a is determined by the mode of operation for flash EEPROM 20, the
external operating supply voltage VCC, and the external programming supply
voltage VPP as detected by the VCC ramp detector 30, the 3.3 v/5 v VCC
level detector 35, and the 5 v/12 v VPP level detector 55. The program and
erase operations are inhibited if a low external supply voltage VCC level
is detected by the low VCC level detector 40 while the flash EEPROM 20 is
in the active mode of operation. The current source 45 and the pulse
generator 50 are included to conditionally and periodically enable the
internal power supplies 60a for charging the wordline switches 23 to 5.0
volts while the flash EEPROM operates in either the stand-by or deep power
down operating modes. The wordline switches 23 are thus maintained at the
requisite voltage level, but the internal power supplies are only
periodically activated such that the power consumption of the flash EEPROM
20 may be maintained within the limits defined for the stand-by and deep
power down modes of operation. This circuitry is described in more detail
below.
The internal power supplies 60a include three output lines. The HH5PX
output line may be coupled to the wordline switches 23 for read
operations. The HHVPLL output line may be coupled to the bitline switches
25 for programming operations. The HHVP12 output line may be coupled to
the wordline switches 23 for programming operations and to the source
switches 24 for erase operations.
FIG. 3B shows smart voltage circuitry 27b that typically requires less
semiconductor die space than the circuitry shown in FIG. 3A. Smart voltage
circuitry 27b includes VCC ramp detector 30, 3.3 v/5 v VCC level detector
35, a low VCC detector 40, 5 v/12 v VPP level detector 55, and internal
power supplies 60b, which include a stand-by five-volt internal supply
(shown in FIG. 13B) that is used to charge the wordline switches 23 to 5.0
volts if the external supply voltage VCC is not 5.0 volts, and if the
flash EEPROM 20 is operating in the stand-by mode. The stand-by five-volt
internal supply is smaller than the five-volt internal supply used during
read operations such that power consumption may be maintained within the
limits of the stand-by operating mode. The wordline switches 23 are
charged to the external supply voltage VCC during deep power down mode,
regardless of whether or not external VCC is equal to 5.0 volts. As shown,
the same circuitry that is used as a VCC ramp detector 30 may be used as a
low VCC detector 40 to further reduce the amount of semiconductor die
space required for the smart voltage circuitry 27b.
The basic operation of the smart voltage circuitry 27a shown in FIG. 3A
will now be discussed. The VCC ramp detector 30 is provided to enable the
internal power supplies 60a and to initialize the 3.3 v/5 v VCC level
detector 35, the current source 45, and the pulse generator 50 when power
is first applied to the flash EEPROM 20. The precise operation of VCC ramp
detector 30 depends on the mode of operation for the flash EEPROM 20 when
power is first applied.
FIG. 23A shows a method of operation for the smart voltage circuitry 27a
shown in FIG. 3A when the flash EEPROM 20 is operating in the deep power
down or stand-by modes. At process block 2400, power is first supplied to
the flash EEPROM 20. At process block 2405, the VCC ramp detector 30
responds to power-up by enabling the internal power supplies 60a to charge
the wordline switches 23, by initializing the 3.3 v/5 v VCC level detector
35 to indicate a 3.3 volt external VCC, and by initializing the current
source 45 and the pulse generator 50.
The VCC ramp detector 30 outputs a control signal HDRMVCD to the 3.3 V/5 V
VCC level detector 35, the current source 45, the pulse generator 50, and
the internal power supplies 60a. When the operating supply voltage VCC is
less than a trip-point voltage V.sub.trip of the VCC ramp detector 30, the
signal HDRMVCD tracks the external supply voltage VCC as it ramps from
zero volts to its final value, and the appropriate circuitry is enabled or
disabled.
At process block 2410, the supply voltage exceeds the trip-point voltage
V.sub.trip, which may be 2.7 volts or 2.9 volts, and the control signal
HDRMVCD goes low. The VCC ramp detector 30 is switched off to reduce the
power consumption of smart voltage circuitry 27a. In response to the
control signal HDRMVCD going low, the 3.3 v/5 v VCC level detector 35 and
the internal power supplies 60a are disabled, and the pulse generator 50
is enabled. The pulse generator 50 periodically supplies a logic high
control pulse to the internal power supplies 60a and the 3.3 v/5 v VCC
level detector 35 via the HDOUT signal line. The current source 45 is
included to provide biasing currents PBIAS and NBIAS to the oscillators
(as shown in FIG. 22) of the pulse generator 50.
At process block 2415, a control pulse is received by the internal power
supplies 60a and the 3.3 v/5 v VCC level detector 35. The internal power
supplies 60a are enabled for the duration of each control pulse so that
the voltage of the wordline switches 23 may be maintained at 5.0 volts.
The 3.3 v/5 v VCC level detector 35, which is coupled to receive the
external supply voltage VCC, is also enabled for the duration of the
control pulse. According to one embodiment, a six microsecond pulse is
applied once every three milliseconds.
The 3.3 v/5 v VCC level detector 35 outputs a control signal ID5V to
indicate the detected value of the external supply voltage VCC. As
described above, the control signal ID5V is initialized during power-up of
the flash EEPROM 20 to a logic low level for indicating that external VCC
is not five volts. If the external supply voltage VCC is greater than a
trip-point voltage V.sub.3/5 for the 3.3 v/5 v VCC level detector 35 while
the 3.3 v/5 v VCC level detector 35 enabled, the ID5V signal is set to a
logic high level.
At process block 2420, if the external supply voltage VCC is detected as
not being equal to five volts, the internal power supplies 60a are allowed
to charge the wordline switches 23 at process block 2425. If the external
supply voltage VCC is equal to five volts, the 3.3 v/5 v VCC level
detector 35 sets control signal ID5V logic high, which disables the
internal power supplies 60a and enables external VCC to charge the
wordline switches 23 at process block 2430. The high value of the control
signal ID5V is latched. The current control pulse ends at process block
2435. Process blocks 2415-2435 are repeated for each control pulse
received from the pulse generator 50. If external VCC was detected as
being at five volts during a previous control pulse, and external VCC is
detected as being 3.3 volts during the current control pulse, the internal
charge pumps are enabled at process block 2425. The process shown in FIG.
23A may be repeated each time the flash EEPROM 20 is powered up in the
stand-by or deep power down modes.
FIG. 23B shows a method of operation for the smart voltage circuitry 27a
shown in FIG. 3A when the flash EEPROM 20 is operating in the active mode.
At process block 2450, power is initially supplied to the flash EEPROM 20.
At process block 2455, | | |
