A method and apparatus for processing video data and graphics data with minimal visual differences is accomplished by retrieving the graphics data and the video data at a first clock rate. Having retrieved the video data, it is sampled at a second clock rate to produce sampled video data. The second clock rate is greater than the first such that the video data is sampled at a higher rate than the pixel rate of the computing device. The sampled video data is then filtered by a low-pass filter to produce filtered video data. The filtered video data is then mixed, based on a control signal, with the retrieved graphics data to produce a mixed signal that is subsequently displayed.

A method and apparatus for performing color space conversion using blend circuitry in a graphics/video adapter is provided. Blend circuitry which is capable of blending two color values and fog circuitry which is capable of adjusting color values based on a fog factor are used. A first stage of converting a color value from YC.sub.r C.sub.b (YUV) color space to RGB color space is performed using the fog circuitry, and a second stage of converting the color value from the YC.sub.r C.sub.b (YUV) color space to RGB color space is performed using the blend circuitry, resulting in the generation of a converted color value .

In accordance with a technique for stabilizing the picture output in a video display apparatus, the resolution of the video mode supplied from a PC, for example, is converted into a resolution of a pre-set video mode, thereby making it possible to output stabilized picture. The method for stabilizing a picture output in a video display apparatus includes the following steps. A power-on is recognized, and then a first power control signal is outputted. A counting is carried out for N seconds by an internal counter after outputting the first power control signal, and then a second power control signal is outputted. Then, counting is carried out for N/4 seconds by an internal counter after the outputting of the second power control signal, and control data and a clock signal are then outputted. In this manner, the format converter module and the circuit blocks are sequentially drive. Thus, the microcomputer drives the format converter module, and the format converter module converts externally input RGB signals to a resolution of a pre-set video mode so as to display stable full pictures.

A method for an image reducing processing circuit includes the memory architecture of two FIFO units. The method includes the following steps of: providing an input processing unit receiving original image data and delivering the image data; providing a horizontal direction image processing unit receiving the image data from the input processing unit; providing a first step FIFO unit receiving the image data from the horizontal direction image processing unit to read and write the image data on the same access frequency; providing a vertical direction image processing unit receiving the image data from the first step FIFO unit; providing a second step FIFO unit receiving the image data from the vertical direction image processing unit and implementing the readout/writing of the image data on two access frequency, and providing an output processing unit receiving the image data from the second step FIFO unit and outputting reduced image.

A system and method of rendering overlapping layers in a computer display, such as a windowing system, employs front-to-back assembly of the displayed image. An arbitrary number of overlapping elements, such as windows, can be presented, without requiring temporary storage space or additional off-screen buffers. The front-to-back assembly technique minimizes the number of memory transfers performed in connection with rendering an image, and avoids unnecessary reading and processing of pixels that will not contribute to the final image. Special effects such as semi-transparency, shadows, and irregular shapes can be accommodated and processed in an efficient manner.