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Claims  |
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What is claimed is:
1. Chip carrier package, comprising:
an upper substrate having an upper surface, a lower surface, and an outline
shape;
a lower substrate having an upper surface, a lower surface, and an outline
shape;
an opening extending through the lower substrate;
conductive lines interposed between the lower surface of the upper
substrate and the upper surface of the lower substrate, the conductive
lines contacting the lower surface of the upper substrate and the upper
surface of the lower substrate, and extending between the upper and lower
substrates towards the opening in the lower substrate;
a semiconductor die having a front face containing circuit elements and a
back face, and mounted in the opening in the lower substrate;
wiring traces disposed on the lower surface of the lower substrate, and
extending across the lower substrate to adjacent the opening in the lower
substrate;
means for electrically connecting the circuit elements to the inner ends of
the wiring traces;
means for electrically connecting outer portions of the wiring traces to
the conductive lines;
plastic molding compound disposed over the front face of the die and
extending partially over the lower surface of the lower substrate;
ball bumps disposed on the upper surface of the upper substrate; and
means for connecting the conductive lines to the ball bumps.
2. Chip carrier package, according to claim l, wherein:
the means for electrically connecting the circuit elements to inner ends of
the wiring traces is bond wires.
3. Chip carrier package, according to claim 1, wherein:
the means for electrically connecting the wiring traces to the conductive
lines is at least one row of plated through holes extending through the
lower substrate.
4. Chip carrier package, according to claim 3, wherein:
at least two rows of plated through holes are disposed through the lower
substrate, and each row of through holes is offset from the remaining rows
of plated through holes.
5. Chip carrier package, according to claim 3, further comprising:
additional through holes extending through the upper and lower substrates;
wherein:
the additional through holes are plated; and
the additional through holes are electrically isolated from the conductive
lines.
6. Chip carrier package, according to claim 1, wherein:
the upper substrate is provided with a central opening;
a heatsink element is disposed within the central opening in the upper
substrate; and
the back face of the semiconductor die is adhered to the heatsink.
7. Chip carrier package, according to claim 1, wherein:
the back face of the semiconductor die is adhered to the lower surface of
the upper substrate.
8. Chip carrier package, according to claim 1, wherein:
a die-receiving area formed by inner ends of the wiring traces has a
certain non-square geometric configuration similar to a geometric
configuration of a certain non-square die mounted in the die-receiving
area.
9. Chip carrier package, according to claim 1, wherein:
a geometric configuration formed by the inner ends of the wiring traces
defines a triangular shaped die-receiving area.
10. Chip carrier package, according to claim 1, wherein:
a geometric configuration formed by the inner ends of the wiring traces
defines a "greatly elongated rectangular" shaped die-receiving area.
11. Chip carrier package, according to claim 1, wherein:
a geometric configuration formed by the inner ends of the wiring traces
defines a parallelogram shaped die-receiving area.
12. Chip carrier package, according to claim 1, wherein:
a geometric configuration formed by the inner ends of the wiring traces
define a trapezoidal shaped die-receiving area.
13. Chip carrier package, according to claim 1, further comprising:
a "certain non-square" body shape defined by the outlines of the upper and
lower substrates.
14. Chip carrier package, according to claim 13, wherein:
the body shape is triangular.
15. Chip carrier package, according to claim 13, wherein:
the body shape is a "greatly elongated rectangular" shape.
16. Chip carrier package, according to claim 13, wherein:
the body shape is a parallelogram shape.
17. Chip carrier package, according to claim 13, wherein:
the body shape is a trapezoidal shape.
18. Chip carrier comprising:
an upper substrate having an upper surface, a lower surface, and an
outline;
a lower substrate having an upper surface, a lower surface, and an outline;
an opening extending through the lower substrate for receiving a
semiconductor die;
conductive lines interposed between the lower surface of the upper
substrate and the upper surface of the lower substrate, the conductive
lines contacting the lower surface of the upper substrate and the upper
surface of the lower substrate, and extending between the upper and lower
substrates towards the opening in the lower substrate;
wiring traces disposed on the lower surface of the lower substrate, and
extending across the lower substrate to adjacent the opening in the lower
substrate, said wiring traces having inner ends adjacent the opening in
the lower substrate;
means for electrically connecting outer portions of the wiring traces to
the conductive lines;
ball bumps disposed on the upper surface of the upper substrate; and
means for connecting the conductive lines to the ball bumps;
wherein:
a completed package is formed by mounting a die in the opening, connecting
the die to the inner ends of the wiring traces and disposing plastic
molding compound over the die and partially over the lower surface of the
lower substrate.
19. Chip carrier, according to claim 18, wherein:
the means for electrically connecting the wiring traces to the conductive
lines is at least one row of plated through holes extending through the
lower substrate.
20. Chip carrier, according to claim 19, wherein:
at least two rows of plated through holes are disposed through the lower
substrate, and each row of through holes is offset from the remaining rows
of plated through holes.
21. Chip carrier, according to claim 19, further comprising:
additional through holes extending through the upper and lower substrates;
wherein:
the additional through holes are plated; and
the additional through holes are electrically isolated from the conductive
lines.
22. Chip carrier, according to claim 18, wherein:
a geometric configuration formed by the inner ends of the wiring traces
defines a triangular shaped die-receiving area.
23. Chip carrier, according to claim 18, wherein:
a geometric configuration formed by the inner ends of the wiring traces
defines a "greatly elongated rectangular" shaped die-receiving area.
24. Chip carrier, according to claim 18, wherein:
a geometric configuration formed by the inner ends of the wiring traces
defines a parallelogram shaped die-receiving area.
25. Chip carrier, according to claim 18, wherein:
a geometric configuration formed by the inner ends of the wiring traces
define a trapezoidal shaped die-receiving area.
26. Chip carrier, according to claim 18, further comprising:
a "certain non-square" body shape defined by the peripheries of the upper
and lower substrates.
27. Chip carrier, according to claim 26, wherein:
the body shape is triangular.
28. Chip carrier, according to claim 26, wherein:
the body shape is a "greatly elongated rectangular" shape.
29. Chip carrier, according to claim 26, wherein:
the body shape is a parallelogram shape.
30. Chip carrier, according to claim 26, wherein:
the body shape is a trapezoidal shape. |
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Claims |
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Description |
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TECHNICAL FIELD OF THE INVENTION
The invention relates to the packaging of integrated circuit (IC)
semiconductor devices (chips), especially to high pin count packages
formed by injection or transfer molding.
BACKGROUND OF THE INVENTION
Packages provide the interconnect from a chip to a printed circuit board
(PCB). The package also provides protection for the chip from the
environment. The overall objective of the package design is to provide
these features at the lowest possible manufacturing cost.
A common process employed in semiconductor packaging is wire bonding,
wherein a fine wire is connected between semiconductor die pads and inner
ends of package lead fingers.
In one packaging scheme, a semiconductor die is mounted within an opening
in a package having external leads (or pins). Bond pads on the die are
wired to terminals within the package, and a lid is mounted over the
opening containing the die. This type of package is usually formed of
ceramic, and is relatively expensive to manufacture.
Another technique for packaging integrated circuit devices is mounting the
die to a die attach pad on a lead frame, connecting the die to various
inner lead fingers of the lead frame, and encapsulating the die, either
with epoxy or with a plastic molding compound. Plastic packages are
preferred by most commercial users for their low cost and low weight.
Plastic packaging is discussed in the main, hereinafter.
As chips become more complex, their packages require more pins (or external
leads), and hence become larger in size. Transfer molding large plastic
packages involves the transfer of large amounts of melted plastic, and the
injection of the plastic can cause bond wires connecting the chip to the
leadframe to move and short against each other (wire sweep). Also, because
of the set cure characteristics of plastic molding compound, a large
molded body has a tendency to warp, causing difficulties when packages are
mounted to a PCB.
Molding the entire package body ("fully molded") usually requires that the
leadframe has a "dambar", namely a continuous ring of metal surrounding
the body that prevents the plastic from flowing out of the mold cavity
between the external leads of the leadframe. The dambar then has to be
removed to isolate individual leads before the package is usable. With
high pin count packages, the leads are often delicate and spaced closely
(fine pitch), resulting in the need for very fine precision tooling for
the trimming operation. This type of tooling is also very expensive, which
adds to the overall cost of packaging.
Molding of the plastic around the leadframe also causes some leakage of the
plastic onto the leadframe (flashing). The flash then has to be removed in
a separate de-flashing (dejunking) step.
Attention is directed to commonly-owned U.S. Pat. No. 5,051,813, entitled
PLASTIC-PACKAGED SEMICONDUCTOR DEVICE HAVING LEAD SUPPORT AND ALIGNMENT
STRUCTURE, which discloses plastic packaging with and without dambars,
dejunking, etc.
In the main, hereinafter, molding where the mold gate is disposed at the
parting plane of the two mold halves is discussed, as most pertinent to
the present invention.
The following U.S. Patents are cited of general interest in the field of
packaging (annotations in parentheses): U.S. Pat. No. 3,405,441 (hermetic
sealing process using glass and metal lid on a ceramic substrate); U.S.
Pat. No. 3,909,838 (package formed by sealing two halves or pre-molded
body around a molded pill package bonded to a leadframe); U.S. Pat. No.
4,143,456 (glob top sealing devices mounted on a substrate); U.S. Pat. No.
4,264,917 (silicon substrate with glob top encapsulation); U.S. Pat. No.
4,300,153 (TAB device with a substrate bonded to the bottom of the die;
glob top encapsulation); U.S. Pat. No. 4,330,790 (tape-mounted device
encapsulated using a metal carrier and epoxy); U.S. Pat. No. 4,363,076
(flat TAB assembly); U.S. Pat. No. 4,507,675 (molded heatsink package);
U.S. Pat. No. 4,594,770 (bonding a metal cap and a plastic cap around a
leadframe); U.S. Pat. No. 4,857,483 (mold gate is not located at the
parting plane of the mold halves); U.S. Pat. No. 4,872,825 (encapsulation
method using a lamination process instead of injection or transfer
molding); U.S. Pat. No. 4,874,722 (pre-molded flatpack encapsulated with
silicone gel; dambar required; not encapsulated by molding); U.S. Pat. No.
4,890,152 (molded pin grid array package; not a surface mount flatpack
construction); U.S. Pat. No. 4,913,930 (coating and encapsulating a device
in a reel-to-reel format); U.S. Pat. No. 4,955,132 (flip chip mounting to
a substrate); U.S. Pat. No. 4,961,105(die back metallization); U.S. Pat.
No. 4,974,057 (die coated with resin and then molded); U.S. Pat. No.
4,975,765 (high density flatpack with edge connectors; not a molded
package); U.S. Pat. No. 4,982,265 (stackable TAB); U.S. Pat. No. 4,984,059
(leadframe tips overlap the top of the die surface); U.S. Pat. No.
4,996,587 (thin,stackable package); and U.S. Pat. No. 5,025,114 (leadframe
construction resulting in multilayer structure for plastic packages).
The functional demands placed on modern integrated circuits have resulted
in an ever-increasing demand for input/output (I/O) connections to the
die. Hundreds of I/O connections are not uncommon. Commonly-owned,
co-pending U.S. patent application Ser. No. 07/916,328 ("CNS-DIES"),
discussed below, discloses a method for increasing I/O connections for an
integrated circuit (die) of a given area. There remains a similar problem
with the number of connections required in the package mounting and
connecting to the die. Generally, there is a one-to-one correspondence
between the number of package connections and the number of bond pads on
the die.
Thus, there is a need for semiconductor packaging techniques that can
accommodate increased lead count, particularly suited to the dies
discussed in the aforementioned U.S. patent application No. Ser.
07/916,328.
Generally, semiconductor packages are used for (1) enclosing (protecting) a
semiconductor (IC) die in some kind of package body, and (2) providing
external connections for connecting the packaged die to external systems.
Packaging the integrated circuit, requires at a minimum, (1) a conductive
layer having a plurality of conductive lines, and (2) a "die-receiving
area." As is discussed in greater detail hereinbelow, the inner ends of
the conductive lines define the die-receiving area.
Once the die is mounted in (on) the die-receiving area, bond pads located
on the die will be connected, usually by wire bonding or tape automated
bonding (TAB) to inner end portions of the conductive lines.
Generally speaking, there are four distinct techniques of packaging a
semiconductor device, in any case said package having one or more layers
of conductive lines (leads, traces, or the like) exiting the package for
electrically connecting the packaged die to other components, whether by
mounting directly to a printed circuit (mother) board or by plugging the
packaged device into a socket which in turn is mounted to the mother
board. These are:
(1) plastic molding;
(2) ceramic packaging;
(3) PCB-substrate type packaging; and
(4) tape-based packaging.
Plastic molding typically involves a relatively rigid lead frame, wherein
the lead frame has a patterned layer of conductive leads (conductive
lines), the inner ends of which define the die-receiving area. A die is
mounted to a die paddle, within the die-receiving area, and is connected
to inner end portions of the conductive leads. The die and inner portion
of the lead frame are encapsulated by plastic molding compound. Outer end
portions of the conductive leads extend outside of the molded plastic
body.
Ceramic packaging typically involves one or more layers of conductive
traces (conductive lines) applied on interleaved ceramic layers. Again,
the die-receiving area is defined by the inner ends of the conductive
traces. Outer layers are typically ceramic. The die is mounted in a cavity
(either up or down), connected to inner ends of the traces, and the cavity
is closed by a lid. Outer ends of the traces are connected, within the
ceramic, to external pins or leads (for example) on the exterior of the
ceramic package body.
PCB-substrate type packaging involves a patterned layer of conductive
traces (conductive lines) on a printed circuit board (PCB) substrate, and
the inner ends of the conductive traces define the die-receiving area. The
die is mounted to the substrate, connected to the inner ends of the
traces, and may be encapsulated by epoxy, plastic molding compound, or in
any suitable manner. Outer ends of the traces are connected to external
pins or leads (for example), in a manner similar to ceramic packaging.
Tape-based packing involves a relatively non-rigid foil of conductive leads
(conductive lines), supported by a plastic layer, and the inner ends of
the conductive traces define the die-receiving area. A die is mounted to
the substrate formed by the layer of conductive leads and plastic, and is
connected to the inner ends of the conductive leads. Outer ends of the
leads are connected to (or form) external interconnects for the packaged
die.
In any of these, or other, packaging techniques, a die connected to
conductive lines and having some sort of support and/or package body is
referred to as a "semiconductor device assembly".
FIGS. 4A and 4B show two similar prior art layers 400, 400' of pattered
conductive lines, which are applicable to any of the aforementioned
package types. A "die-receiving area" 410, 410' is defined by the inner
ends 408,408' of a plurality of conductive lines 406, 406'. A die 402,
402' is mounted in the die-receiving area 410, 410', and bond pads 412,
412' on the die are connected to the inner ends of the conductive lines.
Two techniques for attaching a die to conductive lines are shown. In FIG.
4A, the die 402 is wire bonded to the conductive lines 406, as indicated
by bond wires 414 extending between the bond pads 412 and the conductive
lines 406. In FIG. 4B, the die 402' is connected to the conductive lines
406' by tape automated bonding (TAB) techniques (indicated by 414'). Both
of these techniques are well known. Other techniques (not shown) of
connecting a die to a pattern of conductive lines include flip-chip and
the like.
Notably, as shown in FIGS. 4A and 4B, the die is square. The conductive
lines extend (radiate) from the die-receiving area, outward from the die.
Hence, a sub-plurality of conductive lines are disposed on each of the
four sides of the die, their inner ends defining a square die-receiving
area. Also shown, by way of example, in FIGS. 4A and 4B are die attach
pads 404, 404', which are generally somewhat larger than the die and
somewhat smaller than the die-receiving area.
The conductive lines (406 and 406') include, but are not limited to, lead
frame leads, tape leads, and traces on a ceramic or PCB substrate.
Ultimately, a package body (not shown) may be formed about the die and
inner portions of the conductive lines, as discussed above.
As a practical matter, the number of conductive lines (406 and 406') is
determined by the number of bond pads (412 and 412') located on a given
die (402 and 402'). A problem with the prior art is insufficient number of
conductive lines (406 and 406').
Commonly owned, co-pending application Ser. No. 07/916,328 provides a
technique for increasing the number of I/O bond pads for a given die.
Hence, it is desirable to provide an increased number of conductive lines,
defining a die-receiving area and connecting to the die bond pads, hence
increasing the number of I/O connections.
Therefore, problems with mounting a die within a prior art square
die-receiving area is the limitation placed on the number of conductive
lines (406 and 406') defining the prior art square die-receiving area
(e.g., 410 and 410'). Prior art inner ends (408 and 408') of conductive
lines (406 and 406') make up a square die-receiving area, hence, providing
I/O connection limited to the periphery of the square. Moreover, the prior
art square die-receiving area does not accommodate the increased number of
I/O connection on a given die provided in commonly owned co-pending patent
application Ser. No. 07/916,328. Hence, what is needed is (at least) a
layer of conductive lines defining a die-receiving area that provides an
increased number of conductive lines, thus increasing the number of I/O
connections.
RELATION TO CNS-DIES
This invention is similar, in concept, to commonly owned, copending U.S.
patent application Ser. No. 07/916,328 ("CNS-DIES") in that there is a
recognition that certain geometric shapes exhibit a greater ratio of
periphery:area than squares. In the context of making I/O connections to
an integrated circuit die, this geometric relationship can be used to
great advantage.
As set forth in CNS-DIES, the demands placed on modern integrated circuits
are headed in two directions:
1. Fitting (fabricating) as many active elements as possible in the active
element area, to create more complex devices; and
2. Fitting as many bond pads as possible in an I/O area, typically around
the perimeter of the die, to accommodate an increased number of I/O
connections.
To satisfy these demands, CNS-DIES discloses what is generally termed
"certain non-square" dies that provide an increase in the number of bond
pads for a die of a given size (area). As disclosed in CNS-DIES, these
"certain non-square" dies include, inter alia:
(1) equilateral triangular shaped dies providing 14% more I/O than a square
die of the same size (area);
(2) right isosceles triangular shaped dies providing 21% more I/O than a
square die of the same size (area);
(3) 30.degree.-60.degree.-90.degree. right triangular shaped dies providing
28% more I/O than a square die of the same size (area);
(4) "Greatly Elongated Rectangular" shaped dies providing 16% more I/O than
a square die of the same size (area); and
(5) Parallelogram shaped dies providing 14% more I/O than a square die of
the same size (area).
The teachings of CNS-DIES provides for certain non-square dies that yield
an increased number of bond pads in the I/O area, and hence, a more
efficient utilization of the active element area. As illustrated therein,
certain non-square dies will provide an increased number of bond pads in
the I/O area, hence, allowing for an increase in connections to conductive
lines of the lead frame (e.g.), hence, increasing the number of I/O
connections available for a semiconductor package. However, the prior art
technique of packaging semiconductor dies provides for a square (or not
greatly elongated rectangular) die-receiving area. A square die-receiving
area will not have sufficient conductive lines to accommodate the
increased number of bond pads in certain non-square dies. Furthermore, as
will be shown hereinbelow, geometric configurations of a prior art square
die-receiving area provides for fewer conductive lines than certain
non-square die-receiving areas of the present invention.
Prior art semiconductor packaging techniques do not provide for mounting
certain non-square dies. For example, the prior art would not permit
certain non-square dies to be mounted conveniently in the prior art square
die-receiving area. For one thing, many of the bond wires (e.g.) would be
excessively long, since there is not a good fit between triangles (e.g.)
and squares (e.g.). The industry is in need of a semiconductor package
having a die-receiving area that provides an increased number of
conductive lines, and that will accommodate the packaging of the certain
non-square dies disclosed in CNS-DIES and satisfying the demands for
increased I/O connections.
Parent U.S. patent application Ser. No. 07/933,430, which itself is a
continuation-in-part of the aforementioned Ser. No. 07/916,328 (CNS-DIES),
discloses various techniques for packaging certain non-square dies.
Parent U.S. patent application Ser. No. 07/834,182 discloses a novel
packaging technique which is not explicitly directed to packaging certain
non-square dies (although such is not specifically excluded from that
case).
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide an improved
technique for packaging a die.
It is another object of the present invention to provide a packaging
technique that is relatively inexpensive and relatively easy to
manufacture, and reliable.
It is another object of the present invention to provide a packaging
technique that does not rely on expensive tooling for trimming dambars,
that does not rely on additional tooling for dejunking, and the like.
It is another object of the present invention to provide a plastic
packaging technique that minimizes wire sweep, and allows for tighter
lead-to-lead spacing and increased pin count.
It is another object of the present invention to provide a layer of
conductive lines having an increased number of conductive lines for given
die-receiving area.
It is another object of the present invention to provide "certain
non-square" die-receiving areas corresponding to "certain non-square"
dies, especially in a package of the type disclosed in parent U.S. patent
application Ser. No. 07/834,182.
It is another object of the present invention to provide a semiconductor
package having a certain non-square die-receiving area corresponding to a
certain non-square die.
It is another object of the present invention to provide a semiconductor
package having increased conductive lines for increased I/O connections.
It is another object of the present invention to provide semiconductor
packages that layout more efficiently on a given printed circuit (mother)
board.
According to the invention, a dambar-less leadframe is sandwiched between
two printed circuit boards (PCBs). The PCBs form a major portion of the
package body, and isolate the leadframe leads from plastic molding
compound.
In one embodiment of the invention, an upper PCB (substrate) is formed as a
square ring, having an opening containing a heat sink element. A lower PCB
is also formed as a square ring, and has a smaller opening for receiving a
die. The back face of the die is mounted to the heat sink. The exposed
front face of the die is wire bonded to inner ends of traces on the
exposed face of the lower PCB. The outer ends of the traces are
electrically connected to the leadframe leads by plated-through vias
extending through the two PCBs. The plated-through vias additionally
secure the sandwich structure together. Plastic is injection/transfer
molded over the front face of the die and the bond wires, forming a
partially-molded package.
In another embodiment of the invention, the upper PCB is a solid planar
element, and is not provided with an opening for a heat sink. The back
face of the die is mounted to the inside surface of the upper PCB.
Further, according to the invention, the conductive lines (leads) of the
leadframe are patterned to define a certain non-square die-receiving area
for mounting a certain non-square die.
According to an aspect of the present invention, the conductive lines
define a triangular die-receiving area for mounting triangular dies.
According to another aspect of the present invention, conductive lines
define a parallelogram shaped die-receiving area for mounting
parallelogram shaped dies.
According to another aspect of the present invention, conductive lines
define a greatly elongated rectangular shaped die-receiving area for
mounting greatly elongated rectangular shaped dies.
According to another aspect of the present invention, conductive lines
define a trapezoidal shaped die-receiving area for mounting greatly
elongated rectangular shaped dies.
According to another aspect of the present invention, any of the geometric
shapes formed by the inner ends of the conductive lines are applicable to
lead frame leads, conductive traces, and the like, in various forms of
semiconductor packaging.
Generally, the outside shape of a package body (i.e., the printed circuit
board substrates or the plastic encapsulant) containing the die may be
square, rectangular (not greatly elongated) or any other "traditional"
shape.
According to another aspect of the present invention, a package body is
formed, and the external shape of the package is similar to the shape of
the die-receiving area formed by the inner ends of the conductive lines.
Inasmuch as the die-receiving areas are termed "certain non-square", these
packages are also "certain non-square".
According to another aspect of the present invention, a number of "certain
non-square" packages are laid out more efficiently on a printed circuit
(mother) board.
Other objects, features and advantages of the invention will become
apparent in light of the following description thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of a first embodiment of the
partially-molded PCB chip carrier of the present invention.
FIG. 2 is a plan view of the leadframe element of the chip carrier of FIG.
1, at an earlier stage of fabrication. FIG. 1 is a section taken on lines
1--1 of FIG. 2.
FIG. 3 is a cross-sectional view of another embodiment of the
partially-molded PCB carrier of the present invention.
FIG. 4A is a plan view diagrammatic representation of a prior art patterned
layer of conductive lines, employing a wire bond technique for connecting
a die to the conductive lines.
FIG. 4B is a plan view diagrammatic representation of a prior art patterned
layer of conductive lines, employing a Tape Automate Bonding technique for
connecting a die to the conductive lines.
FIG. 5A is a plan view diagrammatic representation of a patterned layer of
conductive lines, the inner ends of the conductive lines forming a
triangular die-receiving area, according to the present invention, and
employing a wire bond technique for connecting a die to the conductive
lines.
FIG. 5B is a plan view diagrammatic representation of a patterned layer of
conductive lines, the inner ends of the conductive lines forming a
triangular die-receiving area, according to the present invention, and
employing a Tape Automate Bonding technique for connecting a die to the
conductive lines.
FIG. 6 is a plan view diagrammatic representation of a patterned layer of
conductive lines, the inner ends of the conductive lines forming a
"greatly elongated rectangular" shaped die-receiving area, according to
the present invention, and employing a wire bonding technique (by way of
example) for connecting a die to the conductive lines.
FIG. 7 is a plan view diagrammatic representation of a patterned layer of
conductive lines, the inner ends of the conductive lines forming a
parallelogram shaped die-receiving area, according to the present
invention, and employing a wire bonding technique (by way of example) for
connecting a die to the conductive lines.
FIG. 8 is a plan view diagrammatic representation of a patterned layer of
conductive lines, the inner ends of the conductive lines forming a
trapezoidal shaped die-receiving area, according to the present invention,
and employing a wire bonding technique (by way of example) for connecting
a die to the conductive lines.
FIG. 9 is a cross-sectional view of a plastic molded semiconductor package
enclosing a die mounted to a die attach pad (paddle) within a
corresponding die-receiving area defined by inner end leads according to
the present invention.
FIG. 10 is a cross-sectional view of a tape-based, by way of example
plastic molded, semiconductor package enclosing a die mounted on a tape
substrate within a corresponding die-receiving area defined by inner end
leads according to the present invention.
FIG. 11 is a cross-sectional view of a ceramic semiconductor package
enclosing a die in the die-receiving area defined by the inner end traces
of a conductive layers according to the present invention.
FIG. 11A is a bottom view of a semiconductor package, by way of example the
ceramic package of FIG. 11, the ceramic package having a pin grid array
for external connections to the package.
FIG. 11B is a bottom view of a semiconductor package, by way of example the
ceramic package of FIG. 11, the ceramic package having a ball bump grid
array for external connections to the package.
FIG. 11C is a bottom view of a semiconductor package, by way of example the
ceramic package of FIG. 11, the ceramic package having external leads
providing external connections to the package.
FIG. 12 is a cross-sectional view of a PCB-substrate packaging technique
for mounting a die in the die-receiving area defined by inner end
conductive layer traces, according to the present invention.
FIG. 13 is a plan view of a semiconductor device assembly, according to the
present invention, having a "certain non-square" external configuration,
triangular by way of example.
FIG. 14A is a plan view of mounting a number of triangular semiconductor
packages on a printed circuit "mother" board, according to the present
invention. As employed herein, the term "printed circuit mother board"
refers to any circuit board, or the like, used to mount the semiconductor
package of the present invention and (usually) other additional electronic
components.
FIG. 14B is a plan view of mounting a number of greatly elongated
rectangular semiconductor packages on a printed circuit mother board,
according to the present invention.
FIG. 14C is a plan view of mounting a number parallelogram shaped
semiconductor packages on a printed circuit mother board, according to the
present invention.
FIG. 14D is a plan view of mounting a number of trapezoidal shaped
semiconductor packages on a printed circuit mother board, according to the
present invention.
FIG. 14E is a plan view of mounting a number of triangular dies to a
printed circuit mother board, forming a "multi-chip module", according to
the present invention.
FIG. 15 is a plan view of a leadframe element similar to that shown in FIG.
2, for a package similar to that shown in cross-section in FIGS. 1 or 3,
but adapted for a triangular die shape and a triangular package shape, as
an example of packaging one configuration of certain non-square dies.
Examples for other configurations of certain non-square dies would
resemble FIGS. 6, 7 and 8. A cross-section through the finished package of
FIG. 15 would yield features similar or identical to those shown in FIGS.
1 or 3.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1 and 2 show a molded PCB chip carrier package 100, according to the
present invention.
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