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BACKGROUND OF THE INVENTION
This invention relates to the application of precision delay circuits in
integrated circuit memories to obtain a high operating speed and low power
dissipation.
In the prior art, delay circuits have been conventionally structured in an
integrated circuit chip as a serial string of several inverter gates. This
is illustrated in FIG. 1 by the serial string of N inverters 10-1 through
10-N. Each of the inverters is comprised of a P-channel transistor 10a and
an N-channel transistor 10b; and these two transistors are shown in FIG. 1
only for the first inverter 10-1 in order to simplify the drawing.
In operation, a digital input signal v.sub.i is applied to an input
terminal 10c of the first inverter 10-1. Then signal v.sub.i is high,
transistor 10a is off and transistor 10b is on; whereas when signal
v.sub.i is low, transistor 10a is on and transistor 10b is off. Thus, any
low-to-high transition (or high-to-low transition) in signal v.sub.i
sequentially switches the on/off state of the transistors 10a and 10b in
each of the inverters to thereby generate an output signal v.sub.o which
is a delayed replica of the input signal v.sub.i. To increase the delay
between the input signal v.sub.i and the output signal v.sub.o, the total
number N of inverters is increased; and vice-versa.
Also in the prior art, the above-described serial string of inverter gates
is conventionally used in conjunction with an AND gate 11 to generate a
pulse signal v.sub.p. In the case where the total number of inverters N is
odd, the pulse v.sub.p begins when the digital input signal v.sub.i makes
a low-to-high transition; and that pulse v.sub.p lasts until the input
signal transition propagates through the last inverter 10-N.
However, a major problem with the FIG. 1 circuits is that the delay in the
output signal v.sub.o and the width of the pulse signal v.sub.p has a
large tolerance. Such a large tolerance occurs because on any one
particular integrated circuit chip, the transistors 10a and 10b in the
inverters 10-1 through 10-N switch on and off at an unpredictable speed.
This is illustrated by a graph in FIG. 2 wherein a range of switching
speeds is given on the horizontal axis, and the corresponding probability
for any particular switching speed to occur in the transistors 10a and 10b
is given by a curve 12.
Inspection of curve 12 shows that the transistors 10a and 10b on any one
particular chip have an unpredictable switching speed which can be
anywhere between the slowest speed 13a to the fastest speed 13b. In other
words, the switching speed of the transistors 10a and 10b has a tolerance
.DELTA..sub.1 which occurs about a mean speed 13c that lies midway between
the slowest speed 13a and the fastest speed 13b. This switching speed
tolerance .DELTA..sub.1 arises due to certain unavoidable variations in
the process by which the transistors 10a and 10b are fabricated. Two such
process variations are identified in FIG. 2 by reference numeral 14 as
variations in the transistor's gate length and variations in the thickness
of the transistor's gate oxide.
Due to the large switching speed tolerance .DELTA..sub.1 of FIG. 2, the
delayed output signal v.sub.o and the pulse output signal v.sub.p are
generated with a proportionately large tolerance k.DELTA..sub.1 as shown
in FIG. 3. Signal v.sub.o occurs with a minimum delay 15a, a maximum delay
15b, and a mean delay 15c which respectively correspond to the switching
speeds 13a, 13b, and 13c. Similarly, the output pulse v.sub.p occurs with
a minimum width 16a, a maximum width 16b, and a mean width 16c which
respectively correspond to the switching speeds of 13a, 13b and 13c.
In order for the delayed output signal v.sub.o to occur with precision, the
delay tolerance of k.DELTA..sub.1 must be small in comparison to the mean
delay 15c. Likewise, in order for the pulse output signal v.sub.p to have
a precise width, the width tolerance of k.DELTA..sub.1 must be small in
comparison to the mean width 16c. Unfortunately, however, the process
variations 14 become more and more significant as the physical size of the
transistors 10a and 10b get smaller and smaller. For submicron transistors
having a mean size of 0.50 .mu.m, the delay tolerance k.DELTA..sub.1 is
about 90% of the mean 15c.
Accordingly, one object of the invention is to provide an integrated
circuit memory which incorporates a novel delay/pulse generating circuit
to achieve a faster operating speed than the prior art.
Another object of the invention is to provide an integrated circuit memory
which incorporates a novel delay/pulse generating circuit to achieve a
smaller power dissipation than the prior art.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a memory is constructed in an
integrated circuit chip as follows. Firstly, an array of memory cells and
a read/write circuit is provided such that the read/write circuit performs
a predetermined operation on the array for a time interval that is set by
the width of a pulse signal. Also, a pulse generator is provided which is
coupled to the read/write circuit and which contains transistors that
switch on and off at an unpredictable speed to generate the pulse signal
such that the width of the pulse signal has a large tolerance. Further, a
compensation circuit is provided which includes a plurality of
compensation components for the pulse generator circuit. This compensation
circuit selectively couples the compensation components to the pulse
generator such that the selectively coupled components in combination with
the pulse generator's transistors produce the pulse signal with a precise
width that has an insignificant tolerance.
Preferably, the read/write circuit includes bit lines which intercouple the
memory cells, and the predetermined operation precharges the bit lines
during a precise time interval that is set by the transistors in
combination with the compensation components. Also preferably, the
read/write circuit includes a sense amplifier which is coupled to the bit
lines, and the predetermined operation enables the sense amplifier to read
data and dissipate power during a precise time interval that is set by the
transistors in combination with the compensation components.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a delay/pulse generating circuit of the
prior art.
FIG. 2 is a graph which shows a range of switching speeds for the
transistors in the FIG. 1 circuit.
FIG. 3 is a set of signal waveforms which occur in the FIG. 1 circuit.
FIG. 4 is a circuit diagram of one preferred embodiment of a precision
delay/pulse generating circuit which incorporates the present invention.
FIG. 5 is a set of signal waveforms which occur in the FIG. 4 circuit.
FIG. 6 is a graph which explains how certain compensation components in the
FIG. 4 circuit are used depending upon the switching speed of the
transistors in the FIG. 4 circuit.
FIG. 7 shows how an output signal from the FIG. 4 circuit has a precise
delay even though the transitors in the FIG. 4 circuit have a wide range
of switching speeds.
FIG. 8 is a circuit diagram of a second preferred embodiment of a precision
delay/pulse generating circuit which incorporates the present invention.
FIG. 9 is a graph which shows how various compensation components are used
in the FIG. 8 circuit depending upon the switching speed of the
transistors in the FIG. 8 circuit.
FIG. 10 is a circuit diagram of a third preferred embodiment of a precision
delay/pulse generating circuit which incorporates the present invention.
FIG. 11 is a circuit diagram of a static memory in which precharge signals,
wordline signals, and sense signals are precisely generated with the
present invention.
FIG. 12 shows the precharge signals, wordline signals, and sense signals in
the FIG. 11 memory.
FIG. 13 is a circuit which generates the precharge signals, wordline
signals, and sense signals as shown in FIG. 12 in accordance with the
present invention.
FIG. 14 is a circuit diagram of a dynamic memory in which the precharge
signals, wordline signals, and sense signals are precisely generated with
the present invention.
FIG. 15 is a circuit which is an alternative to the FIG. 13 circuit for
generating the precharge signals, wordline signals, and sense signals for
the memories of FIGS. 11 and 14.
FIG. 16a shows a circuit which is used to generate control signals for the
circuit of FIG. 15.
FIG. 16b shows a circuit which is an alternative to the circuit of FIG.
16a.
DETAILED DESCRIPTION
With reference now to FIG. 4, one embodiment of a precision delay circuit,
which incorporates the present invention, will be described in detail.
This FIG. 4 embodiment is comprised of three modules which are identified
by reference numerals 20, 30 and 40; and all three modules are in a single
integrated circuit chip.
Module 20 is a transistor switching circuit which is the same as the
previously described prior art circuit of FIG. 1. Included within module
20 is a serial string of three inverters 20-1, 20-2, and 20-3; and those
inverters respectively correspond to the inverters 10-1, 10-2 and 10-3 of
FIG. 1. Also, included in module 20 is an AND gate 21 which corresponds to
the previously described AND gate 11 in FIG. 1.
Since module 20 is the same as the prior art FIG. 1 circuit, it follows
that the delay in output signal v.sub.o and the width of output pulse
v.sub.p will have a large tolerance when the module 20 operates in
isolation from the other two modules 30 and 40. This large tolerance
occurs because the transistors 20a and 20b in the inverters 20-1 through
20-3 switch on and off with an unpredictable speed as was described in
conjunction with FIGS. 2 and 3. By comparison, when Module 20 interacts
with the other two modules 30 and 40, that large tolerance is
substantially reduced.
Module 30 is a control circuit which estimates the speed at which the
transistors 20a and 20b within the inverters 20-1 through 20-3 switch on
and off. As an output, module 30 generates control signals which identify
the estimated switching speed. In the FIG. 4 embodiment, the estimated
switching speed has three quantized values of slow, medium and fast. An
estimate of a slow switching speed causes signal SL to go high on an
output 30a; an estimate of a medium switching speed causes signal MED to
go high on an output 30b; and an estimate of a fast switching speed causes
signal FA to go high on an output 30c.
Within module 30, the three control signals of SL, MED and FA are generated
by a ring oscillator 31, a divide by N circuit 32, an up-counter 33, and a
decoder 34. All of these components are interconnected to each other as
shown.
Ring oscillator 31 is made up of one NAND gate 31-1 plus two inverters 31-2
and 31-3. When an enable signal EN to the NAND gate 31-1 is low, the ring
oscillator 31 is inhibited from oscillating and generates a high output
signal OSC. Conversely, when signal EN is high, the output signal OSC from
the ring oscillator 31 oscillates at a frequency which is proportional to
the switching speed of the transistors 31a and 31b within the NAND gate
31-1 and the two inverters 31-2 and 31-3.
Those transistors 31a and 31b in the ring oscillator 31 switch on and off
at essentially the same speed as the transistors 20a and 20b within the
inverters 20-1 through 20-3 of module 20. This correspondence in switching
speed occurs because all of the transistors in the modules 20, 30 and 40
are fabricated on the same integrated circuit chip at the same time; and
consequently, the particular physical tolerances which those transistors
have will track each other.
For example, if the transistors 20a and 20b in the inverters 20-1 through
20-3 have a gate oxide thickness which is less than the mean, then the
transistors 31a and 31b in the ring oscillator will also have essentially
that same thin gate oxide. Similarly, if the transistors 20a and 20b in
the inverters 20-1 through 20-3 have a gate length which is less than the
mean, then the transistors 31a and 31b in the ring oscillator will also
have essentially the same short gate length.
Signal OSC from the ring oscillator 31 is sent to the divide by N circuit
32; and in response, that circuit generates an output signal OSCN. Signal
OSCN is the same as the signal OSC except that it is reduced in frequency
by a factor of N.
Signal OSCN is sent to a clock input CK on the up-counter 33; and, that
counter also receives a reset signal RES on a reset input R. When signal
RES is high, the counter 33 is reset to a count of zero; whereas when
signal RES is low, the counter 33 counts up by one for each low-to-high
transition which occurs in the signal OSCN.
Thus, by resetting the counter 33 and subsequently enabling the ring
oscillator 30 for a predetermined time interval, a count is generated in
the up-counter 33 which indicates the speed at which the transistors 20a
and 20b switch on and off. As the switching speed of those transistors 20a
and 20b is increased, the corresponding count in the up-counter 33 also
increases; and vice-versa.
From the up-counter 33, the count signals CNT are sent to the decoder 34.
There, the count is quantized by determining if it falls within a "small"
range or a "medium" range or a "large" range. A count which is small
(SL=1) indicates that the transistors switch at a slow speed; a count
which is medium (MED=1) indicates that the transistors switch at a medium
speed; and a count which is large (FA=1) indicates that the transistors
switch at a fast speed.
Each of the output signals SL, MED and FA from module 30 are sent as inputs
to module 40 which is a compensation circuit. This compensation circuit
includes three small capacitors C.sub.S, three medium capacitors C.sub.M,
three large capacitors C.sub.L, three sets of pass gates 41-43, and three
inverters 44-46. Each pass gate consists of one N-channel transistor and
one P-channel transistor. All of these components are interconnected as
shown.
When signal SL is high, module 40 couples the small capacitors C.sub.S
through the pass gates 41 to the serial string of inverters 20-1 through
20-3. When signal MED is high, module 40 couples the medium capacitors
C.sub.M though the pass gates 42 to the serial string of inverters 20-1
through 20-3. When the control signal FA is high, module 40 couples the
large capacitors C.sub.L through the pass gates 43 to the serial string of
inverters 20-1 through 20-3.
By coupling the small capacitors C.sub.S to the inverters 20-1 through
20-3, a small delay is added to the output signal v.sub.o because the
small capacitors charge and discharge is a short time interval. Similarly,
by coupling the medium capacitors C.sub.M to the inverters 20-1 through
20-3, a medium delay is added to the output signal v.sub.o. Likewise, by
coupling the large capacitors C.sub.L to the inverters 20-1 through 20-3,
a large delay is added to the output signal v.sub.o.
These added delays substantially reduce the tolerance in the total delay of
the output signal v.sub.o because they compensate for variations in the
switching speed of the transistors 20a and 20b. If those transistors
switch in the fast speed range, then a large delay is added; if they
switch in the medium speed range, then a medium delay is added; and if
they switch in the slow speed range, then a small delay is added.
A timing diagram which illustrates the operation of the control module 30
and the compensation module 40 is shown in FIG. 5. There, the up-counter
33 is reset to a count of zero by the reset signal RES being high during a
time interval .DELTA.T.sub.R. Thereafter, at time t.sub.1, the enable
signal EN goes high; and in response, signal OSC from the ring oscillator
31 starts to oscillate.
Each low-to-high transition in the ring oscillator signal OSC causes the
up-counter 33 to increment the count signal CNT by one. As long as that
count does not exceed a predetermined number N.sub.1, the control signal
SL from the decoder 34 will be high; and in FIG. 5, this occurs up to a
time instant t.sub.2. At that time, the count exceeds the number N.sub.1
and thus control signal SL goes low while control signal MED goes high.
Signal MED stays high as long as the count in the up-counter 33 does not
exceed another predetermined number N.sub.2. In FIG. 5, the count N.sub.2
is shown as being exceeded at time instant t.sub.3. When that occurs,
control signal MED goes low while control signal FA goes high.
After the enable signal EN has been high for a predetermined time internal
.DELTA.T.sub.E, the enable signal EN goes low; and that causes the ring
oscillator to stop oscillating. Consequently, the count signals CNT and
the control signals SL, MED, and FA maintain the state which they have at
the end of the time interval .DELTA.T.sub.E.
Considering now FIGS. 6 and 7, they illustrate the degree to which the
tolerance in the output signals v.sub.o and v.sub.p is reduced by the
application of the control signals SL, MED, and FA to the compensation
module 40. In FIG. 6, the graph of FIG. 2 is repeated wherein the range of
switching speeds for the transistors 20a and 20b is given on the
horizontal axis and the corresponding probability for any particular
switching speed to occur is given by the curve 12.
Also in FIG. 6, the range of switching speeds on the horizontal axis is
partitioned into three equal width sub-ranges of slow, medium and fast.
Control signal SL is high when the switching speed is in the slow
sub-range; control signal MED is high when the switching speed is in the
medium sub-range; and control signal FA is high indicates when the
switching speed is in the fast sub-range.
Capacitance C.sub.S is selected such when the switching speed of the
transistors 20a and 20b is at the middle of the slow sub-range, then the
output signal v.sub.o from module 20 will have an ideal predetermined
delay 51a. However, within that slow speed sub-range, the speed of the
transistors 20a and 20b have a tolerance .DELTA..sub.2 as is shown in FIG.
6. Consequently, when the switching speed of the transistors 20a and 20b
is at the high end of the slow switching speed sub-range, the output
signal v.sub.o from module 20 will have a tolerance k.DELTA..sub.2 which
is shown in FIG. 7 by reference numeral 51b. Similarly, when the switching
speed of the transistors 20a and 20b is at the low end of the slow
switching speed sub-range, the output signal v.sub.o from module 20 will
have a tolerance k.DELTA..sub.2 which is shown in FIG. 7 by reference
numeral 51c.
Capacitance C.sub.M is selected such that when the switching speed of the
transistors 20a and 20b is at the middle of medium sub-range, then the
output signal v.sub.o from module 20 will again have the ideal
predetermined delay 51a. Likewise, capacitance C.sub.L is selected such
that when the switching speed of the transistors 20a and 20b is at the
middle of the fast speed sub-range, then the output signal v.sub.o from
module 20 will have the ideal predetermined delay 51a. However, within the
medium and fast speed sub-ranges, the speed of the transistors 20a and 20b
have the tolerance .DELTA..sub.2 as shown in FIG. 6. Thus, when the
switching speed of the transistors 20a and 20b is at either the high end
or the low end of the medium or the fast speed sub-ranges, the output
signal v.sub.o from module 20 will have a tolerance k.DELTA..sub.2 as
shown in FIG. 7.
By comparing the switching speed tolerance .DELTA..sub.2 which occurs in
each speed sub-range (slow, medium and fast) to the overall switching
speed tolerance .DELTA..sub.1 as shown in FIG. 2, it is seen that the
sub-range tolerance .DELTA..sub.2 is one-third of the overall tolerance
.DELTA..sub.1. Consequently, the corresponding tolerance k.DELTA..sub.2
which occurs in the delayed output signal v.sub.o of FIG. 7 is only
one-third of the tolerance k.DELTA..sub.1 which occurs in the output
signal v.sub.o of FIG. 3. This means that the control module 30 and
compensation module 40 of FIG. 4 reduce the tolerance in the delayed
output signal v.sub.o and the pulse signal v.sub.p from module 20 by 300%!
Both the structure and the operation of the FIG. 4 precision delay circuit
have now been described in detail. In addition, however, many changes and
modifications can be made to the details of this particular embodiment.
For example, the serial string of three inverter 20-1 through 20-3 as
shown in FIG. 4 can be replaced with a serial string of any number of
inverters. For each such inverter in that serial string, the capacitors
C.sub.S, C.sub.M, and C.sub.L need to be coupled through respective pass
gates 41, 42, and 43 to the inverter output.
As another modification, the decoder 34 in the FIG. 4 circuit can be
modified such that it quantizes the count from the counter 33 into any
number of sub-ranges. For each such sub-range, a separate control signal
from the decoder output must be generated; and for each such control
signal, a separate group of compensation capacitors and pass gates must be
provided.
For example, the decoder 34 can partition the count from the counter 33
into eight sub-ranges of equal width. In that case, the decoder 34 will
generate eight control signals; and the three sets of capacitors C.sub.S,
C.sub.M, and C.sub.L will be replaced by eight sets of capacitors with
different magnitudes. The set of capacitors with the smallest magnitude is
selected by the pass gates when the control signals indicate the count is
in the smallest sub-range; the set of capacitors with the second smallest
magnitude is selected by the pass gates when to the control signals
indicate the count is in the second smallest sub-range; etc.
As another modification, the reset signal RES and the enable signal EN
which are input signals to the control module 30 can be generated by any
circuit as desired; and, that circuit can be integrated into the same chip
which holds the modules 20-40 or it can be exterior to the chip. Likewise,
the reset and enable signal sequence as shown in FIG. 5 can be initiated
by any event as desired. For example, the FIG. 5 signal sequence can be
initiated manually by a technician, or it can be initiated automatically
by a logic signal from a microprocessor or sequential state machine.
As still another modification, the FIG. 4 embodiment can be changed as
shown in FIG. 8. All of the components in FIG. 8 which occur identically
in FIG. 4 have the same reference numeral; and all of the components in
FIG. 8 which are modifications to the FIG. 4 components have the same
reference numeral with a prime. For example, in FIG. 8, the previously
described control module 30 is modified to control module 30'.
One of the modifications in control module 30' is that the up-counter 33'
is a three-bit counter which is coupled directly to the compensation
module 40'. In other words, in the FIG. 8 embodiment, there is no decoder
on the output of the up-counter 33' which generates control signals that
are sent to the compensation module 40'. Instead, those control signals
come directly from the three-bit counter 33' as BIT2.sup.0, BIT2.sup.1,
and BIT2.sup.2 where BIT2.sup.0 is the least significant bit of the count
and BIT2.sup.2 is the most significant bit of the count.
Also, a modification in the compensation module 40' is that the capacitors
which are selected by the pass gates 41, 42, and 43 have magnitudes which
are binary multiples of each other. Specifically, each of the pass gates
41 is connected to a capacitor of magnitude C.sub.1 ; each of the pass
gates 42 is connected to a capacitor of magnitude 2C.sub.1 ; and each of
the pass gates 43 is connected to a capacitor of magnitude of 4C.sub.1.
How the FIG. 8 embodiment operates is shown in FIG. 9. There the graph of
FIG. 6 is repeated so that the complete range of the switching speeds for
the transistors 20a and 20b is given on the horizontal axis and the
corresponding probability for any particular switching speed to occur is
given by the curve 12.
Also in FIG. 9, the range of switching speeds on the horizontal axis is
partitioned into seven sub-ranges of equal width. These seven sub-ranges
correspond to counts of one through seven in the up-counter 33'. A count
of one in the up-counter 33' occurs when the switching speed of the
transistors 20a and 20b are in the slowest speed sub-range of FIG. 9; a
count of two in the up-counter 33' occurs when the switching speed of the
transistors 20a and 20b is in the second slowest sub-range of FIG. 9; etc.
When the up-counter 33' holds a particular count, each bit in that counter
which is high will couple a capacitor in the compensation module 40' to
the inverters 20-1 through 20-3. For example, when the up-counter 33'
holds a count of three, BIT2.sup.0 and B1T2.sup.1 will both be high. Thus,
capacitor C.sub.1 will be coupled by the pass gates 41 to the inverters
20-1 through 20-3; and simultaneously, capacitors 2C.sub.1 will be coupled
by the pass gates 42 to the inverters 20-1 through 20-3. Likewise, when
the up-counter 33' holds a count of five, BIT2.sup.0 and BIT2.sup.2 will
both be high; and thus capacitors C.sub.1 and 4C.sub.1 will be coupled by
the pass gates 41 and 43 to the inverters 20-1 through 20-3.
Within the compensation circuit 40', the capacitors C.sub.1, 2C.sub.1, and
4C.sub.1 which are selected by the pass gates are interconnected in
parallel; and consequently, they add together. Thus, as the count in the
up-counter 33' increments from one through seven, the total capacitance
which is coupled to the inverters 20-1 through 20-3 also increments from
C.sub.1 to 7C.sub.1. This correlation between the count and the
capacitance is shown in FIG. 9.
Since the overall switching speed range on the horizontal axis of FIG. 9 is
partitioned into seven sub-ranges, the width of each sub-range is only one
seventh of the total switching speed range. Thus, the tolerance
.DELTA..sub.3 from the mean in each sub-range is only one seventh of the
tolerance .DELTA..sub.1 from the mean of the overall speed range.
Consequently, the control module 30' and the compensation module 40' of
FIG. 8 reduce the tolerance in the delayed output signal v.sub.o and the
pulse signal v.sub.p from module 20 by 700%.
As yet another modification, the compensation module 40 in the FIG. 4
embodiment can be changed as shown by module 40" in FIG. 10. All of the
components within module 40" which are identical to components in module
40 of FIG. 4 have the same reference numeral.
One of the changes in module 40" is that each of the pass gates is
connected to a respective resistor instead of a respective capacitor. A
small resistor R.sub.S is connected to each of the pass gates 41; a medium
resistor R.sub.M is connected to each of the pass gates 42; and a large
resistor R.sub.L is connected to each of the pass gates 43. Also, a common
capacitor C is inserted into each of the leads that connect module 40" to
the serial string of inverters 20-1 through 20-3.
When signal SL is high, module 40" couples the small resistors R.sub.S
through the pass gates 41 to the capacitors C. When signal MED is high,
module 40" couples the medium resistors R.sub.M to the capacitors C. When
the control signal FA is high, module 40" couples the large resistors
R.sub.L to the capacitor C. By coupling the small resistors R.sub.S to the
capacitors C, a small delay is added to the output signal v.sub.o of the
serial string of inverters 20-1 through 20-3 because the capacitors C
charge and discharge in a short time interval. Similarly, by coupling the
medium resistors R.sub.M to the capacitors C, a medium delay is added to
the output signal v.sub.o. Likewise, by coupling the large resistors
R.sub.L to the capacitors C, a large delay is added to the output signal
v.sub.o. These added delays substantially reduce the tolerance in the
total delay of the output signal v.sub.o because they compensate for
variations in the switching speed of the transistors 20a and 20b.
Up to this point in the Detailed Description, the focus has been on the
structure and operation of a precision delay/pulse generating circuit by
itself. However, in accordance with the present invention, the
precision/delay pulse generating circuits of FIGS. 4-10 can be
incorporated into several types of integrated circuit memories to increase
operating speed and reduce power dissipation over the prior art. One
preferred embodiment of such a high-speed low-power static memory is shown
in FIG. 11, and the operation of that memory is shown in FIG. 12.
Included within the FIG. 11 memory is a plurality of static memory cells,
one of which is identified by reference numeral 60. Each memory cell
includes a cross-coupled pair of invertors 61 and 62 plus a pair of
transistors 63 and 64. This memory cell 60 is replicated in columns as
indicated by a set of dots 65 and it is replicated in rows as indicated by
a set of dots 66.
All of the remaining components which are shown in FIG. 11 constitute a
read/write circuit for the memory cells. This read/write circuit includes
one pair of bit lines 71 and 72 for each column of memory cells, one
precharge circuit 73 for each column of memory cells, a one sense
amplifier 74 for each column of memory cells, and one pair of write data
transistors 75a and 75b for each column of memory cells. Also, the
read/write circuit includes a respective word line for each row of memory
cells, one of which is identified by reference numeral 76i.
Precharge circuit 73 consists of three transistors 73a, 73b, and 73c. Sense
amplifier 74 consists of five transistors 74a, 74b, 74c, 74d, and 74e. All
of the components within the precharge circuit and the sense amplifier and
the memory cells are interconnected as shown in FIG. 11.
To read data from the i-th row of memory cells, a precharge signal PC and a
word line signal WL.sub.i and a sense amplifier signal SENSE are sent to
the FIG. 11 memory in a particular sequence as shown in FIG. 12. First,
the precharge signal PC is sent to the precharge circuit 73 as a pulse
which has a width W.sub.1. Then, starting at the end of the precharge
pulse PC, the word line signal WL.sub.i goes high. Then, after a delay
D.sub.1, the sense amplifier signal SENSE goes high. This SENSE signal is
a pulse which has a width W.sub.2, and during that pulse the word line
signal WL.sub.i goes low. After the sense pulse is completed, the entire
signal sequence can be repeated.
The purpose of the precharge signal PC is to set the bit line 71 and 72 to
a high voltage level which is the same for both bit lines. To achieve
this, transistors 73a and 73b couple the bit lines to the supply voltage
+V and transistor 73c couples the bit lines to each other. Consequently,
when the precharge pulse PC begins, the voltages B and B' on the bit line
71 and 72 start to equalize at one transistor drop below the supply
voltage +V. This is shown in FIG. 12 by reference numeral 80.
If the width W.sub.1 of the precharge pulse PC is too short, then the
voltages B and B' on the bit lines 71 and 72 will not have time to
equalize and so memory read errors will occur. Conversely, if the width
W.sub.1 of the precharge pulse is too long, then the overall read cycle
time for the memory will be too slow.
In order to achieve both a complete precharge and a fast cycle time, the
width W.sub.1 of the precharge pulse must be precisely controlled. And, in
accordance with the present invention, this is achieved by generating the
precharge pulse PC with the circuits of FIGS. 4 through 10.
After the precharge operation is complete, the word line signal WL.sub.i
goes high to transfer data from one row of memory cells onto the bit
lines. When this occurs, the voltage on one of the bit lines starts to
drop from its precharge level while the voltage on the other bit line
remains unchanged. This is shown in FIG. 12 by reference numeral 81.
The purpose of the delay D.sub.1 is to allow the voltage on one of the bit
lines to drop by a sufficient amount from the precharge level so that the
difference in voltage between the two bit lines can be sensed by the sense
amplifier 74. If the delay D.sub.1 is too small, then the difference
between the bit line voltages will be too small to be sensed properly; and
consequently, memory read errors will occur. Conversely, if the delay
D.sub.1 is too long, then the overall read cycle time for the memory will
be too slow.
In order to achieve both an adequate difference in the bit line voltages
prior to the sense operation and maintain a fast read cycle time, the
length of the delay D.sub.1 must be precisely controlled. And, in
accordance with the present invention, this is achieved by generating the
delay D.sub.1 with the circuits of FIGS. 4 through 10.
After the delay D.sub.1, the SENSE signal goes high to allow the sense
amplifier to amplify the voltage difference between the bit lines to a
full one or full zero level and thereby generate a data output signal
DOUT. This DOUT signal from the sense amplifier must be maintained long
enough to be latched into a flip-flop (which is not shown in FIG. 11) so
that the sensed memory data will be available for use for one complete
memory cycle. Thereafter, the sense pulse can end and the precharge pulse
for the next cycle can begin.
If the width W.sub.2 of the sense pulse is too short, then the data output
signal DOUT will not last long enough to be latched into a flip-flop; and
consequently, memory read errors will occur. Conversely, if the width
W.sub.2 of the sense pulse is too long, then the overall read cycle time
for the memory will be too slow.
In addition, if the width W.sub.2 of the sense pulse is too long, then the
power dissipation in the FIG. 11 memory will be too high. This is because
during the sense pulse transistor 74e is on, and thus a current path is
formed from the supply voltage +V to ground through the three transistors
74a, 74c, and 74e, or through the three transistors 74b, 74d, and 74e.
Thus, in order to provide a data output signal DOUT which is long enough to
be latched and is short enough for a fast low-power cycle time, the width
W.sub.2 of the SENSE pulse must be precisely controlled. And, in
accordance with the present invention, this is achieved by generating the
SENSE pulse with the circuits of FIGS. 4 through 10.
Throughout the above-described read sequence, the write data signals WD1
and WD0 to transistors 75a and 75b are low. To write data into the FIG. 11
memory, the signal sequence of FIG. 12 is repeated with the following
modifications. A "1" is written into a memory cell of the i-th row by
generating signal WD1 as a high voltage when the word line signal WL.sub.i
is high. A "0" is written into a memory cell of the i-th row by generating
WD0 as a high voltage when the word line signal WL.sub.i is high.
Turning now to FIG. 13, it shows the structural details of a circuit which
generates the precharge signal PC, the word line signals WL.sub.i, and the
SENSE signal in accordance with the present invention. This FIG. 13
circuit includes a serial string of N inverters 80-1 through 80-N, a
control/compensation circuit 81, and several AND gates 82 through 85. All
of these components are interconnected as shown in FIG. 13.
Control/compensation circuit 81 has the same internal structure as any of
the previously described modules 30 and 40 of FIG. 4, or 30' and 40' of
FIG. 8, or 40" of FIG. 10. If module 40 of FIG. 4 is used in circuit 81,
then respective capacitors C.sub.S, C.sub.M, C.sub.L and respective pass
gates 41, 42 and 43 are provided for each of the inverters 80-1 through
80-N. Similarly, if module 40" of FIG. 8 is used in circuit 81, then
respective capacitors C.sub.1, 2C.sub.1, 4C.sub.1, and respective pass
gates 41, 42 and 43 are provided for each of the inverters 80-1 through
80-N. Likewise, if module 40" of FIG. 10 is used in circuit 81, then
respective components R.sub.S, R.sub.M, R.sub.L, C, 41, 42, and 43 are
provided for each of the inverters 80-1 through 80-N.
To form the precharge signal PC, the input signal | | |
