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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to cellular mobile communications
systems, and more specifically to a power saving technique for a mobile
unit frequency synthesizer for a TDMA (time division multiple access)
cellular communication system.
2. Description of the Related Art
As illustrated in FIG. 1, a prior art frequency synthesizer for use in a
TDMA cellular mobile communications system includes a direct digital
synthesizer 10 that supplies reference pulses to an initial phase
alignment circuit 11 to which the output of a frequency divider 16 is also
applied to establish phase alignment with the reference pulse. The phase
aligned signals are input to a phase comparator 12 where their phase
difference is detected and fed via a switch 13 to a loop filter 14. A
voltage-controlled oscillator 15 supplies a VCO output to the frequency
divider 16 at a frequency variable with the output of the loop filter 14.
A power-saving controlled DC voltage is supplied to the power-draining
units of the frequency synthesizer such as DDS 10, phase comparator 12 and
frequency divider 16 to periodically turn off their power supplies to
reduce their energy consumption.
When the mobile unit is in a standby mode in a host cell site area, the
power supply to the transmitter is continuously turned off and the power
supply to the receiver is periodically turned on and off so as to enable
it to monitor the control slot of the TDMA frame of the host cell site.
The power-saving controlled voltage is synchronized with the power saving
operation of the receiver. During a turn-off period, the switch 13 is
turned off to operate the frequency synthesizer in an open-loop mode by
feeding the VCO 15 with a voltage developed by the loop filter 14 during
the previous turn-on period and currently maintained by the loop filter.
During a talking mode, the transmitter and receiver are alternately turned
on during assigned transmit and receive slots of the TDMA frame and turned
off during other time slots. The receiver is further turned on during an
idle slot of the TDMA frame to enable it to be switched to the channel of
an adjacent cell site for a possible hand-off.
Since the mobile unit is required to make a channel search and return to
the current channel within a short period of time, the prior art mobile
unit cannot turn off the power-draining parts of its frequency synthesizer
at a high speed during talking modes. Therefore, the power saving feature
of the synthesizer is used only during standby modes.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a frequency
synthesizer capable of power savings operation during a talking mode.
In a broader aspect of the present invention, a frequency synthesizer of a
mobile unit for a time division multiple access cellular communication
system is provided. The communication system includes a plurality of cell
site stations each being assigned a channel of unique frequency for
carrying a sequence of transmit/receive slots and idle slots. The
synthesizer comprises a reference pulse source, a phase comparator, a loop
filter, a voltage-controlled oscillator connected to the loop filter,
switch means for establishing and clearing a connection between the phase
comparator and the loop filter, and a frequency divider connected to the
voltage-controlled oscillator for producing an output at a submultiple of
an output frequency of the voltage-controlled oscillator, the phase
comparator being responsive to a reference pulse from the reference pulse
source and the output of the frequency divider for supplying a phase
difference signal to the loop filter. According to the present invention,
a power saving method is provided which comprises the steps of:
a) activating the reference pulse source and operating the switch means to
establish the connection;
b) operating one of the reference pulse source and the frequency divider so
that a channel is established between the mobile unit and a first cell
site station;
c) operating the switch means to clear the connection and deactivating the
reference pulse source to thereby allow signals to be exchanged between
the mobile unit and the first cell site station during a transmit/receive
slot of the channel in a power saving mode;
d) activating the reference pulse source, operating the switch means to
reestablish the connection, and operating one of the reference pulse
source and the frequency divider during an idle slot of the channel to
receive a signal from a second cell site station;
e) operating one of the reference pulse source and the frequency divider so
that signals can be exchanged between the mobile unit and the first cell
site station during a subsequent transmit/receive slot of the channel; and
f) repeating the steps (c) to (e).
According to a first specific aspect of the present invention, a frequency
synthesizer is provided for a mobile unit of a time division multiple
access (TDMA) cellular communication system wherein each of a plurality of
cell site stations is assigned a channel of unique frequency for carrying
a sequence of transmit/receive slots and idle slots. The frequency
synthesizer comprises a reference pulse source for generating pulses of
reference frequency, a phase comparator for generating a phase difference
signal indicative of a phase difference between two input signals applied
thereto, first and second loop filters, first switch means for selecting
one of the first and second loop filters, second switch means for
establishing a connection between the output of the phase comparator and
the selected loop filter in response to a close-loop command signal to
cause the selected loop filter to develop a voltage according to the phase
difference signal and clearing down the connection in response to an
open-loop command signal, a voltage-controlled oscillator connected to the
selected loop filter for generating an output signal at a frequency
corresponding to the voltage developed by the selected loop filter, a
frequency divider connected to the voltage-controlled oscillator for
producing an output pulse at a submultiple of the frequency of the
voltage-controlled oscillator, and a phase alignment circuit for
establishing initial phase alignment between an output pulse from the
frequency divider and a reference pulse from the reference pulse source in
response to an enable signal and applying the phase-aligned signals to the
phase comparator as the two input signals. A controller is provided for
(a) generating the closed-loop command signal, causing the first switch
means to select the first loop filter, and controlling one of the
reference pulse source and the frequency divider to establish a channel
between the mobile unit and a first cell site station, (b) generating the
open-loop command signal during a transmit/receive slot of the established
channel to thereby allow signals to be exchanged with the first cell site
station in an open loop mode of the synthesizer, (c) generating the
close-loop command signal, causing the first switch means to select the
second loop filter, controlling one of the reference pulse source and the
frequency divider and generating the enable signal during an idle slot of
the established channel to receive a signal from a second cell site
station, and (d) causing the first switch means to select the first loop
filter, controlling one of the reference pulse source and the frequency
divider and generating the enable signal during the idle slot so that
signals can be exchanged again with the first cell site station during a
subsequent transmit/receive slot of the channel.
According to a second specific aspect of the present invention, the
frequency synthesizer includes a phase-lock detector connected to the
phase comparator for producing a phase-lock detect signal when the phase
difference indicates that the two input signals are locked in phase and
means for generating a steady-state detect signal indicating that the
voltage developed in the loop filter has attained a substantially steady
value. A gate circuit generates a signal when the phase-lock detect signal
and the steady-state detect signal are simultaneously present. A
controller is provided for (a) generating said closed-loop command signal
and controlling one of the reference pulse source and the frequency
divider to establish a channel between the mobile unit and a first cell
site station, (b) generating said open-loop command signal in response to
the signal from said gate means to allow signals to be exchanged with the
first cell site station in an open loop mode of the synthesizer during a
transmit/receive slot of the established channel, (c) generating said
close-loop command signal, controlling one of said reference pulse source
and the frequency divider and generating said enable signal during an idle
slot of the established channel to receive a signal from a second cell
site station, and (d) controlling one of said reference pulse source and
the frequency divider and generating said enable signal during said idle
slot so that signals can be exchanged again with the first cell site
station during a subsequent transmit/receive slot of the channel.
According to a third specific aspect, the frequency synthesizer includes a
delay circuit for delaying the output of the frequency divider for a
predetermined interval, and a phase-lock detector connected to the phase
comparator for producing a phase-lock detect signal when the phase
difference indicates that the two input signals are locked in phase. A
switch is provided for exclusively connecting the reference pulse to the
phase alignment circuit in response to a first mode signal or exclusively
connecting the output of the delay circuit to the phase alignment circuit
in response to a second mode signal. A controller is provided for (a)
operating the switch means to apply the reference pulse to the second
input terminal of the phase comparator, and operating one of the reference
pulse source and the frequency divider so that a channel is established
between the mobile unit and a first cell site station, (b) operating the
switch means to apply the output signal of the delay means to the second
input terminal of the phase comparator when the phase difference indicates
that signals at the first and second input terminals of the phase
comparator are locked in phase to allow signals to be exchanged between
the mobile unit and the first cell site station in an open-loop mode
during a transmit/receive slot of the channel, (c) operating the switch
means to apply the reference pulse to the second input terminal of the
phase comparator, and operating one of the reference pulse source and the
frequency divider during an idle slot of the channel to receive a signal
from a second cell site station, and (d) operating one of the reference
pulse source and the frequency divider so that signals can be exchanged
between the mobile unit and the first cell site station during a
subsequent transmit/receive slot of the channel.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be described in further detail with reference to
the accompanying drawings, in which:
FIG. 1 is a block diagram of a prior art frequency synthesizer;
FIG. 2 is a block diagram of a frequency synthesizer and associated TDMA
cellular mobile circuitry according to a first embodiment of the present
invention;
FIG. 3 is a timing diagram associated with the first embodiment of the
present invention;
FIG. 4 is a flowchart diagram associated with the first embodiment of the
present invention;
FIG. 5 is a block diagram of a frequency synthesizer and associated TDMA
cellular mobile circuitry according to a second embodiment of the present
invention;
FIG. 6 is a circuit diagram showing details of a steady state detector;
FIG. 7 is a timing diagram associated with the second embodiment of the
present invention;
FIG. 8 is a flowchart diagram associated with the second embodiment of the
present invention;
FIG. 9 is a block diagram of a frequency synthesizer and associated TDMA
cellular mobile circuitry according to a third embodiment of the present
invention;
FIG. 10 is a timing diagram associated with the third embodiment of the
present invention; and
FIG. 11 is a flowchart diagram associated with the third embodiment of the
present invention.
DETAILED DESCRIPTION
Referring now to FIG. 2, there is shown a mobile unit according to a first
embodiment of the present invention. The mobile unit comprises a digital
radio transceiver 22 that transmits an uplink burst in a transmit slot of
a TDMA frame to a host cell site station and receives a downlink burst in
a receive slot of the frame from the cell site. The transmit section
(transmitter) of transceiver 22 is powered through a power line 50 from a
power supply (battery) unit 20 under the control of a power saving circuit
21 and the receive section (receiver) of the transceiver is powered
through a power line 51 under the control of power saving circuit 21. A
controller 23 is connected to the transceiver 22 to monitor the operating
state of the mobile unit and provides power-saving control signals
(standby/talk mode and power saving on/off command) to power saving
circuit 21 and timing control signals (sync enable and close/open command)
to a phase-locked loop 30 in a manner as will be described later. A signal
level detector 24 is connected to transceiver 22 and controller 23 to
measure the level of a TDMA frame received by the mobile unit.
The phase-locked loop 30 includes a direct digital synthesizer 31 for
generating a reference frequency, an initial phase alignment circuit, or
synchronizer 32, a phase comparator 33, a loop control switch 34 which is
connected through a resistor 35 to a loop filter control switch 40, and a
voltage controlled oscillator 36 which generates the local carrier of the
transceiver 22. A variable frequency divider 37 is connected to the output
of the VCO 36. Loop filters 41 and 42 of resistor-capacitor network are
connected to the outputs of switch 40 to be selectively connected across
the input and ground terminals of VCO 36 in accordance with a loop filter
switching signal from controller 23. The loop filter 41 is normally
connected to the VCO when the transceiver is tuned to a speech channel.
The loop filter 42 is switched into circuit with the VCO during an idle
slot for seeking an idle channel (channel search mode) for possible
hand-off to an adjacent cell site. As will be described, the effect of the
loop filter 41 is to hold the voltage developed in the loop filter
capacitor during a transmit/receive slot and use it again during the next
transmit/receive mode. The voltage reapplied to the VCO from the loop
filter 41 is approximately the same voltage which the VCO received at the
end of the previous transmit/receive mode so that the frequency of the
divider 36 can be made to match the reference frequency in a short period
of time prior to the next transmit/receive mode.
Power saving circuit 21 supplies DC voltage from source 20 to the power
draining units of the phase locked loop 30 such as DDS 31, phase
comparator 33 and frequency divider 37 via a power line 52 and turns off
the power line for power savings purpose in response to a power saving
control signal from the controller 23. The remaining parts of the phase
locked loop 30 are directly powered by the voltage source 20 through power
line 53.
Direct digital synthesizer 31 supplies sharply defined rectangular pulses
at the reference frequency to the initial phase synchronizer 32. This
synchronizer comprises D flip-flops 44, 46 and AND gates 45, 47. Flip-flop
44 receives the outputs of DDS 31 and VCO 36 at its data and clock inputs,
respectively, and produces a high-level Q output in response to a pulse
from the VCO if the binary level at the data input is high or a low-level
Q output in response to the VCO output if the data input's binary level is
low. The output of DDS 31 is also applied to the data input of flip-flop
46 to produce a high-level Q output in response to a sync enable pulse
applied to its clock input from the controller 23. AND gates 45 and 47
receive this sync enable pulse at their first input as well as the output
signals of flip-flop 44 and frequency divider 37 respectively at their
second input. AND gate 45 thus produces a pulse whose leading and trailing
edges are synchronized to the VCO output pulse. The output of flip-flop 46
is applied to frequency divider 37 as an enable pulse to cause it to start
a count operation on the input from the VCO to produce an output frequency
which is a submultiple of the VCO frequency, which submultiple being
varied in response to a channel selection signal from controller 23. The
output of frequency divider 37 causes AND gate 47 to produce a pulse whose
leading and trailing edges are timed with the output pulse of frequency
divider 37, and hence with the VCO output pulse. Thus, the initial phases
of the outputs of flip-flop 44 and frequency divider 37 are synchronized
to each other immediately following the leading edge of the sync enable
pulse as shown in FIG. 3. The output flip-flop 44 is passed through AND
gate 45 to the reference input of phase comparator 33 and the output of
frequency divider 37 is passed through AND gate 47 to the second input of
phase comparator 33.
Phase comparator 33 is any of conventional logic circuits which produces a
high-level output at one of two output terminals when one of the inputs to
the comparator is advancing with respect to the other and produces a
high-level output at the other output terminal when the input phase
relation is reversed. A circuit known as a charge-pump is connected to the
output terminals of the logic circuit for charging a loop filter when one
of the outputs is driven high and drawing a charge from the loop filter
when the other output is driven high.
When the loop control switch 34 is in a closed state, the charge-pump of
phase comparator 33 pumps a charge into or draws a charge from the
capacitor of the selected loop filter, so that a voltage corresponding to
the phase difference is developed at the junction between resistor 35 and
the input of switch 40 and this voltage is applied as a frequency control
signal to the VCO 36.
Variable frequency divider 37 is controlled by a channel selection signal
from the controller 23. For possible hand-off operation, channels of
adjacent cell sites must be monitored when a communication proceeds on a
certain speech channel with a host cell site by briefly switching the
frequency of the frequency divider 37 to the channel of an adjacent cell
site in response to a channel selection signal from the controller 23.
During this channel search mode, a filter switching signal is supplied
from the controller 23 to the switch 40 to connect the loop filter 42,
instead of loop filter 41, to the VCO, and a closed-loop command signal is
supplied from the controller 23 to the loop control switch 34 to connect
the phase comparator 33 to the selected loop filter 42.
Note that, instead of controlling the frequency divider 37, the direct
digital synthesizer 31 may be controlled by the channel selection signal
from the controller as indicated by a bus 43.
The TDMA cellular communication system of the present invention uses a
frame format as shown in FIG. 3. Each cell site of the system is allocated
a unique frequency according to the system's frequency reuse plan. The
frequency assigned to each cell site carries a TDMA frame comprising a
plurality of 20-ms two-way channels, each comprising a receive slot for
receiving a burst from the cell site, a transmit slot for transmitting a
burst from the mobile unit, and an idle timeslot in which the mobile unit
is allowed to make a channel search in preparation for a possible hand-off
from the current cell to an adjacent cell.
The operation of the first embodiment will be given below with reference to
a flowchart shown in FIG. 4 in which a sequence of operational steps
performed by the controller 23 is illustrated. Program execution starts
with decision block 60 which initializes the adjacent channel index
variable "i" to one. Exit then is to block 61 to check to see if the
mobile unit is in a standby or a talking mode. If the controller 23
determines that the mobile unit is in a standby mode, it branches at block
61 to block 62 to cause the power saving circuit 21 to interrupt the power
applied to the PLL power line 52. This power interrupt mode is provided
according to the conventional standby-mode periodic power-savings pattern
so that the control slot of the TDMA frame can be accessed to determine
whether there is an incoming call from the host cell site. More
specifically, the standby-mode periodic power-savings pattern is such that
power saving circuit 21 turns off the transmitter continuously during this
mode to save its power consumption, and periodically turns on the receiver
for an interval slightly longer than the TDMA frame period to allow the
controller 23 to monitor the control slot of the TDMA frame of the current
cell site, and then turns it off for an interval much longer than the
frame period to conserve the receive power.
During the standby mode, the controller 23 controls the filter switch 40 to
connect the loop filter 41 to the VCO to allow the receiver to tune to
channel frequency F.sub.1 of the current cell site. Control then advances
to block 63 to open and close the loop control switch 34 in synchronism
with the turn-off and turn-on timing of power line 52 (and hence, the
receiver's turn-off and turn-on timing), and returns to block 61 to repeat
the process. When the switch 34 is in a closed state, the capacitor of
loop filter 41 is driven by the output of phase comparator 33 to develop a
control voltage for the VCO. When it is open, the phase locked loop 30
operates in an open-loop mode, and the control voltage supplied previously
to the VCO is maintained by the capacitor of the loop filter 41. The close
and open states of the PLL are repeated as long as the mobile unit is a
standby mode according to the standby-mode periodic interruption pattern.
If control determines at block 61 that the mobile unit is in a talking
mode, it branches to block 64 to increment the variable "i" to one, and
proceeds to block 65 to determine whether power-on timing is approached.
This timing is used to turn on the phase locked loop immediately prior to
the beginning of an assigned idle slot to allow the phase locked loop to
tune to a selected channel within the period of the subsequent idle slot.
If the answer is negative at block 65, control branches at block 72 to
turn off the PLL power line 52, and returns to block 61. If the answer is
affirmative, control branches to block 66 to turn on the PLL power line 52
(time t.sub.0, FIG. 3). Exit then is to block 67 to apply a sync enable
pulse to the initial phase synchronizer 32 of the PLL (at time t.sub.1) so
that phase comparator 33 is supplied with phase-aligned input pulses. The
establishment of this initial phase synchronization allows phase locked
loop 30 to quickly converge to a stabilized state.
Controller 23 then proceeds to block 68 to supply a closed-loop command
signal to the loop control switch 34 (at time t.sub.2) and apply a channel
selection signal (change-to-F.sub.i) to variable frequency divider 37 and
a filter switching signal to the switch 40 to connect the loop filter 42
to the VCO, instead of loop filter 41. Phase locked loop 30 now operates
in a closed loop using the loop filter 42.
The receiver is thus tuned to the channel of an adjacent cell and the
signal level of this channel is determined by the signal level detector 24
and the controller 23 is informed of this level to determine whether a
hand-off is to be performed, which will be completed until time t.sub.3.
Controller 23 then supplies a channel selection signal (return-to-F.sub.1)
to frequency divider 37 and a filter switching signal to filter control
switch 40 (block 69) to return to the current frequency F.sub.1 to connect
the loop filter 41 to the VCO. Since the voltage maintained in the loop
filter 41 during the channel search mode is substantially equal to the
voltage, the initial phase synchronizer 32 can quickly resynchronize to
the current channel, and the loop filter 41 keeps its capacitor voltage
without being affected by the channel switching operation. No dielectric
absorption problems thus occur in the loop filter capacitor, and the loop
filter keeps its voltage during subsequent channel switching and open loop
operation.
As a result, the phase-locked loop 30 can be stabilized again to frequency
F.sub.1 immediately prior to the next receive slot. Control then proceeds
to block 70 to apply an open-loop command signal to the loop control
switch 34 and a PLL-power turn-off command to power saving circuit 21 to
cause it to turn off the PLL power line 52 (time t.sub.4). Exit then is to
block 71 to check to see if i=k. If it is not, control returns block 61 to
repeat the above process on the channels of the other adjacent cells, and
if it is control returns to block 60 to repeat the process all over again.
It is seen that during the period between times t.sub.3 and t.sub.4, the
loop filter 41 capacitor is driven in a phase-locked mode to update its
voltage level for the subsequent open-loop operation.
When the talking mode proceeds, power saving controller 21 turns off the
transmitter during an assigned receive slot as well as on an assigned idle
slot and turns it on during an assigned transmit slot, while turning the
receiver off during each transmit slot and turning it on during the
assigned receive and idle slots.
FIG. 5 is a block diagram of a second embodiment of the present invention
in which parts corresponding to those in FIG. 2 are marked with the same
numerals as those used in FIG. 2, and the description thereof are omitted
for simplicity. This embodiment differs from the first embodiment by the
use of a single loop filter 80, instead of the switched loop filters.
When channel switching occurs, a rapid voltage change would occur at the
input of the loop filter 80, and a dielectric absorption current flows,
causing voltage fluctuations to occur in the loop filter. A steady state
detector 82 is connected to the loop filter 80 to determine whether such
voltage fluctuations are stabilized and converged to within a narrow
voltage range. A phase-lock detector 83 is connected to the output of
phase comparator 33 to detect a phase comparator output which indicates
that a phase-lock condition is established in the loop and produce a
phase-lock detect signal. The output signals of steady state detector 82
and phase-lock detector 83 are applied to an AND gate 84, whose output is
supplied to controller 23 as a signal to allow it to determine the time at
which the phase locked loop is to be opened again.
FIG. 6 shows details of the steady state detector 82. As illustrated, it
comprises a voltage follower 85 connected to the loop filter 80. The
output of the voltage follower 85 is connected over two paths to
comparators 87 and 88, one being a delay-line path through a
resistor-capacitor delay circuit 86 to the positive input of comparator 87
and to the negative input of comparator 88, and the other being a direct
path to the negative input of comparator 87 and the positive input of
comparator 88. The outputs of both comparators are applied to an AND gate
89 to produce a steady-state detect signal for coupling to the AND gate
84. Comparators 87 and 88 both produce a logic-1 signal when the delayed
output becomes smaller than the offset voltage of the comparators.
The operation of the controller 23 of FIG. 5 will be described with
reference to a timing diagram and a flowchart respectively shown in FIGS.
7 and 8. Referring to FIG. 8, the operation of the controller is
illustrated which differs from the previous embodiment in that it uses
blocks 90 to 95 instead of blocks 68 to 70 of FIG. 4. During the open-loop
mode prior to the turn-on of power line 52 at time t.sub.0, the loop
filter 80 maintains a constant voltage and the VCO 36 is driven with this
voltage. At time t.sub.0, the frequency divider 81 is turned on to receive
the output of the VCO whose frequency is the same as the open-loop mode.
Therefore, the frequency of the output of the frequency divider 81 is
approximately the same as the frequency generated during the previous
open-loop mode. In response to the application of a sync enable pulse to
the PLL 30 at time t.sub.1 (block 67), the output of frequency divider 81
and the reference input of phase comparator 33 are quickly brought into
phase in the same manner as in the previous embodiment.
Control now proceeds to block 90 to close the switch 34 at time t.sub.2.
Exit then is to block 91 to apply a channel switching command to the
frequency divider 81 at time t.sub.3 so that VCO 36 will then be caused to
change its output frequency from F.sub.1 to F.sub.i through a closed-loop
mode of operation. When the phase locked loop 30 subsequently enters a
phase lock state and the VCO frequency is stabilized to F.sub.i, the
output of AND gate 84 will switch to logic 1 as indicated at 84a in FIG.
7. However, the controller 23 ignores this signal. When the controller 23
completes a channel switching for a hand-off to an adjacent cell, it
returns to the channel of the cur | | |
