Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range

Claims

What is claimed is:

1. A flash EEPROM system connected to a voltage source providing an arbitrary source voltage within a prespecified voltage range, comprising:

a plurality of EEPROM cells;

a comparator having a first input receiving said arbitrary source voltage, a second input receiving a first reference voltage within said prespecified voltage range, and an output providing a control signal indicative of a comparison of said arbitrary source voltage to said first reference voltage; and

a voltage generation circuit responsive to said control signal to generate a plurality of voltages for programming, reading, and erasing said plurality of EEPROM cells such that the respective magnitudes of said plurality of voltages for programming, reading, and erasing said EEPROM cells are substantially same values for any received source voltage within said prespecified voltage range.

2. The flash EEPROM system as recited in claim 1, wherein said voltage generation circuit comprises:

means responsive to said control signal, for generating a high voltage from said arbitrary source voltage such that a magnitude of said high voltage is substantially a same value for any received source voltage within said prespecified voltage range; and

means for generating from said source voltage and said high voltage, said plurality of voltages for programming, reading, and erasing said EEPROM cells.

3. The flash EEPROM system as recited in claim 2, wherein said high voltage generating means comprises a regulated charge pump circuit.

4. The flash EEPROM system as recited in claim 3, wherein said regulated charge pump comprises:

a charge pump circuit including a plurality of energy storing elements connected to said arbitrary source voltage such that energy from said arbitrary source voltage is transferred between adjacent ones of said plurality of energy storing elements so as to generate an output voltage greater than said arbitrary source voltage; and

means responsive to said control signal and connected to at least two of said plurality of energy storing elements, for stopping a transfer of energy from one to the other of said at least two energy storing elements and transfering energy from an energy source to the other of said at least two energy storing elements while said control signal is in a first logic state.

5. The flash EEPROM system as recited in claim 4, wherein said regulated charge pump further comprises:

means responsive to a feedback control signal and connected to said at least two of said plurality of energy storing elements for stopping a transfer of energy from one to the other of said at least two energy storing elements when said feedback control signal is in said first logic state; and

means for generating said feedback control signal such that said feedback control signal is only in said first logic state while said output voltage is greater than a second reference voltage by a fixed factor.

6. The flash EEPROM system as recited in claim 5, wherein said second reference voltage is a bandgap reference voltage.

7. The flash EEPROM system as recited in claim 2, further comprising a controller processor, wherein said plurality of voltages generating means comprises:

a plurality of registers respectively storing information indicative of a plurality of voltages suitable for programming, reading, and erasing said EEPROM cells, wherein said information is stored in said plurality of registers by said controller processor and adjusted by said controller processor in response to said control signal; and

a plurality of digital-to-analog converters connected to said high voltage generating means and individually to corresponding ones of said plurality of registers to generate corresponding analog output voltages generally proportional to the information stored in said corresponding ones of said plurality of registers.

8. A self-adaptive voltage generation circuit operative within a continuous voltage source range for generating a plurality of voltages for programming, reading, and erasing a flash EEPROM, comprising:

means for receiving an arbitrary source voltage within said continuous voltage source range, and generating a control signal indicative of a subrange, including the voltage of said received arbitrary source voltage, of said continuous voltage source range; and

means responsive to said control signal, for generating from said arbitrary source voltage, said plurality of voltages for programming, reading, and erasing a flash EEPROM such that the respective magnitudes of said plurality of voltages for programming, reading, and erasing said flash EEPROM are substantially same values for any received arbitrary source voltage within said continuous voltage source range.

9. The self-adaptive voltage generation circuit as recited in claim 8, wherein said control signal generating means comprises a comparator circuit including a first input connected to said arbitrary source voltage, a second input connected to a reference voltage associated with a subrange of said continuous voltage source range, and an output providing said control signal.

10. The self-adaptive voltage generation circuit as recited in claim 9, wherein said comparator circuit generates said control signal such that said control signal is in a first logic state when said arbitrary source voltage is less than said reference voltage, and in a second logic state when said arbitrary source voltage is greater than said reference voltage.

11. The self-adaptive voltage generation circuit as recited in claim 8, wherein said plurality of voltages generating means comprises:

means responsive to said control signal, for generating a high voltage from said arbitrary source voltage such that a magnitude of said high voltage is substantially a same value for any received arbitrary source voltage within said continuous voltage source range; and

means for generating from said arbitrary source voltage and said high voltage, said plurality of voltages for programming, reading, and erasing a flash EEPROM.

12. The self-adaptive voltage generation circuit as recited in claim 11, wherein said plurality of voltages generating means further comprises means responsive to said control signal, for generating from said arbitrary source voltage and said high voltage, said plurality of voltages for programming, reading, and erasing a flash EEPROM such that the respective magnitudes of said plurality of voltages for programming, reading, and erasing a flash EEPROM are substantially same values for any received source voltage within said continuous voltage source range.

13. The self-adaptive voltage generation circuit as recited in claim 12, wherein said plurality of voltages generating means comprises:

a plurality of registers respectively storing information indicative of a plurality of voltages suitable for programming, reading, and erasing a flash EEPROM;

a plurality of digital-to-analog converters connected to said high voltage generating means and individually to corresponding ones of said plurality of registers to generate corresponding analog output voltages proportional to the information stored in said corresponding ones of said plurality of registers; and

means connected to said control signal generating means and said plurality of registers, for storing in said plurality of registers, information indicative of a plurality of voltages suitable for programming, reading, and erasing a flash EEPROM, wherein the information stored in said plurality of registers is adjusted in response to said control signal.

14. The self-adaptive voltage generation circuit as recited in claim 11, wherein said high voltage generating means comprises a regulated charge pump circuit.

15. The self-adaptive voltage generation circuit as recited in claim 13, wherein said regulated charge pump comprises:

a charge pump circuit including a plurality of energy storing elements connected to said arbitrary source voltage such that energy from said arbitrary source voltage is transferred between adjacent ones of said plurality of energy storing elements so as to generate an output voltage greater than said arbitrary source voltage; and

means responsive to said control signal and connected to at least two of said plurality of energy storing elements, for stopping a transfer of energy from one to the other of said at least two energy storing elements and transfering energy from an energy source to the other of said at least two energy storing elements while said control signal is in said first logic state.

16. The self-adaptive voltage generation circuit as recited in claim 15, wherein said regulated charge pump further comprises:

means responsive to a feedback control signal and connected to said at least two of said plurality of energy storing elements for stopping a transfer of energy from one to the other of said at least two energy storing elements when said feedback control signal is in said first logic state; and

means for generating said feedback control signal such that said feedback control signal is only in said first logic state while said output voltage is greater than a reference voltage by a fixed factor.

17. The self-adaptive voltage generation circuit as recited in claim 16, wherein said reference voltage is a bandgap reference voltage.

18. A self-adaptive voltage generation circuit operative within a continuous voltage source range for generating a plurality of voltages for programming, reading, and erasing a flash EEPROM, comprising:

a comparator circuit having a first input connected to an arbitrary source voltage provided to said self-adaptive voltage generation circuit, and at least one second input respectively receiving at least one reference voltage respectively associated with a subrange range of said continuous voltage source range, and having an output providing at least one control signal indicative of a comparison between said received arbitrary source voltage and said received at least one reference voltage; and

a voltage generation circuit connected to said comparator circuit and having a first input connected to said arbitrary source voltage provided to said self-adaptive voltage generation circuit, and at least one second input respectively connected to said at least one control signal, and a plurality of outputs respectively providing said plurality of voltages for programming, reading, and erasing a flash EEPROM such that magnitudes of said plurality of voltages are respectively substantially same values for different connected source voltages within said continuous voltage source range.

19. The self-adaptive voltage generation circuit as recited in claim 18, wherein said plurality of voltages generating means comprises:

means responsive to said control signal, for generating a high voltage from said arbitrary source voltage such that a magnitude of said high voltage is substantially a same value for any received source voltage within said continuous voltage source range; and

means responsive to said control signal, for generating from said arbitrary source voltage and said high voltage, said plurality of voltages for programming, reading, and erasing a flash EEPROM such that the respective magnitudes of said plurality of voltages for programming, reading, and erasing a flash EEPROM are substantially same values for any received source voltage within said continuous voltage source range.

20. The self-adaptive voltage generation circuit as recited in claim 19, wherein said high voltage generating means comprises a regulated charge pump circuit.

21. The self-adaptive voltage generation circuit as recited in claim 20, wherein said regulated charge pump comprises:

a charge pump circuit including a plurality of energy storing elements connected to said arbitrary source voltage such that energy from said arbitrary source voltage is transferred between adjacent ones of said plurality of energy storing elements so as to generate an output voltage greater than said arbitrary source voltage; and

means responsive to said control signal and connected to at least two of said plurality of energy storing elements, for stopping a transfer of energy from one to the other of said at least two energy storing elements and transfering energy from an energy source to the other of said at least two energy storing elements while said control signal is in a first logic state.

22. The self-adaptive voltage generation circuit as recited in claim 21, wherein said regulated charge pump further comprises:

means responsive to a feedback control signal and connected to said at least two of said plurality of energy storing elements for stopping a transfer of energy from one to the other of said at least two energy storing elements when said feedback control signal is in said first logic state; and

means for generating said feedback control signal such that said feedback control signal is only in said first logic state while said output voltage is greater than a bandgap reference voltage by a fixed factor.

23. The self-adaptive voltage generation circuit as recited in claim 19, wherein said plurality of voltages generating means comprises:

a plurality of registers respectively storing information indicative of a plurality of voltages suitable for programming, reading, and erasing a flash EEPROM;

a plurality of digital-to-analog converters connected to said high voltage generating means and individually to corresponding ones of said plurality of registers to generate corresponding analog output voltages proportional to the information stored in said corresponding ones of said plurality of registers; and

means connected to said comparator and said plurality of registers, for storing in said plurality of registers, information indicative of a plurality of voltages suitable for programming, reading, and erasing a flash EEPROM, wherein the information stored in said plurality of registers is adjusted in response to said control signal.

24. The self-adaptive voltage generation circuit as recited in claim 23, wherein said information storing means comprises a controller processor.

25. In an EEPROM device, a voltage regulated charge pump circuit comprising:

a charge pump circuit including a plurality of energy storing elements connected to a power source providing an input voltage to said plurality of energy storing elements such that energy from said power source is transferred between adjacent ones of said plurality of energy storing elements so as to generate an output voltage greater than said input voltage at an output of said charge pump circuit;

means responsive to a feedback control signal and connected to at least two of said plurality of energy storing elements for stopping a transfer of energy from one to the other of said at least two energy storing elements when said feedback control signal is in a first logic state; and

means for generating said feedback control signal such that said feedback control signal is only in a first logic state while said output voltage is greater than a reference voltage by a fixed factor.

26. The voltage regulated charge pump circuit as recited in claim 25, wherein said feedback control signal generating means comprises:

a voltage divider circuit connected to said output voltage so as to generate a feedback voltage which is a fraction of said output voltage, wherein said fraction is inversely related to said fixed factor; and

comparator means for comparing said feedback voltage to said reference voltage, and generating said feedback control signal such that said feedback control signal is in said first logic state when said feedback voltage is greater than said reference voltage.

27. The voltage regulated charge pump circuit as recited in claim 26, wherein said transfer of energy stopping means comprises a transistor having source and drain connected between an adjacent pair of said at least two adjacent energy storing elements, and a control gate connected to said feedback control signal.

28. The voltage regulated charge pump circuit as recited in claim 25, further comprising means responsive to a control Signal and connected to at least two of said plurality of energy storing elements, for stopping a transfer of energy from one to the other of said at least two energy storing elements and transfering energy from an energy source to the other of said at least two energy storing elements while said control signal is in said first logic state.

29. The voltage regulated charge pump circuit as recited in claim 28, wherein said energy source is said power source.

30. In an EEPROM device, a voltage regulated charge pump comprising:

a plurality of voltage doubler circuits, wherein a 1st one of said voltage doubler circuits receives a voltage Vdd and generates, in response to a first clock signal, a first output voltage substantially equal to 2*Vdd during odd phases of said first clock signal and Vdd during even phases of said first clock signal, and a last one of said voltage doubler circuits designated as an nth one of said voltage doubler circuits receives a first (n-1)th output voltage of a second to last one of said voltage doubler circuits designated as an (n-1)th one of said voltage doubler circuits and generates, in response to said first clock signal, a first nth output voltage substantially equal to 2.sup.n *Vdd during said odd phases of said first clock signal and 2.sup.(n-1) *Vdd during said even phases of said first clock signal;

means responsive to a feedback control signal and connected to said (n-1)th and nth ones of said voltage doubler circuits, for electrically disconnecting said (n-1)th one of said voltage doubler circuits from said nth one of said voltage doubler circuits such that said nth voltage doubler circuit does not receive said first (n-1)th output voltage of said (n-1)th one of said voltage doubler circuits while said feedback control signal is in a first logic state; and

means for generating said feedback control signal such that said feedback control signal is only in said first logic state while said first nth output voltage is greater than a reference voltage by a fixed factor.

31. The voltage regulated charge pump circuit as recited in claim 30, wherein said feedback control signal generating means comprises:

a voltage divider circuit connected to said first nth output voltage so as to generate a feedback voltage which is a fraction of said first nth output voltage, wherein said fraction is inversely related to said fixed factor; and

comparator means for comparing said feedback voltage to said reference voltage, and generating said feedback control signal such that said feedback control signal is in said first logic state when said feedback voltage is greater than said reference voltage.

32. The voltage regulated charge pump circuit as recited in claim 31, wherein said transfer of energy stopping means comprises a first transistor having a control gate connected to said feedback control signal, and drain and source electrodes connected between said (n-1)th and nth voltage doubler circuits such that said nth voltage doubler circuit does not receive said first (n-1)th output voltage of said (n-1)th voltage doubler circuit while said feedback control signal is in said first logic state.

33. A method of generating a plurality of voltages for programming, reading, and erasing a plurality of flash EEPROM cells, comprising the steps of:

comparing a source voltage against at least one reference voltage indicative of at least one corresponding subrange within a continuous voltage source range, and generating at least one corresponding control signal in response to such comparison;

adjusting the open loop gain of a regulated charge pump in response to said at least one corresponding control signal such that an output voltage of said regulated charge pump remains substantially the same for source voltages within said continuous voltage source range; and

generating said plurality of voltages for programming, reading, and erasing said plurality of flash EEPROM cells from said output voltage of said regulated charge pump.

34. The method as recited in claim 33, wherein said generating step comprises the steps of:

storing information indicative of said plurality of voltages for programming, reading, and erasing said EEPROM cells into a plurality of registers;

converting the information stored in said plurality of registers into a corresponding plurality of voltages for programming, reading, and erasing said EEPROM cells; and

modifying the information stored in said plurality of registers in response to said control signal so that the plurality of voltages generated by converting the information remain substantially the same.

BACKGROUND OF THE INVENTION

This invention relates in general to voltage generation circuits and in particular, to voltage generation circuits in flash EEPROM systems which are operative within a continuous voltage source range.

In certain applications, it may be desirable for a flash EEPROM system (or flash EEPROM plug-in card) to automatically accomodate either one of two voltage sources which may be connected to the EEPROM system. For example, in a normal mode of operation, a 5 volt voltage source compatible with logic circuitry in the EEPROM system may be connected to the EEPROM system, and in a battery mode of operation, a 3 volt voltage source may be connected to the EEPROM system and automatically accomodated by connecting after its detection, the 3 volt voltage source to a voltage doubler circuit in the EEPROM system.

The operational voltage range for such conventional flash EEPROM systems are typically specified as being discontinuous. For example, the range may be specified as 3 volts.+-.a tolerance (e.g., 5% or 10%), and 5 volts.+-.a tolerance (e.g., 5% or 10%). Intermediate voltages are generally not specified as being within the operational range of these conventional EEPROM systems. For example, with a 5% tolerance, voltages greater than 3.15 volts and less than 4.75 volts are not specified, and with a 10% tolerance, voltages greater than 3.3 volts and less than 4.5 volts are not specified.

In certain applications, however, it may be desirable for a flash EEPROM system (or flash EEPROM plug-in card) to automatically accomodate an arbitrary source voltage within a prespecified continuous range of source voltages. In these applications, the operational voltage source range is preferably specified as a continuous range from 3 to 5 volts.+-.tolerance (e.g., 5% or 10%).

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, one object of the present invention to provide a flash EEPROM system or plug-in card which is operative within a continuous voltage source range.

Another object of the present invention is to provide a self-adaptive voltage generation circuit which is operative within a continuous voltage source range and useful in a flash EEPROM system.

Still another object of the present invention is to provide a voltage regulated charge pump which is operative within a continuous voltage source range and useful in a flash EEPROM system.

These and additional objects are accomplished by the various aspects of the present invention, wherein one aspect is a flash EEPROM system operative within a continuous voltage source range. The flash EEPROM system includes a comparator connected to a voltage source providing an arbitrary source voltage within a prespecified voltage source range, and at least one EEPROM module connected to the comparator. The comparator generates a control signal indicative of a comparison of a reference voltage to the arbitrary source voltage provided by the voltage source. The EEPROM module includes a plurality of EEPROM cells and a voltage generation circuit responsive to the control signal to generate a plurality of voltages for programming, reading, land erasing the plurality of EEPROM cells such that the respective magnitudes of the plurality of voltages for programming, reading, and erasing the EEPROM cells are substantially same values for any received source voltage within the continuous voltage source range.

Another aspect is a self-adaptive voltage generation circuit operative within a continuous voltage source range for generating a plurality of voltages for programming, reading, and erasing a flash EEPROM. The self-adaptive voltage generation circuit includes means for receiving a source Voltage provided to the self-adaptive voltage generation circuit, and generating a control signal indicative of a subrange, including the received source voltage, within the continuous voltage source range; and means responsive to the control signal, for generating from the source voltage, the plurality of voltages for programming, reading, and erasing a flash EEPROM such I that the respective magnitudes of the plurality of voltages for programming, reading, and erasing a flash EEPROM are substantially same values for any received source voltage within the continuous voltage source range.

Another aspect is a self-adaptive voltage generation circuit operative within a continuous voltage source range for generating a plurality of voltages for programming, reading, and erasing a flash EEPROM. The self-adaptive voltage generation circuit includes a comparator circuit and a voltage generation circuit. The comparator circuit has a first input connected to an arbitrary source voltage, at least one second input respectively receiving at least one reference voltage respectively associated with a subrange range of the continuous voltage source range, and an output providing at least one control signal indicative of a comparison between the received arbitrary source voltage and the received at least one reference voltage. The voltage generation circuit is connected to the comparator circuit and has a first input connected to the arbitrary source voltage provided to the self-adaptive voltage generation circuit, at least one second input respectively connected to the at least one control signal, and a plurality of outputs respectively providing the plurality of voltages for programming, reading, and erasing a flash EEPROM such that magnitudes of the plurality of voltages are respectively substantially same values for different connected source voltages within the continuous voltage source range.

Still another aspect is a voltage regulated charge pump circuit comprising: a charge pump circuit including a plurality of energy storing elements (e.g., 3405 and 3406 in FIG. 5) connected to a power source providing an input voltage to the plurality of energy storing elements such that energy from the power source is transferred between adjacent ones of the plurality of energy storing elements so as to generate an output voltage greater than the input voltage at an output of the charge pump circuit; means responsive to a feedback control signal e.g., output of comparator 3420 in FIG. 5) and connected to at least two of the plurality of energy storing elements for stopping a transfer of energy from one to the other of the at least two energy storing elements when the feedback control signal is active; and means for generating the feedback control signal such that the feedback control signal is only active while the output voltage is greater than a reference voltage by a fixed factor.

Yet another aspect is a voltage regulated charge pump comprising: a plurality of voltage doubler circuits, wherein a 1st one of the voltage doubler circuits receives a voltage Vdd and generates, in response to a first clock signal, a first output voltage substantially equal to 2*Vdd during odd phases of the first clock signal and Vdd during even phases of the first clock signal, and a last one of the voltage doubler circuits designated as an nth one of the voltage doubler circuits receives a first (n-1)th output voltage of a second to last one of the voltage doubler circuits designated as an (n-1)th one of the voltage doubler circuits and generates, in response to the first clock signal, a first nth output voltage substantially equal to 2.sup.n *Vdd during the odd phases of the first clock signal and 2.sup.(n-1) *Vdd during the even phases of the first clock signal; means responsive to a feedback control signal and connected to the (n-1)th and nth ones of the voltage doubler circuits, for electrically disconnecting the (n-1)th one of the voltage doubler circuits from the nth one of the voltage doubler circuits such that the nth voltage doubler circuit does not receive the first (n-1)th output voltage of the (n-1)th one of the voltage doubler circuits while the feedback control signal is active; and means for generating the feedback control signal such that the feedback control signal is only active while the first nth output voltage is greater than a reference voltage by a fixed factor.

Still another aspect is a method of generating a plurality of voltages for programming, reading, and erasing a plurality of flash EEPROM cells, comprising the steps of: comparing a source voltage against at least one reference voltage indicative of at least one corresponding subrange within a continuous voltage range of source voltages, and generating at least one corresponding control signal in response to such comparison; adjusting the open loop gain of a regulated charge pump in response to the at least one corresponding control signal such that an output voltage of the regulated charge pump remains substantially the same for source voltages within the continuous voltage range of source voltages; and generating the plurality of voltages for programming, reading, and erasing the plurality of flash EEPROM cells from the output voltage of the regulated charge pump.

Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a illustrates, as an example, a block diagram of a computer system including a host computer and a flash EEPROM system connected to the host computer;

FIG. 1b illustrates, as an example, a block diagram of the flash EEPROM module included in the flash EEPROM system of FIG. 1a;

FIG. 1c illustrates, as an example, a block diagram of the flash EEPROM chip included in the flash EEPROM module of FIG. 1b;

FIG. 2 illustrates, as an example, a block diagram of a conventional voltage generation portion of the conventional flash EEPROM system of FIG. 1a;

FIG. 3 illustrates, as an example, a block diagram of a conventional programmable voltage generation circuit useful in the flash EEPROM system of FIG. 2;

FIGS. 4a-4c respectively illustrate, as examples, circuit schematics of three connectable stages of a conventional charge pump circuit useful in the flash EEPROM system of FIG. 2;

FIG. 4d illustrates, as an example, a block diagram of a conventional charge pump circuit employing the three connectable stages of FIGS. 4a-4c;

FIG. 5 illustrates, as an example, a simplified circuit schematic of a voltage regulation circuit utilizing aspects of the present invention for regulating the high voltage output of the charge pump circuit of FIGS. 4a-4c;

FIG. 6 illustrates, as an example, a simplified circuit schematic of a voltage adjustment circuit utilizing aspects of the present invention for effectively adjusting the open loop gain of the voltage regulation circuit of FIG. 5;

FIGS. 7a and 7b illustrate, as examples, circuit schematics for switching logic included in the voltage adjustment circuit of FIG. 6;

FIGS. 8a-8e respectively illustrate, as examples, a voltage source changing over time, and a flow diagram of a method for maintaining as substantially constant, a plurality of voltages for programming, reading, and erasing EEPROM cells as the voltage source changes over time; and

FIG. 9 illustrates, as an example, a block diagram of a self-adaptive voltage generation portion, utilizing aspects of the present invention, of a flash EEPROM system useful in the computer system of FIG. 1a.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Application Ser. No. 08/325,774 now U.S. Pat. No. 5,508,971, entitled "Programmable Power Generation Circuit for Flash EEPROM Memory Systems," incorporated herein by this reference, and naming Raul-Adrian Cernea, Douglas J. Lee, Mehrdad Mofidi, and Sanjay Mehrotra as inventors, describes a flash EEPROM system functioning as a mass storage medium for a host computer. The flash EEPROM system includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generation circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generation. The multi-voltage generation includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generation circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.

FIGS. 1a-1c illustrate, as an example, a flash EEPROM system 20 (or flash EEPROM plug-in card or module) which serves as a mass storage medium for a host computer 10 by emulating a hard disk system. In FIG. 1a, a simplified block diagram of a computer system is shown including the host computer 10, a system bus 15, and the flash EEPROM system 20 which communicates with the host computer 10 via the system bus 15. Included in the flash EEPROM system 20 are a controller 40 and a flash EEPROM module 30. The controller 40, which includes a processor 43 and a memory 41, interprets the disk drive commands received from the host computer 10, and translates them into corresponding read and write operations for the flash EEPROM module 30, in a manner transparent to the host computer 10.

In FIG. 1b, the flash EEPROM module 30 is shown to include a plurality of flash EEPROM chips, 31-1 to 31-n. In FIG. 1c, each flash EEPROM chip (e.g., 31-1) is shown to include a plurality of flash EEPROM cells 33, conventional row and column decode circuitry, XDEC and YDEC, for accessing selected ones of the flash EEPROM cells 33, certain interface logic 34, and a voltage generator circuit 300 ("VGC") for generating the voltages for programming, reading, and erasing the plurality of flash EEPROM cells 33. Although not shown, the flash EEPROM cells 33 are generally organized in a matrix array and selectively accessed by the row decoder XDEC 38 through a plurality of word lines connected the control gates of flash EEPROM cells in respective rows of the matrix array, and the column decoder YDEC 37 through a plurality of bit lines connected to the drains of flash EEPROM cells in respective columns of the matrix array.

FIG. 2 illustrates, as an example, a simplified block diagram of portions of the flash EEPROM system 20 related to the voltage generation circuit 300. The controller 40 communicates with each of the flash EEPROM chips 33-1 to 33-n of the flash EEPROM module 30 via an internal bus 42 of the flash E