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Claims  |
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We claim:
1. An arbitration circuit in a computer system including a first bus and a
second bus, a slave device coupled to the first bus, a plurality of first
bus master devices coupled to the first bus, an I/O device coupled to the
second bus, a plurality of second bus master devices coupled to the second
bus, and a data routing circuit coupled to the first and second buses for
routing data between the I/O device and the slave device, wherein the
first bus master devices each asserts a corresponding one of a plurality
of first bus request signals to indicate a request for the first bus,
wherein the plurality of first bus master devices include a data transfer
controller for providing control signals to the data routing circuit for
transferring data between the first and second buses, wherein the data
transfer controller provides a command strobe to the second bus I/O device
to indicate a data transfer cycle, wherein each of said plurality of
second bus master devices requests control of the second bus by asserting
one of a plurality of second bus master request signals, wherein the data
transfer controller further asserts a data controller second bus request
signal to indicate a request for the second bus, and wherein the second
bus I/O device and the plurality of second bus master devices utilize
different control signals and the same data signals, the arbitration
circuit comprising:
a first bus arbiter coupled to the first bus and receiving the plurality of
first bus request signals for asserting one of a plurality of grant
signals to select the first bus master device having highest priority; and
a second bus arbiter coupled to the second bus and receiving the data
controller second bus request signal and the plurality of the second bus
master request signals for asserting a data controller second bus grant
signal or one of a plurality of second bus master grant signals to grant
second bus ownership to the data transfer controller or one of the
plurality of second bus master devices depending on which has highest
priority on the second bus,
wherein the data transfer controller asserts the data controller second bus
request signal when a transfer between the second bus I/O device and the
slave device is indicated; wherein, when said data controller second bus
grant signal is asserted by said second bus arbiter, said data transfer
controller responds by asserting the first bus request signal
corresponding to the data transfer controller; and wherein, when said
first bus arbiter asserts the first bus grant signal corresponding to the
data transfer controller, the data transfer controller generates the
control signals for routing data through the data routing circuit.
2. The arbitration circuit of claim 1, wherein the data transfer controller
is a DMA controller, and wherein the slave device is a memory device.
3. The arbitration circuit of claim 2, wherein the second bus I/O device is
an IDE-type device.
4. The arbitration circuit of claim 1, wherein the plurality of first bus
master devices include a first bus controller and a plurality of I/O
cards, wherein the plurality of second bus master devices include a second
bus controller coupled to said first bus controller, said first and second
bus controllers for controlling first-bus-to-second-bus cycles initiated
by a first bus master device, wherein said second bus arbiter assigns in
an arbitration cycle on the second bus the highest priority to said
first-bus-to-second-bus cycles, followed by the data controller second bus
request signal, and then followed by said plurality of second bus master
request signals corresponding to said plurality of I/O cards.
5. The arbitration circuit of claim 4, wherein the plurality of second bus
master devices further include a refresh controller for running refresh
cycles on the second bus, and wherein said second bus arbiter assigns said
second bus master request signal corresponding to said refresh controller
a priority that is higher than said data controller second bus request
signal.
6. The arbitration circuit of claim 4, wherein said second bus arbiter
further includes:
means responsive to the plurality of second bus master request signals and
the data controller second bus grant signal for deasserting the data
controller second bus request signal when one of the plurality of second
bus master request signals is asserted by a corresponding second bus
master device while said data controller second bus grant signal is
asserted; and
means coupled to said data controller second bus request signal deasserting
means and responsive to the plurality of second bus master request signals
for providing a mask signal, said mask signal being asserted if said data
controller second bus request signal is deasserted while said data
controller second bus grant signal is asserted, and if one of the
plurality of second bus master request signals is asserted, wherein said
mask signal masks out further assertions of the data controller second bus
request signal.
7. The arbitration circuit of claim 6, wherein said mask signal providing
means deasserts said mask signal upon completion of a cycle by said second
bus master device on the second bus.
8. The arbitration circuit of claim 6, wherein said data controller second
bus request signal deasserting means is further coupled to said first bus
controller, wherein said data controller second bus request signal is
deasserted if said first bus controller indicates a
first-bus-to-second-bus cycle, and wherein said second bus arbiter further
includes:
means coupled to said mask signal providing means and to said data
controller second bus signal deasserting means for disabling assertion of
said mask signal if said data controller second bus signal is deasserted
in response to a first-bus-to-second bus cycle while said data controller
second bus grant signal is asserted.
9. The arbitration circuit of claim 8, wherein said second bus arbiter
further includes:
a third arbiter receiving the second bus master request signals
corresponding to said plurality of I/O cards, wherein, if said second bus
arbiter indicates that said second bus master request signals
corresponding to said I/O cards have the highest priority in a second bus
arbitration cycle, said third arbiter asserts a second bus master grant
signal corresponding to the highest priority I/O card.
10. The arbitration circuit of claim 9, wherein said third arbiter includes
an 8237-compatible DMA controller having a plurality of channels
corresponding to said plurality of I/O cards, each of said plurality of
channels being programmed in cascade mode.
11. The arbitration circuit of claim 1, wherein said first bus arbiter
assigns priority to said first bus master devices based on a least
recently used scheme.
12. A computer system, comprising:
a first bus;
a second bus;
a slave device coupled to said first bus;
a plurality of first bus master devices coupled to said first bus;
an I/O device coupled to said second bus;
a plurality of second bus master devices coupled to said second bus;
a data routing circuit coupled to said first and second buses for routing
data between said I/O device and said slave device, wherein said first bus
master devices each asserts a corresponding one of a plurality of first
bus request signals to indicate a request for said first bus, wherein said
plurality of first bus master devices include a data transfer controller
for providing control signals to said data routing circuit for
transferring data between said first and second buses, wherein said data
transfer controller provides a command strobe to said second bus I/O
device to indicate a data transfer cycle, wherein each of said plurality
of second bus master devices requests control of said second bus by
asserting one of a plurality of second bus master request signals, wherein
said data transfer controller further asserts a data controller second bus
request signal to indicate a request for said second bus, and wherein said
second bus I/O device and said plurality of second bus master devices
utilize different control signals and the same data signals;
a first bus arbiter coupled to said first bus and receiving said plurality
of first bus request signals for asserting one of a plurality of grant
signals to select said first bus master device having highest priority;
and
a second bus arbiter coupled to said second bus and receiving said data
controller second bus request signal and said plurality of said second bus
master request signals for asserting a data controller second bus grant
signal or one of a plurality of second bus master grant signals to grant
second bus ownership to said data transfer controller or one of said
plurality of second bus master devices depending on which has highest
priority on said second bus,
wherein said data transfer controller asserts said data controller second
bus request signal when a transfer between said second bus I/O device and
said slave device is indicated; wherein, when said data controller second
bus grant signal is asserted by said second bus arbiter, said data
transfer controller responds by asserting said first bus request signal
corresponding to said data transfer controller; and wherein, when said
first bus arbiter asserts said first bus grant signal corresponding to
said data transfer controller, said data transfer controller generates
said control signals for routing data through said data routing circuit.
13. The computer system of claim 12, wherein said data transfer controller
is a DMA controller, and wherein said slave device is a memory device.
14. The computer system of claim 13, wherein said second bus I/O device is
an IDE-type device.
15. The computer system of claim 12, wherein said plurality of first bus
master devices include a first bus controller and a plurality of I/O
cards, wherein said plurality of second bus master devices include a
second bus controller coupled to said first bus controller, said first and
second bus controllers for controlling first-bus-to-second-bus cycles
initiated by a first bus master device, wherein said second bus arbiter
assigns in an arbitration cycle on said second bus the highest priority to
said first-bus-to-second-bus cycles, followed by said data controller
second bus request signal, and then followed by said plurality of second
bus master request signals corresponding to said plurality of I/O cards.
16. The computer system of claim 15, wherein said plurality of second bus
master devices further include a refresh controller for running refresh
cycles on said second bus, and wherein said second bus arbiter assigns
said second bus master request signal corresponding to said refresh
controller a priority that is higher than said data controller second bus
request signal.
17. The computer system of claim 15, wherein said second bus arbiter
further includes:
means responsive to said plurality of second bus master request signals and
said data controller second bus grant signal for deasserting said data
controller second bus request signal when one of said plurality of second
bus master request signals is asserted by a corresponding second bus
master device while said data controller second bus grant signal is
asserted; and
means coupled to said data controller second bus request signal deasserting
means and responsive to said plurality of second bus master request
signals for providing a mask signal, said mask signal being asserted if
said data controller second bus request signal is deasserted while said
data controller second bus grant signal is asserted, and if one of said
plurality of second bus master request signals is asserted, wherein said
mask signal masks out further assertions of said data controller second
bus request signal.
18. The computer system of claim 17, wherein said mask signal providing
means deasserts said mask signal upon completion of a cycle by said second
bus master device on said second bus.
19. The computer system of claim 17, wherein said data controller second
bus request signal deasserting means is further coupled to said first bus
controller, wherein said data controller second bus request signal is
deasserted if said first bus controller indicates a
first-bus-to-second-bus cycle, and wherein said second bus arbiter further
includes:
means coupled to said mask signal providing means and to said data
controller second bus signal deasserting means for disabling assertion of
said mask signal if said data controller second bus signal is deasserted
in response to a first-bus-to-second bus cycle while said data controller
second bus grant signal is asserted.
20. The computer system of claim 19, wherein said second bus arbiter
further includes:
a third arbiter receiving said second bus master request signals
corresponding to said plurality of I/O cards, wherein, if said second bus
arbiter indicates that said second bus master request signals
corresponding to said I/O cards have said highest priority in a second bus
arbitration cycle, said third arbiter asserts a second bus master grant
signal corresponding to said highest priority I/O card.
21. The computer system of claim 20, wherein said third arbiter includes an
8237-compatible DMA controller having a plurality of channels
corresponding to said plurality of I/O cards, each of said plurality of
channels being programmed in cascade mode.
22. The computer system of claim 12, wherein said first bus arbiter assigns
priority to said first bus master devices based on a least recently used
scheme. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to bus arbitration protocols, and more particularly,
to a protocol including multiple arbiters for arbitrating access to a
plurality of buses.
2. Description of the Related Art
The performance demands on personal computers are ever increasing. It has
been determined that a major bottleneck in improving performance is the
capability to perform input/output (I/O) operations. Processor speeds
continue to increase at a great rate and memory speeds and architectures
can partially keep pace. However, the speed of I/O operations, such as
disk and local area network (LAN) operations, has not kept pace. The
increasing complexity of video graphics used in personal computers is also
demanding greater performance then can be conventionally provided.
Some of the problems were in the bus architecture used in IBM PC-compatible
computers. The EISA architecture provided some improvement over the ISA
architecture of the IBM PC/AT, but more performance was still required. To
this end Intel Corporation, primarily, developed the Peripheral Component
Interconnect (PCI) bus. The PCI bus is a mezzanine bus between the host or
local bus in the computer, to which the processor and memory are
connected, and the I/O bus, such as ISA or EISA. For more details on the
PCI bus, reference to the PCI Standard Version 2.0, from the PCI Special
Interest Group in care of Intel Corp., which is hereby incorporated by
reference, is advised. The bus was designed to have a high throughput and
to take advantage of the increasing number of local processors that
support I/O functions. For example, most disk controllers, particularly
SCSI controllers, and network interface cards (NICs) include a local
processor to relieve demands on the host processor. Similarly, video
graphics boards often include intelligent graphics accelerators to allow
higher level function transfer. Typically these devices have the
capability of operating as bus masters, to allow them to transfer data at
the highest possible rates.
Because of the number of potential devices trying to be bus masters, an
arbitration scheme is required. A common arbitration scheme is
least-recently-used (LRU). In certain cases, such as described in
application Ser. No. 07/955,499, entitled "Prioritization of
Microprocessors in Multiprocessor Computer Systems," filed on Oct. 2,
1992, now U.S. Pat. No. 5,535,395 which is hereby incorporated by
reference, the LRU scheme is modified so that the LRU of just the various
requestors is utilized. This avoids potential deadlock conditions.
Another arbitration scheme is described in U.S. patent application Ser. No.
08/187,843, entitled "Bus Master Arbitration Circuitry Having Improved
Prioritization," hereby incorporated by reference. The '843 application
described an arbiter for the PCI bus which minimizes thrashing on a bus
due to a retry generated by a target device. According to the PCI
standard, responding target devices may disconnect a cycle by generating a
retry to the bus master. By so disconnecting the operation, other bus
masters are allowed to gain access to the bus while the target device that
generated the retry is given the opportunity to clear whatever condition
caused it to issue the retry. The '843 application described an arbiter
which masked further requests from the retried master to prevent thrashing
of the bus. However, the high priority of the masked request is maintained
in subsequent arbitration cycles.
In the computer system described in the '843 application, other arbiters
also existed for performing arbitration for other resources. The computer
system included a PCI bus, an EISA bus, and a DMA controller. The multiple
arbiters worked together to arbitrate access to the PCI and EISA buses.
SUMMARY OF THE PRESENT INVENTION
A computer system according to the present invention includes multiple
arbiters for arbitrating access to a plurality of buses. In the preferred
embodiment, a PCI bus and ISA bus form the main buses in the computer
system. The PCI bus has a plurality of bus masters, including a CPU/main
memory subsystem, a PCI-ISA bridge, and other PCI masters. The PCI-ISA
bridge is the means by which an enhanced DMA (EDMA) controller and ISA bus
masters can gain access to the PCI bus. The EDMA controller in the
preferred embodiment controls main memory accesses by IDE devices.
Preferably, a command cycle is generated on the PCI bus to notify the EDMA
controller if a disk write or disk read is desired. In response, the EDMA
controller asserts the proper command strobes to the selected IDE device.
The transfer of data between the selected IDE device and the PCI bus are
accomplished via the data portion of the ISA bus. The ISA bus masters
include a refresh controller, a DMA controller, and ISA bus master cards.
Thus, in the preferred embodiment, there is a PCI arbiter for arbitrating
requests for the PCI bus from the various potential PCI bus masters,
including the CPU/main memory subsystem, the EDMA controller, the DMA
controller, ISA bus masters, and other PCI bus masters. Further, there is
an arbiter for the data portion of the ISA bus, which requests can come
from the EDMA controller, the refresh controller, the DMA controller, one
of the PCI masters in a PCI-to-ISA cycle, and one of the ISA bus masters.
The priority of the ISA bus masters are preferably arbitrated through the
plurality of channels in the DMA controller. The arbiter in the DMA
controller further includes logic that performs an alternating priority
scheme based on the type of requestor for the ISA bus. Preferably, there
are two requestor types. The first requestor type includes the DMA
controller and ISA bus masters, and the second requestor type includes the
other devices, i.e., the EDMA controller, the refresh controller, and the
PCI bus masters. Once the first requestor type (DMA controller or ISA bus
master) gains control of the ISA bus, it loses access to the ISA bus in
the next arbitration cycle. This forces the DMA controller or ISA bus
masters to give up the ISA bus in the next arbitration cycle.
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention can be obtained when the
following detailed description of the preferred embodiment is considered
in conjunction with the following drawings, in which:
FIG. 1 is a block diagram of an exemplary computer system including
arbitration logic according to the present invention;
FIG. 2 is a block diagrams of a PCI-ISA bridge in the computer system of
FIG. 1 and incorporating arbitration logic according to the present
invention;
FIG. 3 is a block diagram of a PCI arbiter in the arbitration logic of FIG.
1;
FIG. 4 is a block diagram of the reservation and masking logic of the PCI
arbiter of FIG. 3;
FIGS. 5A and 5B are a schematic diagram of logic associated with the
reservation and masking logic of FIG. 4;
FIG. 6 is a state machine for tracking cycles to indicate when a retry has
occurred to prevent reprioritization;
FIG. 7 is a state machine for determining when a new master has been
granted the bus;
FIG. 8 is a schematic diagram of logic associated wish the state machine of
FIG. 7;
FIG. 9 is a schematic diagram of logic and circuitry associated with a
minimum grant timer associated with the PCI arbiter of FIG. 3;
FIG. 10 is a block diagram of the LRU arbiter in the PCI arbiter of FIG. 3;
FIGS. 11, 12 and 13 are schematic diagrams of circuitry associated with the
arbiter of FIG. 10.
FIG. 14 is a state diagram of a first retry state machine in the PCI
arbiter of FIG. 3;
FIG. 15 is a state diagram of an SD arbiter for arbitrating for the data
portion of the ISA expansion bus in the computer system of FIG. 1;
FIGS. 16A and 16B are a schematic diagram of logic in a DMA arbiter to
control access of the DMA controller and ISA I/O devices to the ISA bus;
FIG. 17 is a schematic diagram of flush request logic in the computer
system of FIG. 1; and
FIG. 18 is a state diagram of a state machine for monitoring requests from
bus masters on the ISA bus of FIG. 15.
FIG. 19 is a schematic diagram of write data buffers in the PCI-ISA bridge
of FIG. 2;
FIG. 20 is a schematic diagram of a read data buffer in the PCI-ISA bridge
of FIG. 2;
FIG. 21 is a schematic diagram of active and inactive timing registers
defining the DMA transfer timing;
FIG. 22 is a state diagram of an EDMA state machine for controlling write
and read DMA transfers;
FIGS. 23A and 23B are a schematic diagram of logic for interfacing with the
EDMA state machine of FIG. 22;
FIG. 24 is a state diagram of an IDE state machine for monitoring if the
improved DMA controller of FIG. 2 is in an idle, acknowledge, active or
inactive state; and
FIG. 25 is a state diagram of a state machine that controls the write
latching enable signals of the write data buffers of FIG. 19.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, an exemplary computer system S incorporating the
preferred embodiment of the present invention is shown. In the preferred
embodiment, the system board contains circuitry and slots for receiving
interchangeable circuit boards. In the preferred embodiment, there are two
primary buses located in the system S. The first bus is the PCI or
Peripheral Component Interconnect bus P which includes an address/data
portion and control signal portion. The second primary bus in the system S
is the ISA bus I. The ISA bus I includes an address portion, a data
portion and a control signal portion. The PCI and ISA buses P and I form
the backbones of the system S.
A CPU/memory subsystem 101 is connected to the PCI bus P. The processor or
CPU 100 is preferably the Pentium processor from Intel, preferably
operating at an external frequency of 66 MHz, but could be an 80486 from
Intel or processors compatible with the 80486 or Pentium or other
processors if desired. The processor 100 provides data, address and
control portions 102, 104, 106 to form a host bus HB. A level 2 (L2) or
external cache memory system 108 is connected to the host bus HB to
provide additional caching capabilities to improve performance of the
computer systems. The L2 cache 108 may be permanently installed or may be
removable if desired. A cache and memory controller and PCI bridge chip
110, such as the 82424 or 82434X chip from Intel Corporation or the chip
described in patent applications Ser. No. 08/324,016, entitled "SINGLE
BANK, MULTIPLE WAY CACHE MEMORY" and Ser. No. 08/324,246, entitled "MEMORY
CONTROLLER WITH WRITE POSTING QUEUES FOR PROCESSOR AND I/O BUS OPERATIONS
AND ORDERING LOGIC FOR CONTROLLING THE QUEUES", filed Oct. 14, 1994 and
hereby incorporated by reference, is connected to the control and address
portions of the PCI bus P. The bridge chip 110 is connected to the L2
cache 108 as it incorporates the cache controller and therefore controls
the operation of the cache memory devices in the L2 cache 108. The bridge
chip 110 is also connected to control a series of data buffers 112. The
data buffers 112 are preferably similar to the 82433LX from Intel, or
those described in patent applications Ser. Nos. 08/324,246 as
incorporated above and Ser. No. 08/323,263 entitled "DATA ERROR DETECTION
AND CORRECTION SYSTEM," filed Oct. 14, 1994 and hereby incorporated by
reference, and are utilized to handle memory data to a main memory array
114. The data buffers 112 are connected to the processor data portion 102
and receive control signals from the bridge chip 110. The data buffers 112
are also connected to the PCI bus P for data transfer over that bus. The
data buffers 112 provide a memory data bus 118 to the memory array 114,
while a memory address and memory control signal bus MB is provided from
the bridge chip 110.
A video controller 300 is connected to the PCI bus P. Video memory 304 is
used to store the graphics data and is connected to the video graphics
controller 300 and a digital/analog converter (RAMDAC) 306. The video
graphics controller 300 controls the operation of the video memory 304,
allowing data to be written and retrieved as required. A video connector
308 is connected to the RAMDAC 306. A monitor (not shown) is connected to
the video connector 308.
A network interface (NIC) controller 120 is connected to the PCI bus P.
Preferably the controller 120 is a single integrated circuit and includes
the capabilities necessary to act as a PCI bus master and slave and the
circuitry to act as an Ethernet interface. Alternate Ethernet connectors
124 are provided on the system S and are connected to filter and
transformer circuitry 126, which in turn is connected to the controller
120. This forms a network or Ethernet connection for connecting the system
boards and computer to a local area network (LAN).
A PCI-ISA bridge 130 is provided to convert signals between the PCI bus P
and the ISA bus I. The PCI-ISA bridge 130 includes the necessary address
and data buffers and latches, arbitration and bus master control logic for
the PCI bus, ISA arbitration circuitry, an ISA bus controller as
conventionally used in ISA systems, an enhanced DMA controller preferably
having two channels for interfacing with primary and secondary IDE devices
through connectors 133, and an 8237-compatible DMA controller. Preferably
the PCI-ISA bridge 130 is a single integrated circuit, but other
combinations are possible. To reduce the number of pins required for the
PCI-ISA bridge 130, the EDMA controller 204 (FIG. 2) shares the ISA SD or
data bus and the upper portion of the SA or address bus to perform data
transfers between the IDE devices and the main memory 114.
A series of ISA slots 134 are connected to the ISA bus I to receive ISA
adapter cards. A series of IDE slots 133 are connected to the ISA bus I
and the PCI-ISA bridge chip 130 to receive various IDE devices, such as
hard disk drives, tape drives and CD-ROM drives. A series of PCI slots 135
are connected to the PCI bus P to receive PCI adapter cards.
A combination I/O chip 136 is connected to the ISA bus I. The combination
I/O chip 136 preferably includes a floppy disk controller, real time clock
(RTC), CMOS memory, two UARTs, and various address decode logic. A floppy
disk connector 138 for receiving a cable to a floppy disk drive is
connected to the combination I/O chip 136 and the ISA bus I. Serial port
connectors 137 are also connected to the combination I/O chip 136. A data
buffer 144 is connected to the address, data and control portions of the
ISA bus I to provide an additional X bus for various additional components
of the computer system. A flash ROM 154 receives its control, data and
address signals from the X bus for data transfer.
Preferably the flash ROM 154 contains the BIOS information for the computer
system and can be reprogrammed to allow for revisions of the BIOS. An 8042
or keyboard controller 156 is connected to the X bus X. The keyboard
controller 156 is of conventional design and is connected in turn to a
keyboard connector 158 and a mouse or pointing device connector 160.
A miscellaneous system logic chip 132 is connected to the X bus X. The
miscellaneous system logic chip 132 contains counters and timers as
conventionally present in personal computer systems, an interrupt
controller for both the PCI and ISA buses P and I, enhanced parallel port
circuitry and power management logic, as well as other miscellaneous
circuitry.
This is an exemplary computer system S and other variations could readily
be developed by one skilled in the art.
Referring now to FIG. 2, various control blocks of the PCI-ISA bridge 130
are shown. The PCI-ISA bridge 130 includes a PCI interface 207, which
consists of PCI master logic 207 and a PCI slave logic 208. The PCI slave
logic 208 is responsible for monitoring the cycles on the PCI bus P and
determining when to respond to these cycles. The PCI-ISA bridge 130 is the
subtractive decode agent on the PCI bus, i.e., it responds as a PCI target
by asserting a signal DEVSEL, when no other PCI agent responds to the
cycle. As the target, the PCI-ISA bridge 130 passes the PCI cycles to the
ISA bus I. The PCI slave 208 also responds as a PCI target when it decodes
cycles to internal PCI configuration registers, I/O registers or interrupt
acknowledge I/O registers.
The PCI master logic 206 is responsible for running cycles on the PCI bus P
on behalf of ISA bus masters, a DMA controller 216, and the enhanced DMA
(EDMA) controller 204. On the PCI bus P, the PCI master logic 206 runs
memory and I/O read and write cycles. The PCI master logic 206 also
receives a request from the DMA controller 216 for the PCI bus P and in
response asserts a signal EREQ.sub.-- to a PCI arbiter 210. Similarly the
PCI master logic 206 generates EDMAREQ.sub.-- to the PCI arbiter 210 in
response to an IDE request from the EDMA controller 204.
The enhanced DMA or EDMA controller 204 includes state machines 250, 252
and 254 which are described below in FIGS. 22, 24 and 25. The EDMA
controller 204 also provides two channels in the preferred embodiment for
supporting primary IDE devices 230 and secondary IDE devices 232 connected
through connectors 133. Each channel is capable of supporting two devices
configured as a master and slave. The supportable devices include hard
disk drives, CD-ROMs, and tape drives. The IDE devices 230 and 232 are
connected to a data bus HD, which is coupled through bi-directional data
buffers 234 to the SD bus.
The control signals between the IDE devices 230 and 232 and the EDMA
controller 204 are signals IDE.sub.-- WR.sub.--, IDE.sub.-- RD.sub.--,
IDE.sub.-- DRQ.sub.-- P, IDE.sub.-- DRQ.sub.-- S, IDE.sub.-- DAK.sub.--
P.sub.-- and IDE.sub.-- DAK.sub.-- S . The write command strobe IDE.sub.--
WR.sub.-- is asserted by the EDMA controller 204 while a control byte or
data word is driven into the selected IDE device, and the command strobe
IDE.sub.-- RD.sub.-- is asserted when a status byte or data word is
retrieved from the selected IDE device. To begin a transfer operation with
an IDE device, the CPU 100 generates a parallel I/O command cycle on the
PCI bus P. The parallel I/O command is typically a read sector command or
a write sector command. The I/O command is transmitted to the ISA bus and
then to the selected IDE device. Each sector command involves the transfer
of 256 bytes of data. The CPU 100 then generates a second PCI I/O cycle to
write appropriate IDE control registers in the EDMA controller 204. There
are two IDE control registers in the EDMA controller 204, one for the
primary channel and one for the secondary channel. In the preferred
embodiment, the bits written in each control register are the mask bit and
the write/read bit. The mask bit indicates if the channel is masked, and
the write/read bit indicates a write or read operation. The mask bits and
write/read bits are described below in FIG. 23A. When the selected IDE
device is ready to begin the transfer, which usually takes a relatively
long time because of seek times, it asserts either of request signals
IDE.sub.-- DRQ.sub.-- P or IDE.sub.-- DRQ.sub.-- S depending on if the
primary or secondary channel is selected. In response, the EDMA controller
204 generates a request for the SD bus. Once the SD bus has been granted
to the EDMA controller 204, the appropriate one of the acknowledge signals
IDE.sub.-- DAK.sub.-- P.sub.-- and IDE.sub.-- DAK.sub.-- S.sub.-- is
asserted by the EDMA controller 204. Interrupt requests from the IDE
devices 230 and 232 are referred to as IRQ.sub.-- P and IRQ.sub.-- S and
are provided to the miscellaneous system logic chip 132.
Two levels of four-double-word write gathering buffers 209A and 209B and
one level of four-double-word read buffers 211 are provided in the PCI-ISA
bridge 130 for data transfers between the SD and PCI buses. During reads
of the IDE devices (EDMA writes to main memory 114), the EDMA controller
204 initiates a request for the PCI bus as soon as the first level
four-double-word write buffer 209A is full. The data in the first level
buffer 209A is then latched into the second level buffer 209B. Data
transfer from the IDE devices continues until the first level is again
full. This provides for a large latency period for the PCI master logic
206 to obtain control of the PCI bus P. During writes to the IDE devices
(or EDMA reads of the main memory 114), the EDMA controller 204 must pause
to obtain the next four-double-word of data upon completion of a read
transfer as there is only one stage of read buffers 211. Only one level of
read buffers is used in the preferred embodiment to reduce complexity in
the design of the EDMA controller 204. As there are more disk reads than
disk writes, with a variance of almost a 10-to-1 ratio, the benefits
conferred by using two four-double-word read buffers would be relatively
small.
As a result of the above features, it has been found that use of the EDMA
controller 204 according to the preferred embodiment reduces PCI bandwidth
utilization of up to 95% versus conventional 8237 DMA (with type B timing)
controllers for IDE data transfers.
For added flexibility, the timing for completing a data transfer, i.e., one
word out of the 256 bytes of data in a sector, by the EDMA controller 204
between the SD and PCI buses is also completely programmable, as fully
described below. The EDMA timing is programmable via configuration I/O
registers in the PCI-ISA bridge 130. This provides added advantages over
conventional 8237 DMA controllers, which allow for limited timing
selectibility between the ISA-compatible timing mode, Type A timing mode,
Type B timing mode, or Type C timing (or burst) mode.
The DMA controller 216 in the PCI-ISA bridge 130 includes seven channels,
each providing 24 bits of memory address. The DMA controller 216 presents
an 8-bit interface and is programmed with 8-bit I/O instructions. The DMA
controller 216 supports 8 or 16-bit DMA transfers to memory on the PCI bus
P and responds only to I/O devices on the ISA bus I. The DMA controller
216 is effectively equivalent to the conventional chained 8237 pair used
in conventional EISA computer systems.
The DMA controller 216 interfaces with an ISA bus controller 214, also on
the PCI-ISA bridge 130 in the preferred embodiment. The ISA bus controller
214 includes a refresh controller 215 for running refresh cycles on the
ISA bus I. The DMA interface in the ISA bus controller 214 translates
status signals provided by the DMA controller 216 into appropriate bus
cycles. The ISA bus controller 214 also includes other logic blocks,
including the PCI bus interface logic, address converting and sequencing
logic, data buffer control logic, and ISA bus master interface logic.
During cycles on the ISA bus I controlled by an ISA bus master, the ISA
bus controller 214 interprets control signals on the ISA bus I for
transmission to the PCI bus P. The ISA bus controller 214 also generates
ISA control signals during CPU and DMA cycles. During PCI cycles, the ISA
bus interface logic interprets signals from the PCI bus interface for
driving onto the ISA bus I.
The ISA bus interface logic determines the type of cycle being run from
three signals: EGNT.sub.-- which is driven by the PCI arbiter 210 to
indicate that the ISA bus I has control of the PCI bus P;, EMAST16.sub.--
which indicates a 16-bit ISA master has control of the ISA bus I; and
REFRESH.sub.-- which indicates a refresh cycle. If the signal EGNT.sub.--
is deasserted, then that indicates a PCI-to-ISA cycle. If the signals
EGNT.sub.-- and EMAST16.sub.-- are asserted low and the signal
REFRESH.sub.-- is deasserted high, then that indicates a 16-bit ISA bus
master has control of the ISA bus I. If the signal EGNT.sub.-- is asserted
and the signals REFRESH.sub.-- and EMAST16.sub.-- are deasserted, then
control of the ISA bus I is in the DMA controller 216. If the signals
EGNT.sub.-- and REFRESH.sub.-- are asserted, then an ISA bus master has
control of the ISA bus I and is providing a refresh cycle. If the signals
EGNT.sub.-- is deasserted and REFRESH.sub.-- is asserted, then the refresh
controller 215 has control of the ISA bus I. It is noted this cycle is not
propagated to the PCI bus P as refreshes on the ISA bus I by the refresh
controller 215 are hidden.
The arbitration scheme in the PCI-ISA bridge 130 is divided among three
logic blocks: the PCI arbiter 210, an SD arbiter 212, and an arbiter 218
in the DMA controller 216. The PCI arbiter 210 preferably supports a total
of seven masters: five external masters and two internal masters. The
external masters include four general purpose external PCI masters, such
as the video controller 300 and NIC 120, and the bridge chip 110. The two
internal masters are 1) the DMA controller 216 and 2) the EDMA controller
204. The PCI arbiter 210 implements a least-recently-used or LRU
prioritization scheme. The PCI-ISA bridge 130 itself does not have any
higher priority than any of the other PCI masters--its priority is
determined solely by the LRU algorithm except when the signal LOCK.sub.--
is asserted and a lock cycle is in progress on the PCI bus P, the signal
EGNT.sub.-- is masked until the locked cycle is completed.
As will be described below in more detail, the PCI arbiter 210 implements a
mechanism to minimize bus thrashing when a PCI master is retried by a
target. A target generates a retry to notify the PCI master that the
target is currently unable to complete the bus transaction. For additional
details on retry cycles, refer to the PCI Specification.
The SD arbiter 212 determines which device gets control of the SD or ISA
data bus. The SD arbiter 212 works in conjunction with the ISA | | |
