Distributed write data drivers for burst access memories

What is claimed is:

1. A memory device having a plurality of internal data line pairs, an equilibration control circuit and a write cycle control circuit, the memory device further comprising:

a plurality of data sense amplifiers each coupled to the equilibration control circuit, the write cycle control circuit and at least one of the data line pairs;

a plurality of write data drivers, each write data driver associated with at least one of said data sense amplifiers; and

a plurality of write data driver enable circuits, each write driver enable circuit associated with one of said write data drivers to enable said write data drivers to drive data onto at least one of the data line pairs in response to deassertion of an equilibrate signal from the equilibration control circuit while a write cycle enable signal from the write cycle control circuit is asserted.

2. The memory device of claim 1, further comprising:

a burst access control circuit adapted to receive an initial address in response to an access cycle strobe signal and to generate a series of addresses, each in response to a further transition of the access cycle strobe signal.

3. The memory device of claim 2, further comprising:

an output buffer coupled to at least one of said data sense amplifiers and to the access cycle strobe signal, said output buffer adapted to drive data from the memory device in response to a plurality of transitions of the access cycle strobe signal.

4. The memory device of claim 3, wherein the access cycle strobe signal is a column address strobe signal and the memory device is a burst extended data out dynamic random access memory device.

5. The memory device of claim 1, wherein the memory device is adapted to operate in an Extended Data Out page mode.

6. A memory device comprising:

a plurality of write data drivers comprising an enable input, a data input and a data output;

a plurality of data lines, each of said data lines coupled to the data output of at least one of said write data drivers; and

a plurality of write data driver enable circuits, each of said write data driver enable circuits adapted to receive a write cycle control signal and an equilibrate control signal, each of said write data driver enable circuits located in close proximity and coupled to the enable input of at least one of said write data drivers.

7. The memory device of claim 6, further comprising:

a plurality of data sense amplifiers, each of said data sense amplifiers being associated with one of the plurality of write data drivers.

8. The memory device of claim 7, further comprising:

a plurality of memory element subarrays, each of said subarrays coupled to at least one of said write data drivers by at least one of said data lines, and each of said subarrays coupled to at least one of said data sense amplifiers by at least one of said data lines.

9. The memory device of claim 8, further comprising:

a plurality of equilibration transistors, each of said equilibration transistors responsive to the equilibrate control signal to couple at least two of said data lines together.

10. The memory device of claim 9, wherein said write data drivers are disabled by said write data driver enable circuits while said equilibration transistors couple said data lines together.

11. A memory device comprising:

a memory element array region;

a plurality of data line pairs dispersed within said memory element array region; and

a plurality of write data drivers dispersed along an edge of said memory element array region, each comprising an equilibrate input, a write active input, a write data input and a write data output, each of said write data drivers adapted to drive a data signal from the write data input to at least one of said data line pairs.

12. The memory device of claim 11, further comprising:

a main logic region outside said array region, said main logic region comprising an equilibration control circuit adapted to provide an equilibrate signal to the equilibrate input of said write data drivers.

13. The memory device of claim 12, further comprising:

a pads and logic region outside said array region and outside said main logic region, wherein the equilibrate signal is routed from said main logic region through said pads and logic region to said write data drivers.

14. The memory device of claim 11, further comprising:

a main logic region outside said array region, said main logic region comprising a write cycle control circuit adapted to provide a write active signal to the write active input of said write data drivers.

15. The memory device of claim 14, further comprising:

a pads and logic region outside said array region and outside said main logic region, wherein the write active signal is routed from said main logic region through said pads and logic region to said write data drivers.

16. A memory device comprising:

a memory element array region;

a control circuit region, outside of said memory element array region, for generating memory control signals including an equilibrate signal and a write enable signal;

a plurality of data line pairs dispersed throughout said memory element array region;

a plurality of data sense amplifiers, said data sense amplifiers distributed along an edge of said memory element array region, each amplifier proximately located to at least one of said data line pairs; and

a distributed plurality of write data drivers each comprising an equilibrate inactive input enable responsive to the equilibrate signal and a write active input enable responsive to the write enable signal, each of said write data drivers proximately located to a data sense amplifier and associated with at least one of said data line pairs.

17. The memory device of claim 16, further comprising:

an address strobe input adapted to receive an address strobe signal; and

an address counter responsive to the address strobe signal to generate an address and to provide the address to said memory element array region.

18. A memory device comprising:

a data input;

a plurality of memory element subarrays; and

a plurality of data sense amplifiers coupled to said subarrays, each of said data sense amplifiers comprising a write data driver responsive to an active write enable signal and an inactive equilibration signal, to drive write data received on said data input to a corresponding one of said subarrays.

19. A method of storing data in a system comprising steps of:

providing a memory having a distributed plurality of data driver enable circuits;

addressing the memory;

providing data to the memory;

asserting an equilibration signal at the plurality of data driver enable circuits in response to said step of addressing;

asserting a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibration signal;

gating a write enable signal through at least one of the data driver enable circuits in response to said step of deasserting; and

storing data in a memory cell of the memory in response to said step of gating a write enable signal.

Description Submit all comments and votes

FIELD OF THE INVENTION

This invention relates to memory device architectures designed to provide high density data storage with high speed read and write access cycles. This invention relates more specifically to circuits and methods for controlling memory write cycles.

BACKGROUND OF THE INVENTION

There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low pulse occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS fails, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by the various DRAM manufacturers.

Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM) for example has an additional pin for receiving a system clock signal. Since the system clock is connected to each device in a memory system, it is highly loaded, and it is always toggling circuitry in every device. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin. Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.

It is desirable to design and manufacture a memory device having a standard DRAM pinout and a burst mode of operation where multiple data values can be sequentially written to or read from the device in response to a single address location and multiple access strobes. It is also desirable that this new memory device operate at higher frequencies than standard DRAMs.

There is a problem in performing write cycles at high frequencies. In standard Fast Page Mode and EDO mode DRAM devices, write cycles are performed in response to both /CAS and /WE being low after /RAS is low. If an address change occurs at approximately the same time that /CAS falls, then an additional delay is required to equilibrate input/output lines and to fire a new column prior to beginning the write cycle. Data to be written is latched, and the write cycle begins when the latter of /CAS and /WE goes low provided that the equilibrate is complete. Generally, the write time can be considered to be the period of time that /WE and /CAS are simultaneously low. However, in order to allow for maximum page mode operating frequencies, the write cycle is often timed out so that it can continue for a short period of time after /CAS or /WE goes high especially for "late write" cycles. Maintaining the write cycle throughout the time-out period eases the timing specifications for /CAS and /WE that the device user must meet, and reduces susceptibility to glitches on the control lines during a write cycle. The write cycle is terminated after the time out period, and if /WE is high a read access begins based on the address present on the address input lines. The read access will typically begin prior to the next /CAS falling edge so that the column address to data valid specification can be met (tAA). In order to begin the read cycle as soon as possible, it is desirable to minimize the write cycle time while guaranteeing completion of the write cycle. Minimizing the write cycle duration in turn minimizes the margin to some device operating parameters despite the speed at which the device is actually used. Circuits to model the time required to complete the write cycle typically provide an estimate of the time required to write an average memory cell. While it is desirable to minimize the write cycle time, it is also necessary to guarantee that enough time is allowed for the write to complete, so extra delay is added making the write cycle slightly longer than required.

Another aspect of controlling the write cycle timing includes delaying the write enable or write enables to guarantee that the write data drivers are not enabled prior to the completion of the equilibrate function. Equalization of internal data I/O lines is performed in response to column address transitions in preparation for reading or writing data from another memory cell, and also in response to receipt of a write command to reduce the maximum signal transition on the data lines once the write drivers are enabled. If the data lines are each equalized to one half of Vcc for example, then the write data drivers will only need to drive one line from half Vcc to ground, and the other from half Vcc to Vcc. Otherwise, if the write data is not equal to the data previously on the I/O lines, the write data drivers will need to drive both true and compliment I/O lines a full Vcc swing for each data bit being written. Equalization of the data I/O lines reduces the maximum write cycle time by eliminating the worst case signal swing conditions. A simple method of equilibrating the I/O lines is to: disable I/O line drivers; isolate the I/O lines from the digit lines; and couple complimentary I/O lines together. When a true I/O line is coupled to a complimentary I/O line, a logic high will be coupled to a logic low and each line will equalize to a potential approximately half way between a high and a low. It is important to disable the I/O line drivers during equilibration to prevent a true logic driver from being coupled to a complimentary logic driver which will draw excessive current from the logic high source to the logic low source.

Whether /CAS goes low last (early write) or /WE goes low last (late write), the column address will be valid at or before the write command is received. Hence, a delay from receipt of the write command which is greater than the equilibrate time will guarantee that an equilibrate due to a column address change is complete prior to the enabling the write drivers. If an equilibrate of internal data I/O lines is performed in response to receipt of each write command, a simple delay of the write enables will allow for the equilibrate to complete prior to enabling the write drivers. The delay value for the write cycle to write driver enable delay must account for the worst case signal delays from the equilibrate and write driver enable signal sources to the furthest data I/O line equilibrate devices and write data drivers. Since the equilibrate and write driver enable signal sources are located in a main logic area, a considerable signal propagation delay will result from the transmission of these signals across the chip to the furthest I/O line pair. Timing delays due to routing differences in the two signal paths can be very difficult to accurately model and predict. To overcome these difficulties, extra delay is added for timing margin. Unfortunately, this prevents the write drivers from being enabled as soon as the equilibrate function is complete.

Throughout the memory device product lifetime, manufacturing process advances and circuit enhancements often allow for increases in device operating frequencies. The write cycle timing circuits may need to be adjusted to shorten the minimum write cycle times to match these performance improvements. Adjustments may include shortening the equilibrate time, shortening the write cycle to write driver enable time and shortening the write cycle hold time. Fine tuning of these timing circuits is time consuming and costly. If the write cycles are too short, the device may fail under some or all operating conditions. If the write cycles are too long, the device may not be able to achieve the higher operating frequencies that are more profitable for the device manufacturers. Finally, if the equilibrate is not complete prior to enabling the write drivers, then excessive current may flow through the write drivers from Vcc to ground.

With the increased operating frequencies of burst access memory devices a new method of generating the write cycle timing is desired which will allow for maximum write cycle times despite the operating frequency of the device.

SUMMARY OF THE INVENTION

An integrated circuit memory device with a standard DRAM pinout is designed for high speed data access and for compatibility with existing memory systems. A high speed burst mode of operation is provided where multiple sequential accesses occur following a single column address, and read data is output relative to the /CAS control signal. In the burst mode of operation the address is incremented internal to the device eliminating the need for external address lines to switch at high frequencies. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at high speeds. Only one control line per memory chip (/CAS) must toggle at the operating frequency in order to clock the internal address counter and the data input/output latches. The load on each /CAS is typically less than the load on the other control signals (/RAS, /WE and /OE) since each /CAS typically controls only a byte width of the data bus.

A new write cycle timing method and circuit allow for maximized write cycle timing at all operating frequencies to provide maximum write cycle timing margins. Write control is maintained throughout a write cycle such that the write operation time approaches the write cycle time. The write function is only halted between write cycles for a period of time required to select a new column of the array and to equilibrate I/O lines in the array. To maximize write cycle times, a logic device is located near the sense amplifiers of the device to control the write function directly with the use of the I/O line equilibrate signal. It is important to disable the write drivers during the equilibrate time to prevent current flow through the true and compliment data drivers while the I/O lines are coupled together. The local write enable circuit allows the write cycle time to be essentially equal to the access cycle time minus the I/O line equilibrate time in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention as well as objects and advantages are best understood by reference to the appended claims, detailed description of particular embodiments and accompanying drawings where:

FIG. 1 is an electrical schematic diagram of a memory device in accordance with one embodiment of the invention;

FIG. 2 is a timing diagram for a method of accessing the device of FIG. 1;

FIG. 3 is a top view of a general device layout for a device designed in accordance with the teachings of the present invention;

FIG. 4 is block level schematic of a data path portion of the device of FIG. 3;

FIG. 5 is a more detailed schematic of a portion of the circuitry of FIG. 4; and

FIG. 6 is a schematic diagram of a computer system designed in accordance with the teachings of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a schematic representation of a sixteen megabit device designed in accordance with the present invention. The device is organized as a 2 Meg.times.8 burst EDO DRAM having an eight bit data input/output path 10 providing data storage for 2,097,152 bytes of information in the memory array 12. The device of FIG. 1 has an industry standard pinout for eight bit wide EDO DRAMs. An active-low row address strobe (/RAS) signal 14 is used to latch a first portion of a multiplexed memory address, from address inputs A0 through A10 16, in latch 18. The latched row address 20 is decoded in row decoder 22. The decoded row address is used to select a row of the memory array 12. A column address strobe (/CAS) signal 24 is used to latch a second portion of a memory address from address inputs 16 into column address counter 26. The latched column address 28 is decoded in column address decoder 30. The decoded column address is used to select a column of the memory array 12.

In a burst read cycle, data within the memory array located at the row and column address selected by the row and column address decoders is read out of the memory array and sent along data path 32 to output latches 34. Data 10 driven from the burst EDO DRAM may be latched external to the device in synchronization with /CAS after a predetermined number of /CAS cycle delays (latency). For a two cycle latency design, the first /CAS falling edge is used to latch the initial address for the burst access. The first burst data from the memory is driven from the memory after the second /CAS falling edge, and remains valid through the third /CAS falling edge. Once the memory device begins to output data in a burst read cycle, the output drivers 34 continue to drive the data lines without tri-stating the data outputs during /CAS high intervals dependent on the state of the output enable and write enable (/OE and /WE) control lines, thus allowing additional time for the system to latch the output data. Once a row and a column address are selected, additional transitions of the /CAS signal are used to advance the column address within the column address counter in a predetermined sequence. The time at which data becomes valid at the outputs of the burst EDO DRAM is dependent only on the timing of the /CAS signal provided that /OE is maintained low, and /WE remains high. The output data signal levels may be driven in accordance with, but are not limited to, CMOS, TTL, LVTTL, GTL, or HSTL output level specifications.

The address may be advanced linearly, or in an interleaved fashion for maximum compatibility with the overall system requirements. The column address may be advanced with each /CAS transition, each pulse, or multiple of /CAS pulses in the event that more than one data word is read from the array with each column address. When the address is advanced with each transition of the /CAS signal, data is also driven from the part after each transition following the device latency which is then referenced to each edge of the /CAS signal. This allows for a burst access cycle where the highest switching control line (/CAS) toggles only once (high to low or low to high) for each memory cycle. This is in contrast to standard DRAMs which require /CAS to go low and then high for each cycle, and synchronous DRAMs which require a full clock cycle (high and low transitions) for each memory cycle. For maximum compatibility with existing EDO DRAM devices, the invention will be further described in reference to a device designed to initiate access cycles on falling edges of the /CAS signal. For designs where falling edges of the /CAS signal initiate an access cycle, the falling edge may be said to be the active transition of the /CAS signal.

It may be desirable to latch and increment the column address after the first /CAS falling edge in order to apply both the latched and incremented addresses to the array at the earliest opportunity in an access cycle. For example, a device may be designed to access two data words per cycle (prefetch architecture). The memory array for a prefetch architecture device may be split into odd and even array halves. The column address least significant bit is used to select between odd and even halves while the other column address bits select a column within each of the array halves. In an interleaved access mode with column address 1, data from columns 0 and 1 are read and the data from column 1 is output followed by the data from column 0 in accordance with standard interleaved addressing as described in SDRAM specifications. In a linear access mode column address 1 is applied to the odd array half, and incremented to address 2 for accessing the even array half to fulfill the two word access. One method of implementing this type of device architecture is to provide a column address incrementing circuit between the column address counter and the even array half. The incrementing circuit increments the column address only if the initial column address in a burst access cycle is odd, and the address mode is linear. Otherwise the incrementing circuit passes the column address unaltered. For a design using a prefetch of two data accesses per cycle, the column address is advanced once for every two active edges of the /CAS signal. In a write cycle, multiple data words may be temporarily stored as they are input to the device. The actual write of data to the memory cells occurs after the last input data is latched, and may extend slightly into the next memory cycle as long as it ends prior to the next column being activated. Prefetch architectures where more than two data words are accessed are also possible.

Other memory architectures applicable to the current invention include a pipelined architecture where memory accesses are performed sequentially, but each access requires more than a single cycle to complete. In a pipelined architecture the overall throughput of the memory approaches one access per cycle, but the data out of the memory is offset by a number of cycles equal to the pipeline length and/or the desired latency from /CAS.

In the burst access memory device, each new column address from the column address counter is decoded and is used to access additional data within the memory array without the requirement of additional column addresses being specified on the address inputs 16. This burst sequence of data continues for each /CAS falling edge until a predetermined number of data accesses equal to the burst length occurs. A /CAS falling edge received after the last burst address has been generated latches another column address from the address inputs 16 and a new burst sequence begins. Read data is latched and output with each falling edge of /CAS after the first /CAS latency.

For a burst write cycle, data 10 is latched in input data latches 34. Data targeted at the first address specified by the row and column addresses is latched with the /CAS signal when the first column address is latched (write cycle data latency is zero). Other write cycle data latency values are possible; however, for today's memory systems, zero is preferred. Additional input data words for storage at incremented column address locations are latched by /CAS on successive /CAS active transitions. Input data from the input latches 34 is passed along data path 32 to the memory array where it is stored at the location selected by the row and column address decoders. As in the burst read cycle previously described, a predetermined number of burst access writes are performed without the requirement of additional column addresses being provided on the address lines 16. After the predetermined number of burst writes occur, a subsequent /CAS pulse latches a new beginning column address, and another burst read or write access begins.

The memory device of FIG. 1 may include the option of switching between burst EDO and standard EDO modes of operation. In this case, the write enable signal /WE 36 is used at the row address latch time (/RAS falling, /CAS high) to determine whether memory accesses for that row are burst or page mode cycles. If /WE is low when /RAS falls, burst access cycles are selected. If /WE is high at /RAS falling, standard extended data out (EDO) page mode cycles are selected. Both the burst and EDO page mode cycles allow for increased memory device operating frequencies by not requiring the data output drivers 34 to place the data lines 10 in a high impedance state between data read cycles while /RAS is low. DRAM control circuitry 38, in addition to performing standard DRAM control functions, controls the I/O circuitry 34 and the column address counter/latch 26 in accordance with the mode selected by /WE when /RAS falls. In a burst mode only DRAM, or in a device designed with an alternate method of switching between burst and non-burst access cycles, the state of /WE when /RAS falls may be used to switch between other possible modes of operation such as interleaved versus linear addressing modes.

The write enable signal is used in burst access cycles to select read or write burst accesses when the initial column address for a burst cycle is latched by /CAS. /WE low at the column address latch time selects a burst write access. /WE high at the column address latch time selects a burst read access. The level of the /WE signal must remain high for read and low for write burst accesses throughout the burst access. A low to high transition within a burst write access terminates the burst access, preventing further writes from occurring. A high to low transition on /WE within a burst read access likewise terminates the burst read access and places the data output 10 in a high impedance state. Transitions of the /WE signal may be locked out during critical timing periods within an access cycle in order to reduce the possibility of triggering a false write cycle, and/or to guarantee the completion of a write cycle once it has begun. After the critical timing period the state of /WE determines whether a burst access continues, is initiated, or is terminated. Termination of a burst access places the DRAM in a state to rec