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Description  |
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BACKGROUND
The present invention pertains to computer networks, and more particularly,
to a method of transferring data at 100 Mb/s transfer rates over local
area networks (LAN's) using unshielded twisted pair (UTP) wire media.
In the world of computers, pc and workstation users are requiring greater
network bandwidths/higher speeds to carry more and more data over existing
networks. The need for higher speed networks will grow even faster as
desktop computers are equipped with the higher speed bus architectures
that are being developed. Over the past ten years, desktop pc processing
power has increased over a hundredfold. Over that same period, however,
the data transmission speed of Ethernet LAN's has remained constant at 10
Mb/s. Network speeds are now a common bottleneck in a variety of key
business application areas including database management, imaging,
computer-aided design and network printing. On a typical 10 Mb/s Ethernet
or Token-Ring network, it can take as long as 20 seconds to retrieve a
single page of data depending upon network traffic. If 100 Mb/s networks
were available, transfers would not be network limited and would take only
one or two seconds for that same page of data.
Generally, for high speed data transfer in excess of 25 Mb/s over a LAN,
data has been transferred using fiber optic media, coaxial cable, shielded
wire or other specialized cable. For example, the fiber distributed data
interface (FDDI) protocol is a common network protocol which operates
using a fiber optic medium. FDDI has been available the longest of any
high speed (100 Mb/s) network architecture, but it is still the costliest.
Very few business users of computers have installed fiber optic cabling.
In the United States it is estimated that approximately 80% of existing
LAN users have "category 3" (voice grade) unshielded twisted pair wiring
to interconnect desktop users. Such cables are usually configured in
25-pair bundles to accommodate future organizational growth.
The use of fiber optic media or shielded twisted pair (STP) wire for local
area networking present various problems of their own. Most existing
office buildings have an installed base of UTP wiring--not fiber optic
cable or STP wire. Therefore, to utilize a fiber optic or STP network,
assuming existing cable ducts have the space available, it would be
necessary to specially install high quality cabling. This can be cost
prohibitive. Yet if a LAN could be designed to operate at speeds of 100
Mb/s and work over Category 3 to Category 5 (data grade) UTP wire, users
could easily switch to the higher speed network interface equipment using
the existing cabling installation.
There has been some work done to increase the rate over which data can be
transferred over installed twisted pair cabling. See for example U.S. Pat.
No. 5,119,402 issued to Simon A. Ginzburg et al. for a Method and
Apparatus for Transmission of Local Area Network Signals over Unshielded
Twisted Pairs. However, in the prior art there has been no work which has
sufficiently increased the speed of data transmission so that transmission
over a four pair voice grade UTP wire network can rival the speed of data
transmissions over fiber optic cabling. Some of the reasons for this are
obvious. Unlike fiber optic cable or STP wire, UTP wire has greater
radio-frequency (rf) emissions since it is unshielded. And, because the
twist of the wire pairs does not provide perfect balance, there are also
crosstalk and noise interference problems. And as speeds increase above 10
Mb/s these problems are exacerbated along with-high frequency rolloff
causing signal distortion that increases with the length of the wire runs.
Yet, given these problems there are various proposals for new network
topologies to send data over UTP wire at transmission rates of 100 Mb/s;
the present invention represents the heart of one of those proposals. And,
although the present invention could easily be adapted to operate over
higher quality cable, such as STP, it has its greatest utility (in terms
of economy) for existing UTP wired facilities.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a method is
provided for transmitting data packets, grouped as data octets, over a LAN
having a central hub linked to each of a plurality of network nodes via a
physical medium consisting of four pairs of unshielded twisted pair (UTP)
cable. The transmission method initially divides the data octets
sequentially into 5-bit data quintets. The quintets are then sequentially
distributed into four individual serial code streams. The four serial code
streams are sequentially scrambled to produce four streams of randomized
5-bit quintets. The randomized data streams are sequentially block encoded
into 6-bit symbol data which are then transmitted across the network by
transmitting each data stream over one of said pairs of cable.
In the preferred embodiment, before the 6-bit symbol data is transmitted
across the network, the data on two of the cable pairs is staggered (in
time) by at least two data bits for various reasons including to increase
the noise immunity of the transmission across the channel.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention as well as further features
thereof, reference is made to the accompanying drawings wherein:
FIG. 1 shows a simplified block diagram of the interconnection of various
networks.
FIG. 2 shows a simplified block diagram of a network in accordance with a
preferred embodiment of the present invention.
FIG. 3 shows a simplified block diagram of a network device of the network
shown in FIG. 2.
FIG. 3A is a block diagram which shows logical flow of information within
the network device shown in FIG. 3.
FIG. 4 shows a simplified block diagram of the hub of the network shown in
FIG. 2.
FIG. 5 shows a simplified block diagram of a transceiver within the hub
shown in FIG. 4.
FIG. 6 shows a simplified block diagram of a repeater within the Mb shown
in FIG. 4 in accordance with the preferred embodiment of the present
invention.
FIG. 7 is a state diagram for a repeater state machine within the repeater
shown in FIG. 6.
FIG. 8 is a state diagram for a training state machine within the repeater
shown in FIG. 6.
FIG. 9 is a state diagram for a client state machine within the network
device shown in FIG. 3A.
FIG. 10 is a state diagram for a client training state machine within the
network device shown in FIG. 3A.
FIG. 11 is an example of a filter design which may be used the hub shown in
FIG. 4 and the network device shown in FIG. 3.
FIG. 12 shows logic blocks within a network interface which prepare data to
be forwarded to a hub in accordance with the preferred embodiment of the
present invention.
FIG. 13 shows a diagram which explains data flow within the logic blocks
shown in FIG. 12.
FIG. 14 is a timing diagram showing the timing of signals through a group
of four twisted pair wires in accordance with a preferred embodiment of
the present invention.
FIG. 15 is a block diagram of a circuit which facilitates collision
detection in a network in accordance with a preferred embodiment of the
present invention.
FIGS. 16 and 17 show potential frequency spectrums for signals sent across
a twisted pair shown in FIG. 15.
FIG. 18 shows a block diagram of a circuit which provides common-mode
collision signaling in a network.
FIG. 19 shows a block diagram of a circuit which provides in-band collision
signaling in a network.
FIG. 20 is a block diagram which shows how the implementation circuit in
FIG. 15 or the circuit shown in FIG. 18 may be used in a network where a
network device sends data to a network device over four twisted wire
pairs.
FIG. 21 shows a hub connected to network nodes through four twisted wire
pairs.
FIG. 22 shows an example of signal timing within a network.
FIG. 23 shows an example of signal timing within a network.
FIG. 24 shows a hub connected to network nodes in a system where there is a
collision window before each packet transmission.
DETAILED DESCRIPTION
FIG. 1 shows a simplified block diagram of a typical network structure. A
LAN 11, a LAN 12 and a LAN 13 are connected, for example, through a
bridge/router (not shown in FIG. 1) to network 10. Network 10 operates,
for example, using the fiber distributed data interface (FDDI) protocol.
LAN 11 and LAN 13, may operate, in accordance with any number of
protocols. For example, if connected through a router, these LANs could
operate in accordance with the IEEE 802.3 protocol, with the Token Ring
protocol, with ISDN protocol or with a WAN protocol.
Various network devices, also referred to as end nodes, may be connected to
the LANs. For example, a network device 14 and a network device 15 are
shown connected to LAN 11. Network devices 16, 17 and 18 are shown
connected to LAN 12. Network devices 19, 20 and 21 are shown connected to
LAN 13. Network devices 14 through 21 may be, for example, a work station,
a personal computer, a network server, or some other device.
FIG. 2 shows a block diagram of LAN 12 which includes a hub 30. Hub 30 is
an intelligent central controller that manages data from the various
network devices connected to the hub. Hub 30 is connected to network
device 16 through four twisted-pairs of copper cable 31. Hub 30 is also
connected to each network device 17 and 18 through four twisted pairs or
copper cable 32 and 33 respectively.
FIG. 3 shows a simplified block diagram of a network interface 41, which is
used by each of network devices 16, 17 and 18 to interface with hub 30. A
backplane interface 42 provides an interface between computer system RAM
and the network device. A random access memory (RAM) 43 is used to
temporarily store data packets received from or to be transferred out on
the network. A media access controller (MAC) 44 is used to control the
flow of data within network interface 41. A transceiver 45 is used to send
and receive through the network. A transformer and filter 46 is used to
adjust voltage and provide noise filtering for signals transferred between
transceiver 45 and a connector 47. A connector 47 is connected to the
bundle of four UTP wires from hub 30.
FIG. 3A is a block diagram which shows logical flow of information within
network interface (client) 41. A client-training-state machine 501 is used
in initializing the connection between network device 41 and hub 30.
(Although the function is explained below in greater detail, "training" is
the initialization process that verifies the operation of the link and
optimizes the circuitry for data transmission and reception.) A
client-state machine 502 controls data transactions between network device
41 and hub 30. A DMA controller 503 controls DMA transfers between RAM 43
and a data buffer 504. Twisted pair transmit logic 505 forwards data to
transceiver 45 via path 513. Twisted pair receive logic 506 receives data
from transceiver 45 via path 514.
Control signals flow from DMA controller 503 to RAM 43 through an
information channel 507. Control signals also flow from DMA controller 503
to data buffer 504 through another information channel 510. Data signals
flow between data buffer 504 and RAM 43 through another information
channel 508. DMA controller 503'signals client-state machine 502 through
information channel 509 when there is a packet to transmit. Data buffer
504 sends data to twisted pair transmit logic 505 through information
channel 511. Data buffer 504 receives data signals from twisted pair
receive logic 506 through information channel 512. Transceiver 45 receives
data from twisted pair transmit logic 505 through information channel 513.
Transceiver 45 also sends data to twisted pair receive logic 506 through
information channel 514. Twisted pair receive logic 506 signals
client-state machine 502 through an information channel 515 at the start
of a packet and at the end of a packet (RXDONE). Client-state machine 502
signals twisted pair receive logic 506 through an information channel 516
when a packet is to be received. Twisted pair transmit logic 505 signals
client-state machine 502 through an information channel 517 when a
transmit is complete. Client-state machine 502 signals
twisted-pair-transmit logic 505 through an information channel 518 when a
packet is to be transmitted.
FIG. 4 shows a block diagram of hub 30 which manages the network access. A
backbone physical interface 51 provides a physical interface of hub 30 to
network 10. A backbone media access controller (MAC) 52 controls data flow
between hub 30 and network 10. A bridge buffer RAM 53 provides temporary
storage for data (packets) flowing between hub 30 and network 10. A
repeater 57 directs data flow on LAN 12. A content addressable memory
(CAM) 54 is addressable with a network address and outputs an associated
port. A broadcast SRAM 56 is used for temporary storage of multi-port
messages which are to be broadcast across LAN 12.
A network management subsystem 58 provides network management. Network
management subsystem 58 includes a processor 60, an EPROM 62, a RAM 61 and
a memory access controller (MAC) 59. EPROM 62 stores program information
used by processor 60. RAM 61 stores programs used by processor 60. MAC 59
provides a means for processor 60 to communicate with other nodes on the
network.
A transceiver 63 is used to send and receive data to and from a network
device (node) connected to a connector 67. A transceiver 64 is used to
send and receive data to and from a network device connected to a
connector 68. A transceiver 65 is used to send and receive data to and
from a network device connected to a connector 69. A transceiver 66 is
used to send and receive data to and from a network device connected to a
connector 70. While only transceivers 63 through 66 and connectors 67
through 70 are shown, many more transceivers and connectors can be added.
For example, in the preferred embodiment of the present invention, the hub
has 24 ports. A transformer/filter 73 connects transceiver 63 to connector
67. A transformer/filter 74 connects transceiver 64 to connector 68. A
transformer/filter 75 connects transceiver 65 to connector 69. A
transformer/filter 76 connects transceiver 66 to connector 70.
FIG. 5 shows a block diagram of transceiver 63. Transceiver 63 is connected
to connector 67 through four UTP wire pairs. The first pair includes a
connector line 81 and 82 (FIG. 5B). The second wire pair includes a
connector line 83 and 84. The third wire pair includes a connector line 85
and 86. The fourth wire pair includes a connector line 87 and 88. When
transceiver 63 receives the four streams of data over the four pairs
(81-88), the data is received by equalizer circuits 91-94 whose function
is to compensate for the insertion loss variations of the path with
frequency (i.e., rolloff). Each of equalization circuits 91 through 94
ideally provides a clean and amplified signal. In addition, equalization
circuit 91 also provides a carrier detector signal on a carrier detector
line 180.
A phase locked loop (PLL) clock and data recovery circuit 101 receives a
clean and amplified signal on line 181 and 182. PLL clock and data
recovery provides a data signal on a line 171, a clock signal on a line
175 and a clock valid signal on a line 279. A PLL clock and data recovery
circuit 102 receives a clean and amplified signal on line 183 and 184. PLL
clock and data recovery provides a data signal on a line 172, a clock
signal on a line 176 and a clock valid signal on a line 280. A PLL clock
and data recovery circuit 103 receives a clean and amplified signal on
line 185 and 186. PLL clock and data recovery provides a data signal on a
line 173, a clock signal on a line 177 and a clock valid signal on a line
281. A PLL clock and data recovery circuit 104 receives a clean and
amplified signal on line 187 and 188. PLL clock and data recovery provides
a data signal on a line 174, a clock signal on a line 178 and a clock
valid signal on a line 282.
Referring to FIG. 5A, elasticity buffers 111, 112, 113 and 114 synchronize
the data signals from PLL clock and data recovery circuits 101-104 to a
single clock. Elasticity buffer 111 receives the data signal and clock
signal from PLL clock and data recovery circuit 101 and produces a
synchronized data signal on line 191. Elasticity buffer 112 receives the
data signal and clock signal from PLL clock and data recovery circuit 102
and produces a synchronized data signal on line 192. Elasticity buffer 113
receives the data signal and clock signal from PLL clock and data recovery
circuit 103 and produces a synchronized data signal on line 193.
Elasticity buffer 114 receives the data signal and clock signal from PLL
clock and data recovery circuit 104 and produces a synchronized data
signal on line 194.
A logic OR gate 170 receives the clock signal on line 175, the clock valid
signal on line 279, the clock valid signal on line 280, the clock valid
signal on line 281 and the clock valid signal on line 282. OR gate 170
produces a clock signal (Clk 0) on line 190. The Clk 0 signal passes
through OR gate 170 when the four clock valid signals are asserted low.
Driver buffer 106 forwards data to repeater 57 on a line 126, a line 127,
a line 128 and a line 129. Driver 106 also provides a clock signal on a
line 129. Receive line state logic 105 is used to receive and forward
transfer set-up requests over the first and the second twisted wire pairs.
Receive line state logic 105 receives the carrier detector signal on
carrier detector line 180, the data signal on line 171, the data signal on
line 172 and the clock signal on line 175. Receive line state logic 105
produces a priority (PRI) request signal on line 121, a receive line state
signal (RLS0) on line 122, a receive line state signal (RLS1) on line 123,
and a receive line state signal (RLS2) on line 124 for forwarding to
repeater 57. Repeater enables receive line state logic 105 by placing a
receive line state enable signal on a line 125. A receiver enable signal
(RXEN) is generated by repeater 57 to select receive line state logic 105
or driver buffer 106 to forward information to repeater 57.
Referring to FIG. 4, when transceiver 63 transmits data to repeater 57, it
places a first data signal (TDATA0) on transmit data line 137 (in FIG.
5A), a second data signal (TDATA1) on transmit data line 138, a third data
signal (TDATA2) on transmit data line 139 and a fourth data signal
(TDATA3) on transmit data line 140. When transceiver 63 transmits control
signals to repeater 57, it places a first transmit line signal (TLS0) on
line 132, a second transmit line signal (TLS1) on a line 133, a third
transmit line signal (TLS2) on a line 134, and a transmit line clock
(TLSCK) on a line 135. TLSCK is used to store the TLS values. Transmit
line state logic 115 generates tones and drives the TLS values to be
forwarded to a multiplexer/transmitter 116.
Multiplexer/transmitter 116 (FIG. 5A), in response to a transmit enable
signal (TXEN) on a line 136, selects either data signals on lines 137,
138, 139 and 140 to be forwarded to the four twisted wire pairs 81 through
88, or the tones and driver enables from transmit line state logic to be
forwarded to the third and fourth twisted wire pairs 85 through 88. A
transmitter clock (TXCLK) is provided to transmit line state logic 115 and
multiplexer transmitter 116 on a line 141.
FIG. 6 is a block diagram showing data flow within repeater 57. Repeater 57
essentially functions to channel transferred data. Twisted pair receive
logic 212 receives data and control signals from the transceivers, e.g.,
transceivers 63, 64, 65 and 66. For example, twisted pair receive logic
212 is connected to lines 121 through 131 of transceiver 63. Broadcast RAM
readback logic 211 receives data from broadcast SRAM 56. Backbone receive
logic receives data from bridge buffer RAM 53.
Twisted pair transmit logic 220 sends data and control signals to the
transceivers, e.g., transceivers 63, 64, 65 and 66. For example, twisted
pair transmit logic 220 is connected to lines 132 through 141 of
transceiver 63. Broadcast write logic 219 sends data to broadcast SRAM 56.
Backbone transmit logic sends data to bridge buffer RAM 53.
The data received by twisted pair receive logic 212, broadcast RAM
read-back logic 211 and backbone receive logic 210 is channeled through a
first-in-first-out (FIFO) buffer 215 to either backbone transmit logic
218, broadcast write logic 219 or twisted pair transmit logic 220. FIFO
buffer 215 also provides arbitration information to a receiver port
arbiter 214.
Receiver port arbiter 214 selects from which port to receive a data
transmission. In general, a simple arbitration scheme is used. For
example, a round robin arbitration scheme may be used in which the last
port from which a data transmission is received is given lowest priority.
A transmit arbiter 217 determines to which port of backbone transmit logic
218, broadcast logic write logic 219 or twisted pair transit logic 220
data is to be transmitted. Transmit arbiter 217 determines where to send a
message by forwarding a network address of the message to CAM 54. CAM 54
returns a port number to transmit arbiter 217. Repeater 57 also includes a
repeater state machine 216 and a training state machine 213.
FIG. 7 shows a state diagram for repeater state machine 216. After start-up
of the repeater and training of all ports (as explained below) has taken
place, repeater state machine 216 is in idle state 231. Upon receiving a
request for transfer from receiver port arbiter 214, repeater state
machine enters an acknowledge port state 232. When repeater state machine
216 is in the acknowledge port state, repeater 57 sends an acknowledge
signal to the port which was selected by receiver port arbiter 214. If
repeater 57 times out before it begins to receive a data packet from the
selected port, repeater state machine 216 enters a set retrain port state
239. In set retrain port state 239, repeater state machine 216 signals
training state machine 213, to retrain the port. Repeater state machine
216 then returns to idle state 231.
From acknowledge port state 232, upon repeater 57 beginning to receive a
network data packet, repeater state machine 216 enters a determine
destination state 233. While repeater state machine 216 is in determine
destination state 233, transmit arbiter 217 determines where to send a
message by forwarding the network address in the network data packet to
CAM 54. CAM 54 returns a port number to transmit arbiter 217.
If transmit arbiter 217 determines the destination is to a port within
local network 12, repeater state machine 216 enters a transmit to port
state 235. In transmit to port state 235, data as it is received from the
port selected by receive port arbiter 214 is forwarded immediately to the
port selected by transmit arbiter 217. Upon repeater 57 receiving the
complete network data packet and completion of the forwarding of the data,
repeater state machine 216 returns to idle state 231. If the complete data
packet is not received within a specified time, repeater state machine 216
enters set retrain port state 239.
In determine destination state 233, if transmit arbiter 217 determines the
destination is to multiple ports within local network 12, repeater state
machine 216 enters a buffer to local RAM state 237. In buffer to local RAM
state 237, data as it is received from the port selected by receive port
arbiter 214 is forwarded to broadcast SRAM 56. Ira complete data packet is
not received within a specified time, repeater state machine 216 enters
set retrain port state 239. Upon repeater 57 receiving the complete
network data packet and completion of the forwarding of the data to
broadcast SRAM 56, repeater state machine 216 enters a transmit to all
ports state 238. In transmit to all ports state 238, repeater 57 reads the
broadcast message in broadcast SRAM 56 and forwards the message to each of
the ports specified. Upon completion of the data transmissions, repeater
state machine 216 returns to idle state 231.
In determine destination state 233, if transmit arbiter 217 determines the
destination is to the backbone of local network 12, repeater state machine
216 enters a buffer to bridge state 234. In buffer to bridge state 234,
data as it is received from the port selected by receive port arbiter 214
is forwarded to bridge buffer RAM 53. If a complete data packet is not
received within a specified time, repeater state machine 216 enters set
retrain port state 239. Upon repeater 57 receiving the complete network
data packet and completion of the forwarding of the data to buffer RAM 53,
repeater state machine 216 returns to idle state 231. If buffer RAM 53
runs out of available memory locations before completion of the transfer
of the network data packet, repeater state machine 216 enters a set busy
signal state 236. In set busy signal state 236, repeater 57 sends a busy
signal to the transmitting data port and throws away the network data
packet. Upon completion of the transfer of the network data packet to
repeater 57, repeater state machine 216 returns to idle state 231.
FIG. 8 is a state diagram for the training state machine 213 shown in FIG.
6. After a reset or whenever it is necessary to train a port, training
state machine 213 proceeds through the training states. Before training a
port, training state machine 213 is in an idle state 241. When the
training state machine 213 receives a training idle up signal from a port
which requests training, the training state machine 213 enters a
drive-T-idle (training idle)-down state 242. In drive-T-idle-down state
242, repeater 57 sends a training idle down signal to the port requesting
training.
Upon receiving a request-to-transmit signal from the port to be trained,
training state machine 213 enters a request-to-repeater state machine
state 243. In request-to-repeater-state-machine state 243, training state
machine 213 waits for repeater state machine 216 to acknowledge the port
to be trained. Upon repeater state machine 216 providing the
acknowledgment, training state machine 213 enters an acknowledge client
state 244. In acknowledge-client state 244, training state machine 213
waits for the port to start sending a training packet.
Upon the port starting to send a packet, training state machine 213 enters
a receive training packet state 245. In receive-training-packet state 245,
training state machine 213 waits for completion of the sending of the
training packet. When the training packet has been received, training
state machine 213 enters a training completion state 246. In the training
completion state 246, a check is done to see whether receive training is
complete. For example, in the preferred embodiment, training is complete
if 25 consecutive training packets have been received without errors. If
there are errors in reception, the equalization and clock frequencies are
adjusted in the transceiver for the port. If receive training is not
complete, training state machine 213 returns to drive T-idle-down-state
242.
When receive training is complete, training state machine 213 enters a
request-to-repeater-arbiter state 247. In request-to-repeater-arbiter
state 247, training state machine 213 requests transmit arbiter 217 to
initiate the transmission of a training packet to the port being trained.
Upon receiving an acknowledgment from repeater state machine 216, training
state machine 213 enters a transmit-training-packet state 248. Upon
completion of the transmission of the transmit-training-packet state,
training state machine 213 enters a training complete state 249. If
transmit training is not complete, training state machine 213 returns to
request-to-repeater-arbiter state 247.
When transmit training is complete, training state machine 213 enters line
idle state 250. Training state machine 213 remains in line idle state 250
during normal operation of the port. When the port requests retraining,
training state machine 213 returns to drive-training-idle-down state 242.
FIG. 9 shows a state diagram for client-state machine 502 (FIG. 3A).
Client-state machine 502 is initially in an idle state 251. When hub 30
signals that a packet will be incoming to the client, client-state machine
502 enters a wait-for-packet state 252. In wait-for-packet state 252, if
the client sees the receive line state transition to a state other than
incoming, such as idle, client-state machine 502 returns to idle state
251. Upon the client beginning to receive a packet, client-state machine
502 enters a receive-packet state 253.
In the receive-packet state 253, client-state machine 502 waits for the end
of the packet to be received. When the end of the packet is received and
client-state machine 502 is not waiting on a busy signal, client-state
machine 502 returns to idle state 251. When the end of the packet is
received and client-state machine 502 is waiting on a busy signal,
client-state machine 502 enters a wait to re-transmit state 258.
From idle state 251, when the client desires to transmit a data packet, the
client-state machine 502 enters a send request state 254. In the send
request state 254, the client sends a request-to-transmit signal to hub
30. The client then waits for an acknowledgment signal from hub 30
(indicating that the link is clear to send). While waiting for an
acknowledgment, if hub 30 signals the client that a packet will be
incoming to the client, the client-state machine 502 enters the
wait-for-packet state 252 to inhibit messsage transmission from the
client. In the send-request state 254, when the client receives an
acknowledgment from hub 30, client-state machine 502 enters a transmit
packet state 256. In the transmit packet state 256, the client sends a
data packet to hub 30. Upon the end-of-packet being sent, client-state
machine 502 enters a wait-for-idle/busy state 257. In wait-for-idle/busy
state 257, if the client receives an idle signal from hub 30, transmission
of the packet was successful and client-state machine 502 returns to idle
state 251. If the client receives a busy signal from hub 30, client-state
machine 502 enters wait to re-transmit state 258.
In the wait-to-transmit state 258, client-state machine 502 waits for hub
30 to stop sending a busy signal. If hub 30 signals that a packet will be
incoming to the client, client-state machine 502 enters wait-for-packet
state 252. When in wait-to-transmit state 258, if client-state machine 502
detects the busy signal from hub 30 being de-asserted, client-state
machine 502 returns to send-request state 254. When in wait-to-transmit
state 258, if client-state machine 502 times out waiting for hub 30 to
de-assert the busy signal, the client-state machine 502 enters a
discard-packet state 259. When in the discard-packet state 259, the client
discards the network packet and returns to the idle state 251.
There are situations where a client might be the end-node destination
address for a very long string of incoming packets and given the above
description it might appear that a send request would not be allowed. In
response to an incoming packet signal, the client must switch to the
wait-for-packet state 252 t | | |
