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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an automatic equalizer which automatically
equalizes transmission distortion or the like of a receive signal, and
more particularly to an automatic equalizer suitable for use with a modem
having a very high transmission rate,
2. Description of the Related Art
Various modems (modulator-demodulators) for use for transmission of data
which can transmit data at various rates have been provided
conventionally.
Generally, modems having a transmission speed of 9,600 bit/sec (9.6 kbps)
or 14.4 kbps represented by the Recommendation V.29 have been put into
practical use widely. However, as increase in transmission speed
progresses in recent years, very high speed modems having a data
transmission rate of 28.8 kbps are being developed energetically.
Modems as described above normally employ an automatic equalizer (which may
be hereinafter referred to simply as equalizer) as shown in FIG. 11 in
order to compensate, upon reception of data, for deterioration of the data
(signal) caused by transmission distortion.
Referring to FIG. 11, the automatic equalizer is generally denoted at 102
and is interposed between an automatic gain control section (AGC) 101 and
a signal discrimination section 103. The automatic gain control section
101 adjusts a loop gain so that the level of an inputted demodulated
signal may be equal to a predetermined reference level to automatically
adjust the level of a receive signal to be inputted to the automatic
equalizer 102 at the succeeding stage. Thus, the automatic gain control
section 101 is employed so that the automatic equalizer 102 at the
succeeding stage may operate accurately.
The automatic equalizer 102 performs equalization processing to correct
transmission distortion or the like of a channel. To this end, the
automatic equalizer 102 includes an equalizer calculation section 1021 and
a tap coefficient error correction section 1022.
Though not shown, the equalizer calculation section 1021 includes, as well
known in the art, a plurality of delaying sections for delaying a
demodulated signal from the automatic gain control section 101 in time, a
tap coefficient multiplication section for multiplying delayed signals
from the delaying sections by error information (an error signal) from the
tap coefficient error correction section 1022 which will be hereinafter
described, and a totaling calculation section for totaling results of the
multiplications from the tap coefficient multiplication section. A result
of the calculation by the totaling calculation section is outputted as an
equalized signal.
The tap coefficient error correction section 1022 receives one of two
branched outputs of the automatic gain control section 101 and error
information (an error signal) from the signal discrimination section 103,
which will be hereinafter described, and produces and outputs, based on
the thus received signals, a control signal so that the values of the tap
coefficients of the equalizer calculation section 1021 may be corrected to
optimum values.
The signal discrimination section 103 performs pre-processing for signal
discrimination at a succeeding stage and outputs false reference signal
corresponding to an input signal thereto. The signal discrimination
section 103 also produces and outputs a false reference signal for the tap
coefficient error correction section 1022 of the automatic equalizer 102.
Further, the output of the automatic equalizer 102 and the discrimination
result output of the signal discrimination section 103 are negatively
added to each other (subtracted from each other) to obtain an error
signal, which is outputted to the tap coefficient error correction section
1022. An adder 104 is connected so as to negatively add (subtract) an
output signal of the signal discrimination section 103 to (from) an input
signal to the signal discrimination section 103 to obtain an error signal
to be supplied to the tap coefficient error correction section 1022.
Due to the construction described above, with the automatic equalizer shown
in FIG. 11, a demodulated signal whose gain is kept fixed by the automatic
gain control section 101 is input to the equalizer calculation section
1021. The equalizer calculation section 1021 corrects tap coefficients to
optimum values in accordance with a control signal obtained from the tap
coefficient error correction section 1022 to per form accurate
equalization of the input signal.
In this instance, in the tap coefficient error correction section 1022,
required processing such as multiplication or addition is performed on a
signal before equalization to be input to the automatic equalizer 102 and
an error signal obtained by negative addition of the output of the
automatic equalizer 102 in the past and the discrimination result output
of the signal discrimination section 103 by the adder 104. A signal
obtained by the processing is outputted as a control signal to the
equalizer calculation section 1021.
In short, in the conventional automatic equalizer, input data (an input
signal) to the automatic equalizer 102 and input data to the tap
coefficient error correction section 1022 which is used for error
correction are used commonly.
In order to use the automatic equalizer 102 of such a construction as
described above for a very high speed modem having a transmission rate of,
for example, 28.8 kbps, it is necessary to increase the number of taps of
the equalizer 102 very much and lower the level of input data so that the
loop gain of the equalizer 102 may be kept equal to or lower than 1.
However, if the level of input data to the automatic equalizer 102 is
lowered in this manner, then the accuracy in error correction of the tap
coefficients by the tap coefficient error correction section 1022, in
which the input data is used, commonly is degraded, and also the accuracy
of the automatic equalizer 102 is degraded, which is a subject to be
solved with the conventional automatic equalizer.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an automatic equalizer
which can keep, even where it is employed for a modem which has a very
high transmission rate and has a very large number of taps, a high degree
of accuracy in error correction of tap coefficients and allows
equalization processing with a high degree of accuracy.
In order to attain the object described above, according to an aspect of
the present invention, there is provided an automatic equalizer, which
comprises an equalization calculation section including a plurality of
delaying sections, a tap coefficient multiplication section and a totaling
calculation section, a tap coefficient error correction section for
correcting errors of tap coefficients for the equalization calculation
section based on an input to the automatic equalizer and an output of the
automatic equalizer, and an input level setting section for setting an
input signal level to the equalization calculation section and an input
signal level to the tap coefficient error correction section to levels
different from each other.
Accordingly, in the automatic equalizer of the present invention, when an
input signal is to be equalized by the equalization calculation section,
the input signal level to the equalization calculation section and the
input signal level to the tap coefficient error correction section are set
to levels different from each other. Then, based on the signal to the
coefficient error correction section, errors of the tap coefficients for
the equalization calculation section can be corrected. Consequently,
equalization processing by the equalization calculation section and error
correction processing by the tap coefficient error correction section can
be performed independently of each other using signals of different levels
from each other for the equalization processing and the error correction
processing. Accordingly, even if the number of taps of the equalizer is
increased, the accuracy in error correction processing by the tap
coefficient error correction section can be maintained high.
Further objects, features and advantages of the present invention will
become apparent from the following detailed description when read in
conjunction with the accompanying drawings in which like parts or elements
are denoted by like reference characters.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating an aspect of the present invention;
FIG. 2 is a block diagram of an on-line system in which an automatic
equalizer to which the present invention is applied is incorporated;
FIG. 3 is a block diagram showing a construction of a modem employed in the
on-line system of FIG. 2;
FIG. 4 is a block diagram showing a detailed construction of the modem
employed in the on-line system of FIG. 2;
FIG. 5 is a block diagram showing a construction of an automatic equalizer
according to the present invention which is incorporated in the modem
shown in FIG. 3 or 4;
FIG. 6 is a block diagram showing a detailed construction of the automatic
equalizer shown in FIG. 5;
FIG. 7 is a table illustrating an optimum input level to the automatic
equalizer shown in FIG. 5;
FIG. 8 is a diagrammatic view showing an example of signal points on an eye
pattern by the automatic equalizer shown in FIG. 5;
FIG. 9 is a diagrammatic view illustrating operation of the automatic
equalizer shown in FIG. 5;
FIG. 10 is a diagrammatic view illustrating operation of the automatic
equalizer shown in FIG. 5; and
FIG. 11 is a block diagram showing a construction of a general automatic
equalizer.
DESCRIPTION OF THE PREFERRED EMBODIMENT
a. Aspect of the Invention
Referring first to FIG. 1, there is shown, in the block diagram, an
automatic equalizer according to an aspect of the present invention. The
automatic equalizer shown includes an equalization calculation section 1,
a tap coefficient error correction section 2, an input level setting
section 3, and a tap coefficient level correction section 4. Though not
shown, the equalization calculation section 1 includes a plurality of
delaying sections, a tap coefficient multiplication section and a totaling
calculation section.
The tap coefficient error correction section 2 corrects errors of tap
coefficients for the equalization calculation section 1 based on an input
to the automatic equalizer and an output of the automatic equalizer. The
input level setting section 3 sets the input signal level to the
equalization calculation section 1 and the input signal level to the tap
coefficient error correction section 2 to levels different from each
other.
Consequently, in the automatic equalizer of the present invention shown in
FIG. 1, when an input signal is to be equalized by the equalization
calculation section 1, the input level setting section 3 sets the input
signal level to the equalization calculation section 1 and the input
signal level to the tap coefficient error correction section 2 to levels
different from each other. Then, based on the signal to the top
coefficient error correction section 2, the tap coefficient error
correction section 2 can correct errors of the tap coefficients for the
equalization calculation section 1.
In short, by setting the input signal level to the equalization calculation
section 1 and the input signal level to the tap coefficient error
correction section 2 to the levels different from each other by means of
the input level setting section 3, the equalization processing by the
equalization calculation section 1 and the error correction processing by
the tap coefficient error correction section 2 can be performed using
signals of different levels from each other.
Accordingly, with the automatic equalizer of the present invention
described above, equalization processing by the equalization calculation
section 1 and error correction processing by the tap coefficient error
correction section 2 can be performed independently of each other using
signals of different levels from each other, and consequently, even if the
number of taps of the equalizer is increased, the accuracy in error
correction processing by the tap coefficient error correction section 2
can be maintained.
Though not shown, the input level setting section 3 includes a branching
section for branching an input signal into two systems, and a level
variation section for varying the level of one of the branched signals
branched by the branching section which is to be inputted to the
equalization calculation section 1. Further, the level variation section
varies the level of the signal to the equalization calculation section 1
so as to secure a bit accuracy necessary for error correction of the
output of the equalizer.
Accordingly, with the automatic equalizer of the present invention
described above, the input signal level to the equalization calculation
section 1 and the input signal level to the tap coefficient error
correction section 2 can be set to the levels different from each other
with certainty. Further, since, in this instance, the level of the signal
to the equalization calculation section 1 is varied so that the bit
accuracy necessary for error correction of the output of the equalizer may
be secured, error correction can be performed with a higher degree of
accuracy.
Further, the automatic equalizer is constructed such that one of the
branched signals branched by the branching section of the input level
setting section 3 which is to be inputted to the tap coefficient error
correction section 2 is inputted to the tap coefficient error correction
section 2 after a delay corresponding to a delay provided by the
equalization calculation section 1.
Thus, one of the branched signals branched by the branching section of the
input level setting section 3 which is to be inputted to the tap
coefficient error correction section 2 is inputted to the tap coefficient
error correction section 2 after delayed corresponding to a delay provided
by the equalization calculation section 1. Consequently, the input timings
of the two signals to be inputted to the tap coefficient error correction
section 2 coincide with each other. Accordingly, error correction by the
tap coefficient error correction section 2 can be performed with
certainty.
The tap coefficient level correction section 4 mentioned above corrects the
output level of the tap coefficient error correction section 2 so that the
automatic equalizer may have a loop gain equal to or lower than 1. In this
instance, the tap coefficient level correction section 4 corrects the
output level of the tap coefficient error correction section 2 based on an
input signal to the automatic equalizer and taking a number of taps of the
automatic equalizer into consideration.
Accordingly, with the automatic equalizer of the present invention
described above, since the output level of the tap coefficient error
correction section 2 can be corrected by the tap coefficient level
correction section 4 so that the loop gain of the equalizer may be equal
to or lower than 1, an equalizer output of a high degree of accuracy can
be obtained without suffering from an overflow of any of the tap
coefficients of the equalizer. Further, since, in this instance, the
output level of the tap coefficient error correction section 2 can be
corrected based on an input signal to the equalizer and taking the number
of taps of the equalizer into consideration, even if the number of taps of
the equalizer is increased, error correction of the tap coefficients can
be performed while maintaining a high degree of accuracy.
b. Embodiment of the Invention
Referring now to FIG. 2, there is shown in block diagram an on-line system
in which an automatic equalizer to which the present invention is applied
is incorporated. The on-line system shown includes a host computer 10, and
a modem 12 to which the host computer 10 is connected by way of a
communication control apparatus (CCP) not shown. Another modem 12'
installed at another location is connected to the modem 12 by way of an
analog line (privately used line) 14. Terminals 16A to 16C serving as work
stations are connected to the modem 12'.
Each of the modems 12 and 12' is constructed as a very high speed modem
having a transmission rate of, for example, 28.8 kbps and operates, for
example, such that it time division processes data of a main channel for
three main data and a secondary channel for secondary data for supervision
of the network, modulates the thus processed data and transmits the thus
modulated data by a non-Nyquist transmission system, and demodulates a
receive signal to reproduce data (main data and secondary data). Further,
as well known in the art, each of the modems 12 and 12' transmits, prior
to transmission of data, training data so that initialization processing
of the receiving section can be performed making use of the training data.
The modem 12 which serves as a parent station includes, in order to exhibit
such functions as described above, a transmission section 20 with a
modulation function and a reception section 22 with a demodulation
function as shown in FIG. 4. Further, a transmission low-pass filter and a
transmission amplifier not shown are provided on the output side of the
transmission section 20, and a reception amplifier and a reception
low-pass filter not shown are provided on the input side of the reception
section 22.
Referring to FIG. 3, each of the transmission section 20 and the reception
section 22 includes a microprocessor unit (MPU) 24, a digital signal
processor (DSP) 26, a D/A (digital to analog) converter 28 and an A/D
(analog to digital) converter 29. It is to be noted that the MPU 24 or the
DSP 26 constituting the transmission section 20 or the reception section
22 is suitably provided by a plural number depending upon the capacity or
the processing capability of the same.
Essential part of the modem 12 will be described in detail below. Referring
back to FIG. 4, the transmission section 20 of the modem 12 shown includes
a serial to parallel converter (S/P converter) 30, a pair of scramblers
(SCR) 32A and 32B, a pair of sum calculation sections 34A and 34B, a
trellis-coded modulation section (TCM) 36, a pair of signal point
generation sections 38A and 38B, a frame rotation section 40, a roll-off
filter (ROF) 42, a modulation section 44, a fixed equalization section
(EQL) 46, an attenuator (ATT) 48, a sequencer (SEQ) 50 serving as a
control section, and so forth.
The S/P converter 30 converts main channel data SDm from serial data into
parallel data. The scramblers 32A and 32B individually randomize signals
(main channel data SDm and secondary data SDs, and pre-emphasis data).
The sum calculation section 34A performs summing calculation of the output
of the scrambler 32A, and the sum calculation section 34B performs summing
calculation of the output of the scrambler 32B. The sum calculation
section 34B also has a gray/natural code converting (G/N converting)
function which is used upon training. The reason why summing calculation
of data is performed by both of the sum calculation sections 34A and 34B
is that it is intended to transmit transmission data as relative
difference data between two preceding and succeeding data with respect to
time. The trellis-coded modulation section 36 performs processing for
correcting an error.
The signal point generation sections 38A and 38B generate desired signal
points based on main data SDm and secondary data SDs, respectively. Upon
initialization, the signal point generation sections 38A and 38B produce
training data in response to a control signal from the sequencer 50.
When a step-out condition occurs, the frame rotation section 40 rotates a
frame in order to perform re-drawing in. The roll-off filter 42 passes
only a signal of a digital output within a predetermined frequency range
and functions as a low-pass filter.
The modulation section 44 performs modulation processing of the output of
the roll-off filter 42. The carrier frequency of the modulation section 44
is set, for example, to 1,850 Hz.
The fixed equalization section 46 equalizes a delay, an amplitude component
on a channel or the like. The attenuator 48 performs level adjustment of
the output of the fixed equalization section 46.
The sequencer 50 serving as a control section controls the functions 30 to
48 of the transmission section 20. Further, upon initialization, the
sequencer 50 controls the signal point generation sections 38A and 38B so
as to produce training data.
It is to be noted that the MPU 24 has the functions of the scramblers 32A
and 32B, the sum calculation sections 34A and 34B, the trellis-coded
modulation section 36, the signal point generation sections 38A and 38B,
the frame rotation section 40 and the sequencer 50 in the transmission
section 20, and the DSP 26 has the functions of the roll-off filter 42,
the modulation section 44, the fixed equalization section 46 and the
attenuator 48.
Meanwhile, the reception section 22 of the modem 12 includes a fixed
equalizer 52, a demodulation section 54, a roll-off filter
(band-separation filter) 56, an automatic gain control section (AGC) 58,
an automatic equalizer (EQL) 60, a carrier phase correction section (CAPC)
62, a hard decision section 64A, a frame reverse rotation section 66, a
soft decision section 64B, a pair of signal point discrimination sections
68A and 68B, a pair of difference calculation sections 70A and 70B, and a
pair of descramblers 72A and 72B. The reception section 22 further
includes a carrier detection section (CD) 80, a training data detection
section (TRG) 82, an impulse reproduction section 84, an impulse detection
section 84A, a timing extraction section 86, a timing locking section 88,
a sequencer 90 serving as a control section, and so forth.
The fixed equalizer 52 equalizes a delay, an amplitude component on a
channel or the like. The demodulation section 54 performs demodulation
processing for a receive signal after digital conversion by the A/D
converter 29. The roll-off filter 56 passes therethrough only a signal of
a digital output of the demodulation section 54 within a predetermined
frequency range. In the present embodiment, for example, a decimation
filter is employed for the roll-off filter 56.
The automatic gain control section 58 constructs receive level automatic
adjustment means which adjusts the loop gain so that the level of a
demodulated signal after band-width limitation by the roll-off filter 56
may be equal to a predetermined reference value and inputs the demodulated
signal of the predetermined reference level to the automatic equalizer 60
at the succeeding stage. The automatic gain control section 58 is required
to allow the automatic equalizer 60 at the succeeding stage to operate
accurately.
The automatic equalizer 60 performs equalization processing to correct
transmission distortion or the like of the channel. The carrier phase
correction section 62 predicts and removes (or restrains) a frequency
offset, a phase jitter or a phase intercept variation from the output of
the automatic equalizer 60 to correct the phase of the carrier.
The hard decision section 64A outputs a false reference signal
corresponding to an input signal thereto. The soft decision section 64B
receives a false reference signal from the hard decision section 64A and
performs viterbi decoding or the like of the false reference signal to
perform error correction. The hard decision section 64A and the soft
decision section 64B function as a signal pre-discrimination section.
The frame reverse rotation section 66 is provided to prevent a step-out
condition. The signal point discrimination section 68A discriminates
signal points of main data. The signal point discrimination section 68B
discriminates, in an ordinary operation, signal points of secondary data,
but discriminates, upon training, the output of the frame reverse rotation
section 66 (secondary data before discrimination by the soft decision
section 64B is performed) among four values.
The difference calculation section 70A performs difference calculation of
the output of the signal point discrimination section 68A while the
difference calculation section 70B performs difference calculation of the
output of the signal point discrimination section 68B. The difference
calculation section 70B further has a gray/natural code converting (G/N
converting) function which is used upon training. Further, the difference
calculation sections 70A and 70B have a function of restoring original
data from transmitted relative difference data.
The descramblers 72A and 72B descramble signals in a scrambled condition
and output resulted signals as main data RDm and secondary data RDs,
respectively.
The carrier detection section 80 detects a carrier to detect whether or not
data has been received. The output of the carrier detection section 80 is
supplied to the sequencer 90.
The training data detection section 82 detects training data to detect the
beginning of training. Also the output of the training data detection
section 82 is supplied to the sequencer 90.
The impulse reproduction section 84 reproduces an impulse from training
data and, in this instance, can reproduce a desired impulse. The impulse
detection section 84A detects an impulse reproduced by the impulse
reproduction section 84, and also the output of the impulse detection
section 84A is supplied to the sequencer 90.
The timing extraction section 86 extracts a signal timing from the output
of the automatic gain control section 58 to discriminate where the signal
timing is. The timing locking section 88 locks the output of the timing
extraction section 86 using a PLL circuit.
The sequencer 90 serving as a control section controls the function
sections 52 to 88 of the reception section 22.
It is to be noted that a line indicated by a chain line in each of the
secondary data transmission and reception systems of FIG. 4 indicates the
line upon training. Meanwhile, the DSP 26 has the functions of the fixed
equalizer 52, the demodulation section 54, the roll-off filter 56, the
automatic gain control section 58, the automatic equalizer 60, the carrier
phase correction section 62, the hard decision section 64A, the frame
reverse rotation section 66, the soft decision section 64B, the carrier
detection section 80, the training data detection section 82, the impulse
reproduction section 84, the impulse detection section 84A, the timing
extraction section 86 and the timing locking section 88 in the reception
section 22, and the MPU 24 has the functions of the signal point
discrimination sections 68A and 68B, the difference calculation sections
70A and 70B, and the descramblers 72A and 72B in the reception section 22.
It is to be noted that also the modem 12' which serves as a child station
has the same construction as that of the modem 12 serving as a parent
station, and accordingly, description of the construction of the modem 12'
is omitted herein to avoid redundancy.
In the following, operation of the entire on-line system having the
construction described above will be described. First, in the transmission
section 20, main channel data SDm is converted from serial data into
parallel data by the S/P converter 30 and then scrambled by the scrambler
32A. Then, the output of the scrambler 32A is processed by sum calculation
section 34A so that relative difference data is produced. The relative
difference data is processed for error correction by the trellis-coded
modulation section 36, and desired signal points are generated from the
output of the trellis-coded modulation section 36 by the signal point
generation section 38A.
Meanwhile, also secondary data SDs is scrambled by the scrambler 32b and
then processed by sum calculation by the sum calculation section 34B so
that relative difference data is produced. Then, desired signal points are
generated from the relative difference data by the signal point generation
section 38A.
Thereafter, the outputs of the signal point generation sections 38A and 38B
pass the frame rotation section 40 and are filtered by the roll-off filter
42, whereafter they are modulated by the modulation section 44. Further,
the signal obtained by the modulation is supplied to the fixed
equalization section 46, by which a delay, an amplitude component on a
channel and so forth of the signal are equalized. The output of the fixed
equalization section 46 is adjusted in level by the attenuator 48 and then
converted from a digital signal into an analog signal by the D/A converter
28, whereafter it is transmitted on a transmission line by the non-Nyquist
transmission method.
In the reception section 22, a receive signal is converted from an analog
signal into a digital signal by the A/D converter 29 and then supplied to
the fixed equalizer 52, by which a delay, an amplitude on a channel and so
forth of the receive signal are equalized. The output of the fixed
equalizer 52 is demodulated by the demodulation section 54 and then
filtered by the roll-off filter 56, whereafter the receive level with
which the demodulated signal is to be inputted to the automatic equalizer
60 at the succeeding stage is automatically adjusted by the automatic gain
control section 58 by adjustment of the loop gain so that the level of the
demodulated signal may become equal to a predetermined reference value.
The automatic equalizer 60 performs equalizing processing for correction of
transmission distortion or the like of the transmission line. Further, the
carrier phase of the output of the automatic equalizer 60 is corrected by
the carrier phase correction section 62, and signal pre-discrimination of
the carrier phase correction section 62 is performed by the hard decision
section 64A and the soft decision section 64B. Thereafter, the signal
points of the main data are discriminated by the signal point
discrimination section 68A, and the signal points of the secondary data
are discriminated by the signal point discrimination section 68B.
Thereafter, the main data and the secondary data are processed by
difference calculation processing and descrambling processing separately
from each other.
Consequently, stabilized very high speed data transmission can be realized
without using any data compression processing, and a modem having a high
degree of reliability can be provided.
Now, the automatic equalizer (EQL) 60 according to the present invention
which is employed in the reception section 22 of the very high speed modem
described above will be described in detail.
Referring now to FIGS. 5 and 6, there is shown a construction of an
automatic equalizer according to a preferred embodiment of the present
invention. The automatic equalizer (which may be hereinafter referred to
merely as equalizer) shown is generally denoted at 60 and includes an
input level setting section 601, an equalizer calculation section 602, a
tap coefficient level correction section 603 and a tap coefficient error
correction section 604. It is to be noted that the automatic gain control
section (AGC) 58 shown in FIG. 5 is similar to that described hereinabove
with reference to FIG. 4, and a signal discrimination section 61
corresponds to the signal pre-discrimination section constituted from the
hard decision section 64A and the soft decision section 64B shown in FIG.
4. It is to be noted that an adder 605 is connected between the input and
the output of the signal discrimination section 61 and negatively adds
input and output signals (data) to and from the signal discrimination
section 61 to obtain an error signal (error amount) for the tap
coefficient error correction section 604 which will be hereinafter
described.
The input level setting section 601 sets the input signal level to the
equalizer calculation section 602 to a level different from the input
signal level to the tap coefficient error correction section 604 which
will be hereinafter described. In particular, a branching section 6010 of
the input level setting section 601 branches an input signal thereto into
two systems, and a multiplier 6011 constituting a level variation section
multiplies the level of one of the branched signals to be supplied to the
equalizer calculation section 602 by 1/X (where X<1) to vary the input
signal level. It is to be noted that, in FIG. 6, the value by which the
input signal is multiplied by the multiplier 6011 is set to "X=8". The
input level setting section 601 further includes an adder 6012 which
performs rounding processing (RN) of an inputting signal multiplied by 1/8
by the multiplier 6011 of the input level setting section 601.
The equalizer calculation section 602 performs equalization (calculation)
of an input signal thereto from the input level setting section 601 using
error correction signals from the tap coefficient level correction section
603. The equalizer calculation section 602 includes, as seen from FIG. 6,
63 pairs of delaying sections (T) 1C to 63C and 1D to 63D, 64 tap
coefficient multiplication sections 1E to 64E and a totaling calculation
section 6021.
The delaying sections 1C to 63C successively delay one of a pair of
branched signals of an input signal to the automatic equalizer 60 branched
by the input level setting section 601 in time and output the thus delayed
signals to the tap coefficient error correction section 604 which will be
hereinafter described. The delaying sections 1D to 63D similarly delay the
input signal, which has been branched by the input level setting section
601 and has a signal level varied to 1/8 by the input level setting
section 601, and output the thus delayed signals to the tap coefficient
multiplication sections 1E to 63E, respectively. In short, the signal
branched by the input level setting section 601 to the tap coefficient
error correction section 604 is supplied to the tap coefficient error
correction section 604 after it is delayed corresponding to the delays of
the input signal by the delaying sections 1C to 63C of the equalizer
calculation section 602.
The tap coefficient multiplication sections 1E to 63E multiply signals
obtained by successively delaying an input signal by the delaying sections
1D to 63D by corresponding error correction signals from the tap
coefficient level correction section 603 which will be hereinafter
described. The totaling calculation section 6021 adds all of data obtained
by multiplications by the tap coefficient multiplication sections 1E to
64E. It is to be noted that the tap coefficient multiplication in section
64E multiplies ".beta." place of the input signal by a corresponding error
correction signal from the tap coefficient level correction section 603.
The tap coefficient level correction section 603 corrects the output level
of the tap coefficient error correction section 604 so that the loop gain
of the entire equalizer 60 may be equal to or lower than 1. The tap
coefficient level correction section 603 includes, as shown in FIG. 6, 64
delaying sections (nT) 1G to 64G, 64 pairs of adders 1H to 64H and 1J to
64J, and 64 multipliers 1K to 64K. The multipliers 1K to 64K multiply the
outputs of the tap coefficient error correction section 604 by data
"ALPHA" for adjustment of the signal level. The outputs of the multipliers
1K to 64K are individually integrated successively by being added to data
of such outputs in the past delayed by the delaying sections 1G to 64G by
the adders 1J to 64J, respectively. The output levels of the tap
coefficient error correction section 604 are corrected by such
integration. It is to be noted that the adders 1H to 64H perform rounding
processing (RN) of the outputs of the adders 1J to 64J, respectively.
The tap coefficient error correction section 604 produces error correction
signals based on an input signal from the input level setting section 601
before the signal level is varied by the input level setting section 601
and an error signal obtained by negative addition (subtraction) of the
input and the output to and from the signal discrimination section 61 by
the adder 605, and outputs the thus produced error correction signals to
the tap coefficient level correction section 603 to allow corrections of
errors of tap coefficients for the equalizer calculation section 602.
To this end, the tap coefficient error correction section 604 includes, as
shown in FIG. 6, 64 delaying sections (nT) 1L to 64L, 64 pairs of adders
1M to 64M and 1N to 64N, and 64 multipliers 1P to 64P. The multipliers 1P
to 64P multiply input signals thereto from the input level setting section
601 by an error signal (refer to FIG. 5) obtained by subtraction between
an input signal and an output signal to and from the signal discrimination
section 61. The outputs of the multipliers 1P to 64P are individually
integrated successively by being added to data of such outputs in the past
delayed by the delaying sections 1L to 64L by the adders 1N to 64N,
respectively, thereby to produce error correction signals to be outputted
to the tap coefficient level correction section 603. It is to be noted
that also the adders 1M to 64M perform rounding processing (RN) of the
outputs of the adders 1J to 64J, respectively.
Operation of the automatic equalizer 60 of the present invention having the
construction described above will be described in detail below.
First, when a receive signal of the modem outputted from the automatic gain
control section 58 (refer to FIG. 5) is inputted to the automatic
equalizer 60, the receive signal is branched into two systems by the input
level setting section 601. One of the branched receive signals is
successively delayed by the delaying sections 1C to 63C and outputted to
the tap coefficient error correction section 604. The other branched
receive signal is multiplied by 1/8 by the multiplier 6011 so that the
signal level thereof is varied. Then, the output of the multiplier 6011 is
rounded by the adder 6012 and then outputted to the tap coefficient
multiplication sections 1E to 63E.
In short, the input signal is branched into two systems by the input level
setting section 601, and the level of one of the thus branched signals to
the equalizer calculation section 602 | | |
