Dual-architecture super-scalar pipeline

Claims

I claim:

1. A central processing unit (CPU) for processing instructions from two separate instruction sets, the CPU comprising:

RISC instruction decode means for decoding instructions from a RISC instruction set, the RISC instruction set having a first encoding of operations;

CISC instruction decode means for decoding instructions from a CISC instruction set, the CISC instruction set having a second encoding of operations, the first encoding of operations substantially independent from the second encoding of operations;

instruction set indicating means for indicating an instruction set to be decoded, the instruction set indicating means having a RISC state indicating that the RISC instruction set be decoded, the instruction set indicating means having a CISC state indicating that the CISC instruction set be decoded;

select means, coupled to the RISC instruction decode means and the CISC instruction decode means, for outputting a control word, the control word generated from a decoding of an instruction from the RISC instruction set by the RISC instruction decode means when the instruction set indicating means is in the RISC state, the control word generated from a decoding of an instruction from the CISC instruction set by the CISC instruction decode means when the instruction set indicating means is in the CISC state, the control word having a third encoding of operations to control words, the third encoding of operations to control words being related to but substantially different from the first encoding and the second encoding; and

execute means, coupled to the select means and receiving the control word, for executing operations, the execute means executing an operation decoded by the RISC instruction decode means when the instruction set indicating means is in the RISC state, the execute means executing an operation decoded by the CISC instruction decode means when the instruction set indicating means is in the CISC state,

wherein RISC instructions and CISC instructions are directly decoded to the control word, the CISC instructions not being translated to RISC instructions,

whereby instructions from both the RISC instruction set and the CISC instruction set are decoded into control words which are executed by the CPU.

2. The CPU of claim 1 wherein the execute means comprises:

a plurality of pipelines, each pipeline in the plurality of pipelines comprising a sequence of stages, each pipeline for executing a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set, each pipeline responsive to a particular format of the control word.

3. The CPU of claim 2 wherein

the select means generates the control word and a secondary control word when a compound instruction is decoded, the compound instruction encoding two operations, a primary operation and a secondary operation, and wherein the plurality of pipelines comprises:

a first pipeline, receiving the control word, for executing the primary operation indicated by the control word; and

a second pipeline, receiving the secondary control word, for executing the secondary operation indicated by the secondary control word,

whereby compound instructions are decoded into two control words which are executed by two pipelines.

4. The CPU of claim 2 wherein the RISC instruction decode means and the CISC instruction decode means comprise a first decoder, the first decoder decoding a first instruction which encodes a first operation, the plurality of pipelines further comprising:

a first pipeline for executing a first subset of operations, the first subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set; and

a second pipeline for executing a second subset of operations, the second subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set;

the CPU further comprising:

a second decoder for decoding a second instruction which encodes a second operation, the second decoder having a RISC instruction decode means for decoding RISC instructions and a CISC instruction decode means for decoding CISC instructions, the second decoder outputting a second control word, the second control word encoding an operation of a RISC instruction when the instruction set indicating means is in the RISC state but the second control word encoding an operation of a CISC instruction when the instruction set indicating means is in the CISC state; and

dispatch means for allocating the plurality of pipelines, the dispatch means allocating the first pipeline to the first decoder if the first operation is an operation in the first subset of operations, the dispatch means allocating the second pipeline to the first decoder if the first operation is an operation in the second subset of operations,

the dispatch means further allocating the first pipeline to the second decoder if the second operation is an operation in the first subset of operations and the first operation is outside of the first subset of operations, the dispatch means allocating the second pipeline to the second decoder if the second operation is an operation in the second subset of operations and the first operation is outside of the second subset of operations,

whereby two RISC or CISC instructions are dispatched to the plurality of pipelines.

5. The CPU of claim 4 further comprising:

a pipeline valid array, loaded by the dispatch means, for indicating valid instructions in the plurality of pipelines, the pipeline valid array encoding if the first operation is in the first subset of operations, the second subset of operations, or not valid, the pipeline valid array further encoding if the second operation is in the first subset of operations, the second subset of operations, or not valid,

whereby validity and order of operations in the plurality of pipelines is encoded and stored in the pipeline valid array.

6. The CPU of claim 5 wherein the first subset of operations comprises arithmetic-logic-unit (ALU) operations, the CPU further comprising a floating point pipeline for processing floating point operations, the dispatch means allocating both the floating point pipeline and the first pipeline to a floating point instruction decoded by the first decoder.

7. The CPU of claim 4 wherein

the plurality of pipelines further comprises a third pipeline for executing a third subset of operations, the third subset of operations comprising operations encoded by the RISC instruction set and operations encoded by the CISC instruction set,

the dispatch means allocating the third pipeline to the first decoder if the first operation is an operation in the third subset of operations, the dispatch means allocating the third pipeline to the second decoder if the second operation is an operation in the third subset of operations and the first operation is outside of the third subset of operations.

8. The CPU of claim 7 further comprising

a third decoder for decoding a third instruction encoding a third operation, the third decoder having a RISC instruction decode means for decoding RISC instructions, the third decoder outputting a third control word encoding a RISC branch operation when the third instruction is a RISC branch instruction, the third decoder being disabled when the third instruction is not a RISC branch instruction; and wherein

the dispatch means allocates the third pipeline to the third decoder if the third operation is a RISC branch operation and the first operation is outside of the third subset and the second operation is outside of the third subset,

whereby a third instruction is dispatched to the third pipeline if the third instruction is a RISC branch instruction.

9. The CPU of claim 8 wherein

the first subset of operations comprises arithmetic-logic-unit (ALU) operations, the first pipeline for executing ALU operations;

the second subset of operations comprises memory operations, the second pipeline for executing memory operations; and

the third subset of operations comprises branch operations, the third pipeline for executing branch operations.

10. The CPU of claim 2 wherein the RISC instruction decode means and the CISC instruction decode means comprise a first decoder, the first decoder decoding a first instruction which encodes a first operation, the plurality of pipelines further comprising:

a first pipeline for executing a first subset of operations, the first subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set; and

a second pipeline for executing a second subset of operations, the second subset of operations comprising a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set;

the CPU further comprising:

second instruction set indicating means for indicating an instruction set to be decoded for a second instruction, the second instruction set indicating means having a RISC state indicating that the RISC instruction set be decoded, the second instruction set indicating means having a CISC state indicating that the CISC instruction set be decoded;

a second decoder for decoding the second instruction which encodes a second operation, the second decoder having a RISC instruction decode means for decoding RISC instructions and a CISC instruction decode means for decoding CISC instructions, the second decoder outputting a second control word, the second control word encoding an operation of a RISC instruction when the second instruction set indicating means is in the RISC state but the second control word encoding an operation of a CISC instruction when the second instruction set indicating means is in the CISC state; and

dispatch means for allocating the plurality of pipelines, the dispatch means allocating the first pipeline to the first decoder if the first operation is in the first subset of operations, the dispatch means allocating the second pipeline to the first decoder if the first operation is in the second subset of operations,

the dispatch means further allocating the first pipeline to the second decoder if the second operation is an operation in the first subset of operations and the first operation is outside of the first subset of operations, the dispatch means allocating the second pipeline to the second decoder if the second operation is an operation in the second subset of operations and the first operation is outside of the second subset of operations,

whereby both a RISC and a CISC instruction are dispatched to the plurality of pipelines.

11. The CPU of claim 10 wherein

the second instruction set indicating means is coupled to the instruction set indicating means,

if the first operation is outside of a subset of instruction-set-switching operations, the second instruction set indicating means is in the RISC state when the instruction set indicating means is in the RISC state, the second instruction set indicating means is in the CISC state when the instruction set indicating means is in the CISC state;

if the first operation is in the subset of instruction-set-switching operations, the second instruction set indicating means switches to the RISC state when the instruction set indicating means is in the CISC state, the second instruction set indicating means switching to the CISC state when the instruction set indicating means is in the RISC state,

whereby the second decoder switches to decoding an alternate instruction set when an instruction-set-switching instruction is decoded by the first decoder.

12. The CPU of claim 11 wherein the first and second instructions are dispatched within a single clock period, whereby a CISC and a RISC instruction are dispatched during the single clock period.

13. The CPU of claim 1 further comprising:

field decode means, receiving RISC instructions from the RISC instruction set and receiving CISC instructions from the CISC instruction set, for decoding source and destination fields which indicate registers in the CPU, the field decode means coupled to the instruction set indicating means,

the field decode means outputting codes, including source codes and destination codes for registers accessible to the RISC instructions when the instruction set indicating means is in the RISC state, the field decode means converting codes for registers accessible to CISC instructions into codes for registers accessible to RISC instructions when the instruction set indicating means is in the CISC state,

whereby a single set of register codes is used by RISC instructions and CISC instructions.

14. The CPU of claim 13 further comprising

bypass and interlock control means, receiving the codes for registers from the field decode means, for bypassing a result from a prior instruction to a source for a current instruction when a destination code for the prior instruction matches a source code for the current instruction,

wherein the current instruction has a dependency to the prior instruction when the destination code for the prior instruction matches the source code for the current instruction, and wherein the prior instruction and the current instruction belong to different instruction sets,

whereby a dependency may be detected between instructions from different instruction sets.

15. The CPU of claim 4 wherein the first decoder further comprises

means for detecting a move immediate instruction, the move immediate instruction encoding a move immediate operation, both the first subset of operations and the second subset of operations including the move immediate operation, the first pipeline for executing the move immediate operation and the second pipeline for executing the move immediate operation;

and wherein if a move immediate instruction is detected by the means for detecting

the dispatch means allocates the first pipeline to the second decoder if the second operation is an operation in the first subset of operations, the dispatch means allocates the second pipeline to the second decoder if the second operation is an operation in the second subset of operations,

the dispatch means further allocates the first pipeline to the first decoder if the first operation is an operation in the first subset of operations and the second operation is outside of the first subset of operations, the dispatch means allocates the second pipeline to the first decoder if the first operation is an operation in the second subset of operations and the second operation is outside of the second subset of operations,

whereby the second instruction is dispatched to the plurality of pipelines before the first instruction is dispatched when a move immediate instruction is detected in the first decoder.

16. A microprocessor for processing instructions from two separate instruction sets, the microprocessor comprising: CISC

RISC instruction decode means for decoding instructions from a RISC instruction set, the RISC instruction set having a first encoding of operations, the RISC instruction decode means generating a first control word encoding an operation decoded by the RISC instruction decode means;

CISC instruction decode means for decoding instructions from a CISC instruction set, the CISC instruction set having a second encoding of operations, the first encoding of operations substantially independent from the second encoding of operations, the CISC instruction decode means generating a second control word encoding an operation decoded by the CISC instruction decode means;

select means, coupled to the RISC instruction decode means and the CISC instruction decode means, for selecting either the first control word from the RISC instruction decode means or the second control word from the CISC instruction decode means;

instruction set indicating means for indicating an instruction set to be decoded, the instruction set indicating means having a first state indicating that the RISC instruction set be decoded, the instruction set indicating means having a second state indicating that the CISC instruction set be decoded;

the instruction set indicating means coupled to the select means, the select means selecting the first control word from the RISC instruction decode means when the instruction set indicating means is in the first state indicating that the RISC instruction set be decoded, the select means selecting the second control word from the CISC instruction decode means when the instruction set indicating means is in the second state indicating that the CISC instruction set be decoded;

the first control word and the second control word both having a third encoding of operations to control words, the third encoding of operations to control words being related to but substantially different from the first encoding and the second encoding; and

execute means, coupled to the select means and receiving first control words and second control words, for executing operations, the execute means executing the operation decoded by the RISC instruction decode means when the first control word is received from the select means, the execute means executing the operation decoded by the CISC instruction decode means when the second control word is received from the select means,

whereby instructions from both the RISC instruction set and the CISC instruction set are decoded into control words which are executed by the microprocessor.

17. The microprocessor of claim 16 wherein the execute means comprises:

a plurality of pipelines, each pipeline in the plurality of pipelines comprising a sequence of stages, each pipeline for executing a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set, each pipeline responsive to a particular format of control words.

18. A method for simultaneously processing instructions from a plurality of instruction sets in a processor having a plurality of pipelines, the method comprising:

decoding a RISC instruction in a RISC instruction decoder and determining an operation encoded by a first opcode in the RISC instruction using a first encoding of operations to opcodes for a RISC instruction set;

allocating at least one pipeline in the plurality of pipelines to the RISC instruction, the at least one pipeline having a functional unit for performing the operation encoded by the first opcode;

generating at least one control word for the RISC instruction, the at least one control word for indicating to the functional unit to perform the operation encoded by the first opcode;

transmitting the at least one control word to the at least one pipeline;

executing the operation encoded by the first opcode in the at least one pipeline;

decoding a CISC instruction in a CISC instruction decoder and determining an operation encoded by a second opcode in the CISC instruction using the first encoding of operations to opcodes for the RISC instruction set when the RISC instruction is outside of a subset of instructions that change an instruction set being processed, but determining the operation encoded by the second opcode in the CISC instruction using a second encoding of operations to opcodes for the CISC instruction set when the RISC instruction is within the subset of instructions that change the instruction set being processed;

allocating a second pipeline in the plurality of pipelines to the second instruction, the second pipeline having a second functional unit for performing the operation encoded by the second opcode, the second pipeline being a different pipeline than the at least one pipeline;

generating a second control word for the CISC instruction, the second control word for indicating to the second functional unit to perform the operation encoded by the second opcode;

transmitting the second control word to the second pipeline; and

executing the operation encoded by the second opcode in the second pipeline;

whereby instructions from a plurality of instruction sets are processed by a plurality of pipelines.

19. The method of claim 18 wherein

the at least one control word is transmitted to the at least one pipeline and the second control word is transmitted to the second pipeline during a single clock cycle,

whereby the RISC and CISC instruction are dispatched within the single clock cycle.

20. The method of claim 19 wherein

the first encoding of operations to opcodes for the RISC instruction set is substantially independent from the second encoding of operations to opcodes for the CISC instruction set.

21. The method of claim 20 wherein

the subset of instructions that change the instruction set being processed comprises a plurality of unsupported complex instructions in the RISC instruction set that are not decodable by the RISC instruction decoder.

RELATED APPLICATION

This application is related to application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, hereby incorporated by reference. This application is also related to application for a "Pipeline with Temporal Re-Arrangement of Functional Units for Dual-Instruction-Set CPU", filed Jan. 11, 1994, U.S. Ser. No. 08/180,023, abandoned, FWC No. 08/361,017 was filed in place of it, now U.S. Pat. No. 5,542,059, hereby incorporated by reference. This application is further related to application for a "Shared Register Architecture for a Dual-Instruction-Set CPU", filed Jul. 20, 1994, U.S. Ser. No. 08/277,962, now U.S. Pat. No. 5,481,693, hereby incorporated by reference and to application for a "Dual-Architecture Exception and Branch Prediction using a Fault-Tolerant Target Finder Array", filed Aug. 31, 1994, U.S. Ser. No. 08/298,778, hereby incorporated by reference. These related applications have a common inventor and are assigned to the same assignee as the present application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to computer systems, and more particularly to pipelines executing more than one instruction set.

2. Description of the Related Art

Modern central processing units (CPU's) employ a pipeline which allow several instructions to be processed at one time. Each stage of the pipeline performs a function in executing or processing an instruction. Instructions generally enter the pipeline and complete the pipeline one at a time, since each stage can hold just one instruction.

Super-scalar CPU's have more than one pipeline. Thus, a CPU with two pipelines can have two instructions enter and complete the pipelines at a time. The maximum throughput of instructions is effectively doubled.

DUAL-INSTRUCTION-SET PROCESSOR

Processors, or CPU's, that are capable of executing instructions from two separate instruction sets are highly desired at the present time. For example, a desirable processor would execute user applications for the x86 instruction set and the PowerPC.TM. instruction set. It would be able to execute the tremendous software base of x86 programs that run under the DOS.TM. and WINDOWS.TM. operating systems from Microsoft of Redmond, Wash., and it could run future applications for PowerPC.TM. processors developed by IBM, Apple, and Motorola.

Such a processor is described in the related application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, pending. That dual-instruction-set CPU has a pipeline which is capable of executing instructions from either a complex instruction set computer (CISC) instruction set, such as the x86 instruction set, or from a reduced instruction set computer (RISC) instruction set, such as the PowerPC.TM. instruction set.

Two instruction decode units are provided so that instructions from either instruction set may be decoded. Two instruction decoders are required when the instruction sets are separate because the instruction sets each have a substantially independent encoding of operations to opcodes. For example, both instruction sets have an ADD operation or instruction. However, the binary opcode number which encodes the ADD operation is different for the two instruction sets. In fact, the size and location of the opcode field in the instruction word is also different for the two instruction sets. In the x86 CISC instruction set, the opcode 03 hex is the ADD r,v operation or instruction, for a long operand. This same opcode, 03 hex, corresponds to a completely different instruction in the PowerPC.TM. RISC instruction set. In CISC the 03 hex opcode is an addition operation, while in RISC the 03 hex opcode is TWI--trap word immediate, a control transfer instruction. Thus two separate decode blocks are necessary for the two separate instruction sets.

Switching from the CISC instruction set to the RISC instruction set may be accomplished by a far jump or branch instruction, while a return from interrupt can switch back to the CISC instruction set. Rapid execution of these branches is desirable since it is anticipated that these switches between instruction sets will frequently be encountered.

It is therefore desired to execute instructions from both instruction sets in the same pipelines, rather than have separate, redundant, pipelines for each instruction set. When an instruction is encountered causing a switch between the instruction sets, it is desired to avoid purging the pipelines but to continue execution in the new instruction set. Thus the pipelines must be able to contain instructions from two or more instructions sets at the same time.

SUMMARY OF THE INVENTION

A central processing unit (CPU) processes instructions from two separate instruction sets. This is possible because the CPU comprises a RISC instruction decode means for decoding instructions from a RISC instruction set, and a CISC instruction decode means for decoding instructions from a CISC instruction set. The RISC instruction set has a first encoding of operations, while the CISC instruction set has a second encoding of operations. The first encoding of operations is substantially independent from the second encoding of operations.

An instruction set indicating means is for indicating an instruction set to be decoded. The instruction set indicating means has a RISC state indicating that the RISC instruction set be decoded and a CISC state indicating that the CISC instruction set be decoded. A select means is coupled to the RISC instruction decode means and the CISC instruction decode means and outputs a control word. The control word is generated from a decoding of an instruction from the RISC instruction set by the RISC instruction decode means when the instruction set indicating means is in the RISC state. However, the control word is generated from a decode of an instruction from the CISC instruction set by the CISC instruction decode means when the instruction set indicating means is in the CISC state.

The control word has a third encoding of operations to control words which is related to but substantially different from the first encoding and the second encoding. An execute means is coupled to the select means and receives the control word. The execute means executes an operation decoded by the RISC instruction decode means when the instruction set indicating means is in the RISC state, but the execute means executes an operation decoded by the CISC instruction decode means when the instruction set indicating means is in the CISC state.

Thus instructions from both the RISC instruction set and the CISC instruction set are decoded into control words which are executed by the CPU.

In further aspects of the invention the execute means comprises a plurality of pipelines. Each pipeline in the plurality of pipelines comprises a sequence of stages, and each pipeline executes a subset of operations encoded by the RISC instruction set and a subset of operations encoded by the CISC instruction set. Each pipeline is responsive to a particular format of the control word.

In other aspects of the invention the select means generates the control word and a secondary control word when a compound instruction is decoded. The compound instruction encodes two operations, a primary operation and a secondary operation. The plurality of pipelines comprises a first pipeline which receives the control word. The first pipeline executes the primary operation indicated by the control word. A second pipeline receives the secondary control word and executes the secondary operation indicated by the secondary control word.

In still further aspects of the invention the RISC instruction decode means and the CISC instruction decode means comprise a first decoder. A second decoder decodes a second instruction which encodes a second operation. The second decoder also has a RISC instruction decode means for decoding RISC instructions and a CISC instruction decode means for decoding CISC instructions. The second decoder outputs a second control word encoding an operation of a RISC instruction when the instruction set indicating means is in the RISC state, but the second control word encodes an operation of a CISC instruction when the instruction set indicating means is in the CISC state.

A dispatch means allocates the plurality of pipelines. A pipeline valid array is loaded by the dispatch means and indicates valid instructions in the plurality of pipelines. When the CPU has a floating point pipeline, the dispatch means allocates both the floating point pipeline and the first pipeline for ALU operations to a floating point instruction decoded by the first decoder. The plurality of pipelines also has a third pipeline for executing a third subset of operations. This third subset of operations comprises operations encoded by the RISC instruction set and operations encoded by the CISC instruction set.

The invention uses several pipelines that can each execute both RISC and CISC instructions. Several instruction decoders decode both RISC and CISC instructions even during the same clock cycle. Thus both RISC and CISC instructions can be dispatched to the shared pipelines. The instructions are decoded into control words which are related to but substantially different from the two instruction sets but depend upon the operation to be performed by the pipelines. The control words allow the pipelines and bypass logic to be independent of the instruction set of the decoded instructions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a stream of instructions to be processed.

FIG. 2 shows three pipelines of a super-scalar processor: a branch pipeline, an ALU pipeline, and a memory pipeline.

FIG. 3 shows the instruction decode and dispatch unit in more detail.

FIG. 4 shows the first and second instruction decoders.

FIG. 5 shows the third instruction decoder.

DETAILED DESCRIPTION

The present invention relates to an improvement in computer systems. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

This application is related copending application for a "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", filed Jan. 11, 1994, U.S. Ser. No. 08/179,926, pending, hereby incorporated by reference. This application is also related to copending application for a "Pipeline with Temporal Re-Arrangement of Functional Units for Dual-Instruction-Set CPU", filed Jan. 11, 1994, U.S. Ser. No. 08/180,023, abandoned, Ser. No. 08/361,017 was filed in place of it, hereby incorporated by refe