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Description  |
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FIELD OF THE INVENTION
The present invention relates to apparatus for testing integrated circuits
and more particularly to arrangements for testing and burning-in
integrated circuits at the wafer level.
BACKGROUND OF THE INVENTION
The desirability of testing integrated circuits at the wafer level is of
particular interest since determination of failures at this early stage
can significantly reduce costs. At present, the testing of integrated
circuit chips in wafer form is generally limited in scope, or a slow
procedure only permitting extensive testing of a few chips at a time. That
is, wafer level testing is often performed using a mechanical stepping
device with each circuit tested sequentially. Further, wafer level testing
as presently available often does not lend itself to accelerated failure
procedures, such as burn in, and thus requires still further testing at a
later stage in the manufacturing process.
An example of an integrated circuit test arrangement is shown in U.S. Pat.
No. 5,148,103, issued Sep. 15, 1992, which utilizes a flexible membrane
supporting a probe arrangement for testing one chip at a time. This patent
employs a terminating resistor or chip on the membrane for providing high
impedance, low capacitance loading. Simultaneous testing of a few circuit
chips at one time is described in U.S. Pat. No. 5,012,187, issued Apr. 30,
1991. This patent describes a test head comprising a flexible membrane of
circuit board material carrying probe bumps for contacting the pads of the
product chips. Transmission lines connect the probe bumps to the edge of
the membrane for coupling each of the circuit chips to a test apparatus.
As can be appreciated, testing of more than one chip at a time generally
will require isolation of defective chips that draw excessive current.
This difficulty can be resolved by employing a separate switch or fuse
circuit for each product chip undergoing test, as for example, is
described in the IBM Technical Disclosure Bulletins, Vol. 32, No. 6B,
November 1989 and Vol. 33, No. 8, January 1991. In the latter
publications, power and test lines are carried in the Kerf regions of the
product wafer to connect the circuit chips to a remote tester.
In a different approach, IBM Technical Disclosure Bulletin, Vol. 34 No. 8,
dated January 1992 describes a test head, solderable by means of pad bumps
to the front surface of a product wafer for sequentially, or
simultaneously, testing the circuit chips of the product wafer. The test
head includes a multiplicity of active chips each having a switch circuit
for disconnecting faulty chips of the product wafer.
These prior test arrangements fail to accommodate the currents resulting
from simultaneous testing of a multiplicity of chips as for example,
testing at one time, substantially all of the chips provided within a
conventionally sized integrated circuit wafer.
On the other hand, PCT Application WO 93/04375 International Application
Number: PCT/US92/07044, International Filing Date: Aug. 23, 1991 describes
an arrangement for simultaneous burn-in testing of a wafer in which a test
substrate carries both power and ground planes connected through vias to
deformable solder bumps on the surface of the substrate. For burn-in
testing, the substrate is urged against the face of a product wafer with
its solder bumps engaging the pads of the wafer chips.
Isolation resistors provided on the substrate connect its power and ground
planes to the integrated circuit chips to accommodate shorted chips. This
use of isolation resistors, while permitting burn-in testing, limits other
testing modes and also fails to adequately resolve the problem of short
circuited product chips, which draw large currents and reduce the voltage
available for application to neighboring chips.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention is to provide an
improved structure for testing and burning-in integrated circuit chips at
the wafer level.
It is still another object of the present invention to provide an improved
test arrangement for simultaneously testing and burning-in a plurality of
the product chips on an integrated circuit wafer simultaneously.
It is yet another object of the present invention to provide an improved
power distribution structure that provides an externally specified Vdd
voltage to each product chip on an integrated circuit wafer, the voltage
substantially independent of the current drawn by each chip and its
neighbors, and substantially independent of the presence of shorted chips
on the product wafer.
It is yet another object of the present invention to provide an improved
power distribution structure that effectively removes shorted product
chips from power distribution.
It is a feature of the present invention that a substrate having a low
thermal coefficient of expansion (TCE), such as glass ceramic, aluminum
nitride, Kovar, Invar, silicon, or a laminated metal, such as Kovar,
copper-Invar-copper, tungsten, or molybdenum is used to test product
wafers.
It is a feature of the present invention that a voltage regulator circuit
is provided for each product chip to be tested.
It is a feature of one embodiment of the present invention that power is
distributed through a glass ceramic substrate to test chips having voltage
regulators and then to the product wafer.
It is a feature of another embodiment of the present invention that power
supply current is distributed through the back surface of test chips
having voltage regulators and then to the product wafer.
It is another feature of the present invention that a voltage regulator
provided for each circuit chip to be tested has a voltage that can be
externally controlled.
It is another object of the present invention to disconnect signal I/O from
a chip having a short.
It is yet a further object of the present invention to provide an improved
test head having a plurality of active test chips including voltage
regulator circuits.
It is yet a further object of the present invention to provide a portable
apparatus having the product wafer aligned to the test head, the apparatus
ready for insertion into a tester or burn-in chamber.
It is a feature of the present invention that a vacuum clamp having a seal
on the back of the product wafer or on the back of the test head provides
a portable aligned apparatus ready for insertion into a tester or burn-in
chamber.
It is a feature of the present invention to provide a means of maintaining
temperature control of the product wafer while allowing it to conform to
the probe array, which may be non-planar.
These and other objects, features, and advantages of the invention are
accomplished by an apparatus for simultaneously contacting a plurality of
integrated circuit product chips having signal I/O, ground, and power
pads, the product chips on a product wafer having a front surface and a
back surface, the apparatus connectable to a power supply, the apparatus
comprising: a test head connectable to a plurality of the product chips on
the product wafer, said test head comprising at least one test chip
electrically connectable to the product chips, said at least one test chip
having a front and a back surface; and a plurality of voltage regulators
on said at least one test chip, said regulators connectable between the
power supply and the power pads on the product chips.
Another aspect of the invention is accomplished by an apparatus capable of
simultaneously contacting substantially all of the integrated circuit
product chips on a product wafer having a front surface and a back
surface, the product chips having signal I/O, ground, and power pads, the
apparatus connectable to a power supply, the apparatus comprising: a test
head having a first side and a second side; and said first side of said
test head capable of simultaneously contacting power pads on substantially
all of the product chips on the product wafer, said test head having means
for distributing power from the power supply to said contacting means,
said test head comprising a ceramic material, a metal, or a laminated
metal having a thermal coefficient of expansion matching that of the
product wafer.
Another aspect of the invention is accomplished by a method for testing or
burning-in substantially all of the integrated circuit product chips on a
product wafer, the product chips having signal I/O, ground, and power
pads, the method comprising the steps of: a) contacting pads of
substantially all of the product chips on the product wafer simultaneously
with a test head comprising a ceramic material, a metal, or laminated
metal having a thermal coefficient of expansion matching that of the
product wafer; b) providing power from a power supply to power pads of the
product chips through said test head; and c) testing or burning-in the
plurality of product chips on the wafer through said test head.
Another aspect of the invention is accomplished by an apparatus capable of
connecting a plurality of the chips on a product wafer to a test system to
simultaneously test or burn-in the product chips, the product wafer having
a front and a back surface, the apparatus comprising: a test head having a
front and a back surface and a plurality of contacts; means for
electrically connecting said plurality of contacts to the test system; and
means for connecting said contacts to the product wafer wherein said
connecting means comprises probes and a vacuum clamp provided between the
product wafer and said test head, a vacuum seal for said vacuum clamp
provided to the back surface of at least one of the product wafer and said
test head.
Another aspect of the invention is accomplished by an apparatus capable of
wafer level test and burn-in, the apparatus comprising: means for
contacting pads on substantially all the product chips on the product
wafer at room temperature and at a selected burn-in temperature; and means
for providing power to all the product chips to be tested or burned-in on
the product wafer at a voltage level independent of the presence of
shorted chips on the product wafer.
Another aspect of the invention is accomplished by an apparatus for
controlling the temperature of a product wafer having a back surface,
comprising: an array of pistons capable of contacting most of the area of
the back surface of the wafer; and a means for providing force to each
piston of said array capable of providing thermal contact between said
piston and the wafer to control the temperature of the wafer.
A test head of the apparatus can includes a carrier, such as a ceramic
substrate that may be formed of a material such as glass ceramic, and test
chips, including voltage regulator circuits, that are attached to the
substrate. The regulators control the magnitude of the voltage and make
the voltage delivered to each product chip under test conditions
insensitive to the presence of shorted chips on the wafer and insensitive
to the magnitude of the current drawn by each chip. The regulators are
variable to allow selection of a precise voltage. They are also gated, or
capable of being tri-stated (brought to a high impedance state), to enable
selective on or off switching of the regulator circuit. Thus, the
associated product chip can be removed from contact with power.
Alternatively, a compliance current can be set for the regulators to limit
current to shorted chips. Decoupling capacitance is provided at the output
of the regulators, enabling higher speed testing. The glass ceramic
substrate, having many thick copper layers, is capable of providing the
unregulated voltage to the test chips and to distribute regulated voltage
from the test Chips to product chips on the product wafer with minimal
voltage drops.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagrammatic, exploded sectional view in perspective of a test
fixture and test head constructed in accordance with the invention;
FIG. 2 is a block diagram of the overall testing system which employs the
test fixture of FIG. 1;
FIG. 3a is a plan view of the front surface of a test chip utilized in the
test structure of FIG. 1 and illustrating in block diagram form at least a
portion of a circuit provided in the test chip;
FIG. 3b is a plan view of the front surface of a test chip utilized in the
test structure of FIG. 1 and illustrating in block diagram form switches
for signal I/O pads provided in the test chip;
FIG. 4 is a plan view of the front surface of a circuit chip of the product
wafer of FIG. 1 illustrating some of the electrical pads provided thereon;
FIG. 5 is a plan view of a test chip employing a variable voltage regulator
in accordance an alternate embodiment of the invention;
FIG. 6a is a cross sectional view of a composite test head constructed from
separate test chips in accordance with the invention;
FIG. 6b is a cross sectional view of an alternate embodiment of a composite
test head constructed from separate test chips in accordance with the
invention;
FIG. 7a is a diagrammatic, exploded sectional view in perspective of a test
fixture and test head constructed in accordance with yet another
embodiment of the invention;
FIG. 7b is an enlargement of a portion of the exploded cross sectional view
shown in FIG. 7a;
FIG. 7c is an alternate embodiment of the structure shown in FIG. 7b
illustrating a test head having both test chips and probes for direct
connection with a tester; and
FIG. 8 is a cross sectional view of a smaller and portable alternate to the
test fixture shown in FIG. 1.
DESCRIPTION OF THE INVENTION
Several embodiments of the invention will be described, each involving
means for simultaneously testing a plurality of product chips on a wafer.
The invention is available for testing one chip at a time. But it is most
suitable for testing a large number of product chips, such as a quarter of
the chips, or a majority, and especially for testing all, or substantially
all of the non-shorted product chips on a product wafer simultaneously.
Several embodiments involve means for providing regulated Vdd voltage to
product chips. In one, a test wafer is used to directly contact pads of a
product wafer, the test wafer having voltage regulators. The voltage
regulators can include variability, gating, the ability to set compliance
currents, and the ability to feed back the actual voltage on a product
chip to the regulator to assure that its output provides the desired
voltage.
In another embodiment, a carrier is used for holding individual test chips,
and this provides significant advantage over using a whole test wafer. In
one such embodiment, the test chips are mounted on the carrier facing the
product wafer. The power supply can connect to the back plane of the
carrier, and thence to the back surface of the test chips. Alternatively,
pins can be provided on the back of the carrier for plugging into a
tester. The product wafer can also be mounted on one side of the carrier
while the test chips are mounted on the other side, there being
connections through the carrier.
The carrier can be a ceramic material such as glass ceramic or aluminum
nitride. Glass ceramic is described in commonly assigned U.S. Pat. No.
4,301,324, to A. H. Kumar, incorporated herein by reference. Glass ceramic
has many layers of thick copper conductor so as to carry the large
currents needed for wafer test and burn-in with minimum voltage drops. The
carrier can also be an insulated metal having a low TCE or a laminated
metal with alternate layers of polymer and low TCE metal. Low TCE metals
include metal alloys, such as Invar or Kovar, and elemental metals, such
as tungsten or molybdenum. Laminated metal is described in commonly
assigned U.S. Pat. No. 5,224,265 to Dux et al., incorporated herein by
reference, and in in commonly assigned U.S. Pat. No. 5,128,008 to Chen et
al., incorporated herein by reference. The carrier can also be formed of
the same material as the product wafer, typically silicon, especially if
low power chips are being tested and burned-in.
Referring now to the drawings and particularly to FIGS. 1 and 2, test
fixture 10 is illustrated comprising test head housing unit 12 for
supporting and aligning test head 16 and product wafer housing unit 17 for
supporting and aligning product wafer 18 in opposed relationship for
testing and burn-in of product wafer 18. Test head housing unit 12
includes test head housing 22 and test head support 24, while product
wafer housing unit 17 includes housing 26 and product wafer support 28.
In one embodiment, test head 16 comprises test wafer 30 (shown in face down
position) and bed-of-nails contactor unit 31. Test wafer 30 includes test
chips 32. The front surface of test wafer 30 (not visible in FIG. 1) is
connected to contactor unit 31, and edge contacts 33a, along the perimeter
of test wafer 30, are affixed to I/O signal lines 33b in flex cable 33c.
Test wafer 30 carries a plurality of integrated circuit test chips 32
(shown dotted in FIG. 1 since the view is of the back of test wafer 30),
each test chip corresponding to a product chip 34. Test chips 32 are
provided in a substantially planar distribution conforming to the
distribution of product chips 34 of wafer 18 such that each test chip 32
will be positioned in electrical connection with a correspondingly
positioned product chip 34 when test head 16 and product wafer 18 are
aligned and engaged for testing purposes. Front surface 35 of test chip 32
on test wafer 30 (FIG. 2) faces front surface 37 of product chip 34 on
product wafer 18. Back surface 38 of test chip 32 contacts test head
support 24 while back surface 39 of product chip 34 contacts product wafer
support 28. Each test chip 32 includes a test circuit that includes
voltage regulator 40, shown in block diagram form in FIG. 3a.
As later explained in detail with regard to FIGS. 3 and 4, to enable
electrical connection between test head 16 and product wafer 18, each test
chip 32 carries a number of test chip pads 50 including power voltage pad
65. Test chip pads 50 of test chip 32 are in a mirror image configuration
as compared to product chip pads 53 of associated product chip 34.
As illustrated in FIG. 1, contactor unit 31 is affixed to the front surface
of test wafer 30 and is comprised of a plurality of elongated probes, or
electrical contact members 54 electrically connected to test chip pads 50
of test chips 32. Contact members 54 extend to provide engagement of probe
ends 55 with product chip pads 53 (FIG. 4) of associated product chip 34
when test fixture 10 is aligned and clamped in its test configuration.
In this embodiment, contact members 54 are electrically and physically
attached to test chip pads 50 of test wafer 30 by wire bonding, then
formed as an integral unit by means of insulative material 57 such as
epoxy, and finally planarized as a unit so that probe ends 55 of contact
members 54 will define the contact plane of test head 16 in a hairbrush or
bed of nails structure. Contact members 54 include probes, pins, buckling
beams, deformable metal bumps, and pogo pins. In addition, other
conductors can serve to provide connection between test chips 32 and
product chips 34, such as C4 solder bumps. A reflow structure, known in
the art, in which a small area is provided for C4 contacts (known as R3)
makes disconnection of product wafer 18 after burn-in is complete
significantly easier. Particle interconnect schemes are also known in
which a diamond coated with metal is used to make a temporary contact with
an aluminum pad.
Completing the description of test head 16, flex cable 33c, attached to
edge contacts 33a of test wafer 30 carries I/O signal lines 33b (only a
few of which are depicted in FIG. 1) between remote test apparatus 58
(shown in FIG. 2) and test head 16. On test wafer 30, I/O signal lines 33b
are carded in common in the kerf areas between test chips 32 and connect
to all product chips on wafer 30.
The large current drawn from simultaneously testing or burning-in a
multiplicity of chips, such as a full wafer, is accommodated by applying
the power supply voltage and ground to back surfaces, 38 and 39
respectively, of test wafer 30 and product wafer 18 (FIGS. 1 and 2). Thus,
power supply voltage is applied to back surface 38 of test wafer 30 and
ground currents are returned to the power supply through back surface 39
of product wafer 18. This method of providing power is facilitated by
providing a p-type wafer for the product wafer and an n-type wafer for the
test wafer or vice-versa.
Power supply voltage is shown in FIG. 1 connected to terminal pad 59 on
test head support 24. Ground connection is similarly provided to product
wafer support 28. In practice, to accommodate the large currents needed
for parallel testing of a large number of chips, up to all the chips on a
full wafer, supports 24 and 28 preferably comprise a low resistance
conductive material, such as copper or brass, in electrical contact with
back surfaces 38 and 39.
In as much as the application of power supply and ground voltage is to the
back surfaces of test head 16, (test wafer 30) and product wafer 18,
arrangements are provided to insulate housings 22 and 26. As illustrated,
one arrangement is to make housings 22 and 26 of insulative material, such
as ceramic. Alternatively, while retaining electrical contact to back
surfaces 38 and 39, respectively, of test head 16 and product wafer 18,
portions between these elements and housings 22 and 26 can be made of
insulative material.
FIG. 3a shows a simple embedded voltage regulator circuit 40 on front
surface 35 of test chip 32. Connections are shown in dotted outline. Power
supply voltage input path 61 connects voltage regulator circuit 40 to
power supply voltage PS through back surface 38 of test chip 32. Regulated
output of voltage regulator 40 is connected via output line 63 to output
pad 65 on front surface 35. Decoupling capacitor 67 reduces noise on
output line 63. Preferably, decoupling capacitor 67 is on the output line
of each of the voltage regulators. Decoupling capacitor 67 is formed using
a structure such as a planar MOS capacitor, a trench capacitor, a large
array of trench capacitors, or a planar capacitor between levels of metal
(a thin film capacitor) in test chip 32.
As can be seen from the FIGS. 3a and 4, Vdd voltage pad 69 of product chip
34 is located on front surface 37 of product chip 34 in a position
corresponding to the mirror image of output pad 65 of test chip 32. Vdd
pad 69 is in connection to product circuit 71 to provide a gated and
regulated voltage input thereto when test head 16 and product wafer 18 are
engaged in their test configuration.
The operation of voltage regulator circuit 40 is determined by a gate
signal applied to gate signal pad 73. Advantageously, such gating not only
permits individual testing of select chips when desired, but also provides
isolation of shorted chips. Since gate signal pad 73 is solely for control
of test chip 32, it is not connected to product chip 34. Isolation of
shorted chips or limiting current to shorted chips can be provided
automatically in regulator circuit 40, as is well known in the art of
regulators.
For testing product wafer 18, first and second housing units 12 and 17 are
biased together by any conventional means, such as a clamp (not shown), to
provide engagement of probes 54 of test head 16 with product wafer pads 53
on front surface 37 of product wafer 18. Test head support 24 carries a
plurality of electrically conductive spring members 75 which bear against
back surface 38 of test head 16. Spring members 75 in pistons (see FIG.
7b) resiliently urge all elements of the assembly illustrated in FIG. 1
together, including probes 54 of test head 16 into electrical contact with
product wafer pads 53, support 24 to test head 16 (wafer 30), and product
wafer 18 to support 28. Spring members 75 also help remove heat from test
chips 32, while product wafer support 28 helps remove heat from product
chips 34. The use of springs and pistons to cool semiconductor wafers is
described in commonly assigned U.S. Pat. No. 5,228,502, to Chu et al.,
incorporated herein by reference. In an identical fashion, springs and
pistons can be used within product wafer su | | |
