Method and data processing system for verifying circuit test vectors

What is claimed is:

1. A method for verifying a test vector, the method comprising the steps of:

providing the test vector to a test verifier wherein the test vector is generated to test a specific circuit path within an electrical circuit, the testing of the specific circuit path giving electrical propagation time delay information for the specific circuit path, the test vector defining input values which logically affect the specific circuit path for a first test clock cycle and identifying input values which logically affect the specific circuit path for a second test clock cycle;

providing to the test verifier a circuit model which models the operation of the electrical circuit;

generating input values and output values for all circuit elements along the specific circuit path for both the first test clock cycle and the second test clock cycle by accessing the circuit model and the test vector; and

performing logical operations on the input and output values of the circuit elements along the specific circuit path to determine whether the test vector, as input to the test verifier, correctly tests the specific speed path.

2. The method of claim 1 wherein the step of providing the test vector to the verifier comprises:

providing a plurality of test vectors to the test verifier for verification in a parallel manner.

3. The method of claim 1 wherein the step of providing the test vector to the verifier comprises:

providing a plurality of test vectors to the test verifier for verification in a parallel manner wherein each test vector in the plurality of test vectors defines input values to the circuit model for both the first test clock cycle and the second test clock cycle which affect the specific path, the test vectors being stored in data arrays by the test verifier and being verified in parallel.

4. The method of claim 1 wherein the step of providing the test vector comprises:

providing a test vector which defines at least one logic value in at least one flip-flip, storage device, input terminal, input pin, or latch device which affects the specific circuit path.

5. The method of claim 1 wherein the step of providing the test vector comprises:

providing N test vectors to the test verifier wherein N is a finite integer greater than zero;

providing a first memory data array for the first test clock cycle for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the first memory array having at least N bit positions;

providing a second memory data array for the second test clock cycle for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the second memory array having at least N bit positions;

providing a third memory data array to store hazard-free value status for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the third memory array having at least N bit positions; and

using the first, second, and third memory data arrays for verifying the N test vectors in a parallel manner.

6. The method of claim 1 wherein the specific circuit path is tested for at least one transition selected from the group consisting of: input rising output falling, input rising output rising, input falling output falling, input falling output rising, output rising edge transition, and output falling edge transition.

7. The method of claim 1 wherein the specific circuit path passes through a plurality of logic gates and the step of generating input and output values comprises:

simulating the specific path using the circuit model to determine all logic values along the specific circuit path for each logic gate in the plurality of logic gates as a function of the test vector input.

8. The method of claim 7 wherein the step of simulating comprises:

determining a logic value for all inputs of each logic gate in the plurality of logic gates and an output value of each logic gate in the plurality of logic gates.

9. The method of claim 7 wherein the step of performing logical operations comprises:

performing at least one operation selected from the group consisting of: AND operation, OR operation, NAND operation, XOR operation, XNOR operation, NOT operation, and NOR operation, of the logic values which are defined for each logic gate in the plurality of logic gates along the selected circuit path in order to determine if the test vector properly test the specific circuit path for a given specific circuit path logical transition.

10. The method of claim 9 wherein the step of performing at least one operation comprises:

performing at least one operation selected from the group consisting of: AND operation, OR operation, NAND operation, XOR operation, XNOR operation, NOT operation, and NOR operation, on at least one hazard-free status value which is defined for at least one logic gate in the plurality of logic gates along the selected circuit path in order to determine if the test vector properly tests the specific circuit path for a given specific circuit path logical transition.

11. The method of claim 1 wherein the step of generating comprises:

using the input values to determine a hazard-free status for a selected input which affects the specific logic path, the hazard-free states being asserted if the selected input is guaranteed to be electrically glitch free in logic value and being deasserted if the selected input cannot be guaranteed to be electrically glitch free in logic value for the first and second clock test clock cycles.

12. A method for verifying a plurality of test vectors, the method comprising the steps of:

providing, to a test verifier, access to an electrical circuit model which models the operation of an electrical circuit;

identifying at least one circuit path in the circuit model which is to be path delay tested, a plurality of circuit elements residing along the at least one circuit path

providing the plurality of test vectors to the test verifier wherein the test verifier places the test vectors into an array structure, the array structure having a first array, a second array, and a third array for each input and output of each circuit element in the plurality of circuit elements, the first array storing first test clock cycle logic values from the plurality of test vectors for each circuit element in the plurality of circuit elements, the second array storing second test clock cycle logic values from the plurality of test vectors for each circuit element in the plurality of circuit elements, the third array being used to store hazard-free status values as a function of the first and second arrays, the plurality of test vectors is generated to test the least one circuit path within the electrical circuit model, each test vector in the plurality of test vectors defines logical input values which logically affect a state of the specific circuit path for both a first test clock cycle and a second test clock cycle;

generating input values and output values for the plurality of circuit elements for both the first test clock cycle and the second test clock cycle for each test vector in the plurality of test vectors, the generating being performed by logically operating on the first and second arrays for each input and output of each circuit element in the plurality of circuit elements;

determining, via the first and second array, which input values and output values along the specific path are to be hazard-free wherein hazard-free signals are inputs or outputs to at least on circuit element in the plurality of circuit elements wherein electrical glitching is not significant enough to alter a selected logic state of the respective inputs or outputs, the determination of hazard free values being represented in the third array; and

performing logical AND/OR operations on the input values of the circuit elements, the output values of the circuit elements, and the hazard free values along the specific circuit path to determine whether each test vector in the plurality of test vectors, as input to the test verifier, correctly tests the at least one circuit path.

13. The method of claim 12 wherein the step of providing the plurality of test vectors to the verifier comprises:

providing the plurality of test vectors to the test verifier for verification in a parallel manner wherein each test vector in the plurality of test vectors defines input values to the circuit model which affect the specific path for both the first test clock cycle and the second test clock cycle, the test vectors being stored in data arrays by the test verifier and being verified in parallel.

14. The method of claim 12 wherein the step of providing the plurality of test vector comprises:

providing a plurality of test vectors wherein each test vector defines at least one logic value in at least one flip-flip, storage device, input terminal, input pin, or latch device which affects the specific circuit path.

15. The method of claim 12 wherein the step of providing the plurality of test vectors comprises:

providing N test vectors, as the plurality of test vectors, to the test verifier wherein N is a finite integer greater than zero;

providing a first memory data array for the first test clock cycle for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the first memory array having at least N bit positions;

providing a second memory data array for the second test clock cycle for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the second memory array having at least N bit positions;

providing a third memory data array to store hazard-free value status for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the third memory array having at least N bit positions; and

using the first, second, and third memory data arrays for verifying the N test vectors in a parallel manner.

16. A test system for generating and verifying the functionality of a speed path test vector, the test system comprising:

means for modeling the operation of an electrical circuit having a circuit path;

means for providing a test vector for testing a propagation speed of the circuit path, the test vector defining input values and output values along the circuit path defined via the means for modeling, the input and output values having a first set of values defined for a first test clock cycle and a second set of values defined for a second test clock cycle, the test vector being generated by a first process within the means for providing; and

means for verifying the test vector receiving the test vector from the means for providing, the means for verifying accessing the circuit model and simulating the test vector within a portion of the circuit model to verify that the test vector correctly tests the circuit path for the propagation speed, the verification using a second process which is different from the first process.

17. The test system of claim 16 wherein the means for providing a test vector provides a plurality of test vectors to the test verifier, the test verifier processing the plurality of test vectors in parallel.

18. The test system of claim 16 wherein the means for providing a test vector provides N test vectors to the test verifier wherein N is a finite integer grater than zero, and the means for verifying (1) generates a first memory data array for the first test clock cycle for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the first memory array having at least N bit positions; (2) generates a second memory data array for the second test clock cycle for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the second memory array having at least N bit positions; and (3) generates a third memory data array to store hazard-free value status for each flip-flip, storage device, logic gate, custom logic block, input terminal, input pin, or latch device which affects the specific circuit path, the third memory array having at least N bit positions, the means for verifying using the first, second, and third memory data arrays for verifying the N test vectors in a parallel manner.

19. The test system of claim 16 wherein the means for verifying a test vector evaluates the circuit elements in the circuit model for clock cycle one and clock cycle two to obtain input and output values, the means for verifying performing logical operations on the input and output values of the circuit elements along the specific circuit path to determine whether the input and output values have valid input and output values for a predetermined logic transition of the specific circuit path, and identifying the logic path as being untestable if no test vector, which is in accordance with the test condition, correctly tests the specific speed path.

20. A method for testing test vectors, the method comprising the steps of:

(a) initializing an array structure for the test vectors which test a specified circuit, wherein the array structure has a first array, a second array, and a third array for each input and output of each circuit element in the specified circuit, the first array storing first test clock cycle logic values from the test vectors for each circuit element in the plurality of circuit elements, the second array storing second test clock cycle logic values from the test vectors for each circuit element in the plurality of circuit elements, the third array being used to store hazard-free status values as a function of the first and second arrays;

(b) setting a test clock cycle value to one;

(c) loading the test vectors into the array structure for each input and output of each circuit element in the plurality of elements;

(d) loading the values of the test vectors into the first, second, and third arrays for each circuit element which is a scan flip-flop if the test clock cycle has a value of one;

(e) copying the input values stored in the first array of each circuit element which is coupled to the input of the each scan flip-flop to the second array of each of the respective scan flip-flops;

(f) simulating the specified circuit to obtain logic values for the first clock cycle which are stored in the first array;

(g) increasing the test clock cycle value to a value of two;

(h) simulating the specified circuit to obtain logic values for the second clock cycle which are stored in the second array;

(i) detecting path delay information for the specified circuit using the first and second arrays; and

(j) checking for more input test vectors which test the specified circuit, repeating steps (a) through (j) until no test vectors remain to be verified.

21. The method of claim 20 wherein the step (f) circuit further comprises:

checking for the circuit elements within a list of circuit elements for the specified circuit;

popping at least one circuit element from the list of circuit elements for the specified circuit; and

evaluating the at least one circuit element by performing at least one logical operation on at least one first array to form new input and output values for the first array;

comparing previous input and output values in the first array with the new input and output values in the first array structure; and

inserting all fan-out elements into the list of circuit elements for the specified circuit, the fan-out elements being all circuit elements coupled to the output to the at least one circuit element.

22. The method of claim 21 wherein the step (h) circuit further comprises:

checking for the circuit elements within a list of circuit elements for the specified circuit;

popping at least one circuit element from the list of circuit elements for the specified circuit; and

evaluating the at least one circuit element by performing at least one logical operation on at least one second array to form new input and output values for the second array;

comparing previous input and output values in the second array structures with the new input and output values in the second array structures; and

inserting all fan-out elements into the list of circuit elements for the specified circuit, the fan-out elements being all circuit elements coupled to the output of the at least one circuit element.

23. The method of claim 22 further comprising:

computing steady flags from the first and second arrays which are stored in the third array for the at least one circuit element.

24. The method of claim 20 wherein the step (i) further comprises:

(k) setting a detection word to a value of all ones;

(l) computing a FLAG word for detecting a valid transition at a head of a circuit path;

(m) performing bitwise ANDing of the FLAG word with the detection word to get a result and storing the result in the detection word;

(n) checking if the detection word has a value of zero to determine if the path in the specified circuit is untestable;

(o) checking for more circuit elements in the circuit path, and determining a selected circuit element by selecting a circuit element from the circuit path if more circuit elements are along the circuit path;

(p) setting the FLAG word to a value of zero if more circuit elements are in the circuit path to determine if an output for an element along the circuit path is valid for the circuit path;

(q) setting a TOKEN word to a value of all ones if the selected circuit element has more inputs than the input on the circuit path;

(r) checking for other inputs to the selected circuit element which are not on the circuit path;

(s) computing a MASK word for an input for the selected circuit element which is not directly on the circuit path if other inputs exists other than the input on the circuit path;

(t) performing bitwise ANDing with the MASK word and the TOKEN word;

(u) repeating steps (s) and (t) until all inputs to the selected circuit element which are not on the circuit path have been accessed;

(v) performing bitwise ORing with the TOKEN word and the FLAG word to determine if the output of the selected circuit element from the list of circuit elements is valid;

(w) repeating steps (m) through (w) until no more circuit elements are left in the list of circuit elements; and

(x) using the detection word to determine which test vectors detect path delay faults along the circuit path.

25. The method of claim 20 wherein the specific circuit contains a custom logic block which is tested by the test vectors.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates generally to data processing systems, and more particularly, verification of circuit test vectors for circuit path delay testing.

BACKGROUND OF THE INVENTION

The prior art in path-delay testing dates to 1985, with the definition of a delay model based on path delay faults. This delay model based on path delay faults taught algorithms to generate tests for path-delay faults in combinational logic circuits. Due to the fact that nobody actually produces purely combinational circuits any more, the only way for these algorithms to be applied to a real circuit is essentially to double each memory device in the circuit so that it can store the two patterns (first clock cycle pattern and second clock cycle pattern) required for the path-delay test as completely independent patterns. This would roughly double the size of the memory portion of the circuit (the section 12 of FIG. 1), which no price-competitive manufacturer is willing to do. As a consequence, all these prior combinational logic approaches to path-delay testing remain largely academic exercises which cannot be used in modern integrated circuit design.

Test generation methods that could be applied to path-delay faults in standard scan sequential circuits first began to appear in 1991. These methods were the first to make feasible the path-delay testing of real circuits. Unfortunately, the methods described in all known papers/publications/patents that target standard scan sequential circuits used a simplified logic algebra that did not include hazard-free values. A hazard-free being a logic value that is to remain at the same logic level and is free of any timing glitches. As a consequence, the methods are unable to target robust tests, which means that any tests they generate may be invalidated or incorrect due to timing problems or voltage glitches in other parts of the circuit. In other words, by not using hazard-free values, a time delay fault may be inaccurately detected when a time delay fault really didn't occur or vice versa, an actual time delay fault could go unreported due to a static timing hazard or glitch. A recent testing method claims to be able to generate robust tests for general sequential circuitry, including standard scan sequential circuits. The absence of certain necessary logic values, however, means that this algorithm is defective and may declare a path untestable even when a robust test exists. None of the prior art provides an error-free method for generating robust tests for standard scan sequential circuitry.

Also in the modern integrated circuit industry, the use of the Boolean difference has not been possible in the generation of robust path-delay tests through custom logic blocks whose structure is not specified, due to the fact that any data structure used for Boolean differences requires huge amount of physical memory to represent the Boolean difference data.

Furthermore, in the modern integrated circuit industry, a stuck-at fault simulation methodology is based on the (PPSFP) Parallel-Pattern Single-Fault Propagation method. The PPSFP method has not been applied to general sequential circuits, due to the intrinsic inefficiencies encountered in simulating sequential devices and feedback loops across multiple clock cycles in such circuits. Thus, when applying the PPSFP method for fault simulation testing, combinational circuits are used for the test simulation.

However, the usual PPSFP method cannot be used for delay fault testing, due to the fact that the PPSFP method assumes the independence of each pattern and that circuit activity ceases when a single pattern has been processed. Since all delay tests are multi-pattern tests, any application of the standard PPSFP method to the simulation of such tests would be non-functional. Furthermore, in a standard scan path testing environment, a second test vector comes from the functionality of the circuit rather than being directly and independently loaded from an external source.

Current simulators for delay faults are built on either a PPSFP with the added assumption of an enhanced scan design methodology, rendering them incapable of being used for a standard scan design environment, or concurrent fault simulators for general sequential logic, which renders them very inefficient compared to PPSFP methods. Furthermore, current simulators lack the ability to support multiple clock cycles and hazard free value testing, thus a path-delay test verification process in a standard scan design environment cannot be accomplished.

Also, the generation of test vectors to circuit path delay testing can be a complex matter. Therefore, the code used to generate the test vector may have a "bug" or be erroneous and generate a vector which may not function properly to test a path. Therefore, a need exists to both generate a test vector using a first method and verify the correctness of the test vector using a second method wherein errors in the first method are not likely to occur again in the second method.

SUMMARY OF THE INVENTION

The previously mentioned disadvantages are overcome and other advantages achieved with the present invention. The invention comprises a method for verifying a test vector for a logic circuit. The method begins by providing the test vector to a test verifier wherein the test vector is generated to test a specific circuit path within an electrical circuit. The test of the specific circuit path giving electrical propagation time delay information for the specific circuit path. The test vector defining input values which logically affect the specific circuit path for a first test clock cycle and identifying input values which logically affect the specific circuit path for a second test clock cycle. Providing to the test verifier a circuit model which models the operation of the electrical circuit. Generating input values and output values for all circuit elements along the specific circuit path for both the first test clock cycle and the second test clock cycle by accessing the circuit model and the test vector. Performing logical operations on the input and output values of the circuit elements along the specific circuit path to determine whether the test vector, as input to the test verifier, correctly tests the specific speed path.

In another form, the invention comprises a test system for generating and verifying the functionality of a speed path test vector. The test system comprising a medium for modeling, a medium for providing, and a medium for verifying. The medium for modeling being used to model the operation of an electrical circuit having a circuit path. The medium for providing being used to provide a test vector for testing a propagation speed of the circuit path. The test vector defining input values and output values along the circuit path defined via the medium for modeling. The input and output values having a first set of values defined for a first test clock cycle and a second set of values defined for a second test clock cycle. The test vector being generated by a first process within the medium for providing. The medium for verifying being used to verify the test vector receiving the test vector from the medium for providing. The medium for verifying accessing the circuit model and simulating the test vector within a portion of the circuit model to verify that the test vector correctly tests the circuit path for the propagation speed. The verification using a second process which is different from the first process.

The present invention will be more clearly understood from the detailed description below in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in a block diagram, a circuit which can be path delay tested in accordance with the present invention;

FIGS. 2-5 illustrate, in block diagrams, a specific circuit which may be path delay tested and how test logic values are determined within the specific circuit in accordance with the present invention;

FIG. 6 illustrates, in a flowchart, a method for generating a test vector which is used to test a delay path in an electrical circuit in accordance with the present invention;

FIG. 7 illustrates, in a flowchart, several specific steps involved when setting logic constraints as illustrated in FIG. 6 in accordance with the present invention;

FIG. 8 illustrates, in a flowchart, several specific steps which are involved when justifying hazard-free logic values as illustrated in FIG. 6 in accordance with the present invention;

FIG. 9 illustrates, in a flowchart, several specific steps which are involved when justifying values for a second clock cycle as illustrated in FIG. 6 in accordance with the present invention;

FIG. 10 illustrates, in a flowchart, several specific steps which are involved when justifying values for a first clock cycle as illustrated in FIG. 6 in accordance with the present invention;

FIG. 11 illustrates, in a block diagram, a data processing system which may be used to both path delay test an integrated circuit and verify a path delay test for an integrated circuit in accordance with the present invention;

FIG. 12 illustrates, in a block diagram, a circuit that contains a custom logic block, which is a block of elements that is described by its functional equation in accordance with the present invention;

FIG. 13 illustrates, in a block diagram, a circuit diagram describing the custom logic block 210 of FIG. 12 in further detail in accordance with the present invention;

FIG. 14 illustrates, in a flow chart, several specific steps that describe the process in building the internal data structure to describe or represent the control logic block 210 of FIG. 12 in accordance with the present invention;

FIG. 15 illustrates, in a flowchart, a method for generating a test vector which is used to test a delay path in an electrical circuit in accordance with the present invention;

FIG. 16 illustrates, in a flowchart, several specific steps involved when setting logic constraints for custom logic blocks as illustrated in FIG. 15 in accordance with the present invention;

FIG. 17 illustrates, in a flowchart, several specific steps that describe building another part of the data structure that represents a custom logic block that is directly in the delay path in accordance with the present invention;

FIG. 18 illustrates, in a flowchart, several specific steps that describe the process for finding the next Boolean difference set in accordance with the present invention;

FIG. 19 illustrates, in a flowchart, several specific steps which are involved when justifying hazard-free logic values for standard logic devices and/or custom logic blocks as illustrated in FIG. 15 in accordance with the present invention;

FIG. 20 illustrates, in a flowchart, several specific steps which are involved when backtracing input devices whose logic values may be set to produce the needed value back to a circuit input or memory element in accordance with the present invention;

FIG. 21 illustrates, in a flowchart, several specific steps which are involved when tracing a custom logic block whose logic values may be set to produce the needed value back to a circuit input or memory element in accordance with the present invention;

FIG. 22 illustrates, in a flowchart, several specific steps that describe how to handle a Boolean difference conflict in accordance with the preset invention;

FIG. 23 illustrates, in a flowchart, several specific steps which are involved when justifying values for a second clock cycle as illustrated in FIG. 15 in accordance with the present invention;

FIG. 24 illustrates, in a flowchart, several specific steps which are involved when justifying values for a first clock cycle as illustrated in FIG. 15 in accordance with the present invention;

FIG. 25 diagrammatically illustrates, a bit pattern data structure for an element in accordance with the present invention.

FIGS. 26-39 illustrate, in block diagrams, a specific circuit which is undergoing the test verification process by generating input and output bit patterns for all circuit elements along the specific circuit path for both the first test cycle and the second test cycle in accordance with the present invention;

FIG. 40 illustrates, in a flowchart, several specific steps which describe the process for performing a test verification process in accordance with the present invention;

FIG. 41 illustrates, in a flowchart, several specific steps which describe in more detail the process of simulating the test circuit as illustrated in FIG. 40 in accordance with the present invention; and

FIG. 42 illustrates, in a flowchart, several specific steps which describe in more detail process for determining which patterns provide robust tests for detecting path delay faults in a given circuit path as illustrated in FIG. 40 in accordance with the present invention.

It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the FIGURES have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the FIGURES to indicate corresponding or analogous elements.

DESCRIPTION OF A PREFERRED EMBODIMENT

Generally, the present invention provides both a method and an apparatus to perform robust path-delay test verification of an integrated circuit. A circuit path refers to a connected series of elements of an integrated circuit, with the first element in the series referred to as the head of the path and the last element in the series referred to as the tail of the path. A path delay refers to the time required for a logic value change on the head of the path to cause a logic value change on all other elements in the circuit path up to the tail of the path. The speed at which an integrated circuit can work is determined by the largest of the path delays (most time consuming) in the entire integrated circuit. A timing error for such a circuit path is said to have occurred when a path delay exceeds the system clock cycle, which is the amount of time required for the system clock for the integrated circuit to go through one complete period. When a circuit path shows such a timing error, the circuit path is said to possess a path delay fault. A robust test for a path delay fault is a test that guarantees that the circuit response will differ from the expected/passing response whenever the path possesses a path delay fault, regardless of the presence or absence of path delay faults on other circuit paths.

For example, assume that a circuit path comprises a first scannable flip-flop which has an output coupled to an input of an AND gate wherein the AND gate has an output coupled to an input of a second scannable flip-flop. The first and second scannable flip-flops (and any clocked component/circuit in the integrated circuit which contains the first and second scannable flip-flops) are clocked at a predetermined speed by applying a clock signal to the integrated circuit. In order to test this example circuit path, an initial logic value is scanned into a flip-flop preceding the first scannable flip-flop or is provided to an input pin to allow a logic value A to appear on the input of the first scannable flip-flop. This logic value A will not propagate to the output until the first scannable flip-flop is clocked. Also, an initial logic value B is provided at the output of the second scannable flip-flop. Assume for the sake of example that A=0 and B=1, although any combination of values may occur for any type of circuit path.

Various signals are set or predetermined (as discussed herein) along the circuit path to ensure that when A=0 is clocked into the first scannable flip flop via a first clock cycle that the value A=0, when applied down the circuit path, results in B=1 changing to B=0 at a second clock cycle. Therefore, the A=0 has just one clock cycle from the time it is latched into the first scannable flip-flop to propagate down the circuit path and change B from a logic `1` to a logic `0`. If B stays a logic `1` after assertion of the second clock cycle, then the A=0 signal did not propagate through the circuit path in time to affect the second scannable flip-flop. This indicates that the clock speed is too fast for this circuit path (i.e. signals are not arriving at critical clocked inputs before the clocking is occurring). If the signal B is changed to a `0` from a `1` then the circuit path can properly operate at the current clock cycle and under current conditions.

Therefore, for every circuit path in an electrical circuit or integrated circuit, one can determine that a path X is operable up to 47 MHz, path Y is operable up to 113 MHz, and Z is operable up to 80 MHz. This information can then be used to determine what clock speed is maximal for a given circuit or may be used to determine which exact circuit paths need to be redesigned to achieve a higher clock speed for a circuit. For example, if the circuit described above was to run at 60 MHz, path X would be a problem and most likely would require redesign, a new layout, or different manufacturing/processing.

The method of the present invention operates on a circuit model of an integrated circuit (usually a computer simulated model of an integrated circuit) and a database which identifies various circuit paths of this circuit model. The circuit model must be a circuit model in which all circuit memory elements are scannable flip-flops. A circuit path is selected from the set of circuit paths and a set of logic value constraints for elements of the circuit model that are required to achieve a path-delay test are determined. Some of these logic value constraints, referred to as hazard-free logic values, may be required to be free of timing hazards. Logic values which cause these hazard-free logic values to be produced in the circuit model are determined first. Next, logic values to cause logic value constraints for the second clock cycle to be produced in the circuit model are determined. Finally, logic values to cause logic value constraints for the first clock cycle to be produced in the circuit model are determined. A test vector comprises the logic values on input terminals for the integrated circuit and on the scannable flip-flops for both the first clock cycle and the second clock cycle is generated after all logical values have been set for both clock cycles one and two.

The present invention overcomes many of the disadvantages stated in the background and can be more fully understood with reference to the FIGS. 1-42 herein. In summary, the present invention is a method of verifying a plurality of test vectors. The number of patterns needed for path-delay testing in a standard scan environment is known in advance to be exactly two. Therefore, the internal data structure of a test vector verifier is a two-item bit word array allowing the storage of circuit values for both clock cycles needed for a single test. This allows each bit in a machine word, where the machine word is the maximum amount of bits a system can process at a time, to store a separate test pattern. The input values of the test vector are loaded into the internal data structure for the test vector verifier for the first test clock cycle and the second test clock cycle. The test vector verifier proceeds by loading the values for clock cycle one on the scan flip-flops, and loading the values for both clock cycle one and clock cycle two on circuit inputs. Next, the test vector verifier generates input values and output values for all circuit elements along the specific circuit path for both the first test clock cycle and the second test clock cycle by accessing the circuit model, which is a model of the circuit being tested, and the internal data structure of the test vector verifier. In addition to the standard techniques for element evaluation, the fault simulation method computes a hazard-free-value flag during processing of the second clock cycle, thus enabling simulation of robust and hazard-free path delay tests. Finally, the paths under test are simulated in a serial fashion. For each path simulated, a resulting output is produced indicating which pattern or plurality of patterns provide robust tests for the given path.

FIG. 1 generally illustrates a portion of an integrated circuit having a set of scannable flip-flops 12 (i.e., storage devices) and a combinational logic section 10. FIG. 1 also illustrates input values which may come from other storage devices (i.e. scannable flip-flops) or integrated circuit input terminals (input pins). Output values are provided to storage devices or to external terminals (output pins) of the integrated circuit. A circuit path to be tested in this portion of an integrated circuit could consist of: (1) a connected series of circuit elements beginning with a circuit input terminal, containing at least one of the logic devices in the combinational logic section 10, and ending with an external terminal of the integrated circuit, (2) a connected series of circuit elements beginning with a storage device, containing at least one of the logic devices in the combinational logic section 10, and ending with an external terminal of the integrated circuit, (3) a connected series of circuit elements beginning with a circuit input terminal, containing at least one of the logic devices in the combinational logic section 10, and ending with a storage device, or (4) a connected series of circuit elements beginning with a storage device, containing at least one of the logic devices in the combinational logic section 10, and ending with a storage device.

Although FIG. 1 illustrates a generic type of circuit which may be tested a specific example is most useful in understanding the path delay method discussed herein. FIGS. 2 through 5 illustrate a specific circuit which may be used to determine path delays. The scannable flip-flops 20, 22, and 24 correspond to the set of scannable flip-flops 12 of FIG. 1. The combinational logic devices 14, 16, 18, 26, 28, and 30 correspond to the combinational logic section 10 of FIG. 1. The example of a circuit path to be tested in this circuit is the path beginning with scannable flip-flop 24, the head of the path, containing combinational logic devices 28 and 30, and ending at the output to a scannable flip-flop or output terminal, the tail of the path. A test for a path delay fault on this circuit path must first establish the initial value on the head of the path, scannable flip-flop 24 (an initial value being output from flip-flop 24 which may be serially scanned into 24). After a first clock cycle, the first time interval in which the system clock for the integrated circuit goes through one complete period following the establishment of the initial value on the head of the path, the second value for the head of the path has been clocked into the storage element from the input (from inverter 18). After a second clock cycle, the second time interval in which the system clock for the integrated circuit goes through one complete period following the establishment of the initial value on the head of the path, the response value for the tail of the path has either been clocked into a storage element flip-flop or simply provided to the output terminal as indicated in FIG. 1. FIG. 2 illustrates the logic values that are necessary on the inputs and outputs of circuit devices on the example path in order to achieve a robust test of the example circuit path. These logic values are selected from the logic value set that has been designed to be used for test generation for path delay faults. This logic value set is given in TABLE 1 below.

TABLE 1 __________________________________________________________________________ LOGIC LOGIC VALUE VALUE FOR FOR FIRST SECOND LOGIC CLOCK CLOCK VALUE CYCLE CYCLE ADDITIONAL INFORMATION __________________________________________________________________________ 00 0 0 Not guaranteed hazard-free but can be made into S0 01 0 1 Rising transition for path test 0Y 0 Y Y represents both Z and signals constrained to X 0X 0 X Can be made into S0 10 1 0 Failing transition for path test 11 1 1 Not guaranteed hazard-free but can be made into S1 1Y 1 Y Y represents both Z and signals constrained to X 1X 1 X Can be made into S1 Y0 Y 0 Y represents both Z and signals constrained to X Y1 Y 1 Y represents both Z and signals constrained to X YY Y Y Y represents both Z and signals constrained to X YX Y X Y represents both Z and signals constrained to X X0 X 0 Can be made into S0 X1 X 1 Can be made into S1 XY X Y