Bi-directional programmable I/O cell

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BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the transmission, biasing and termination of digital data. More particularly, the present invention presents an I/O cell with programmable active input bias.

2. Description of the Related Art

Today, most electronic systems and many electronic devices (e.g. multichip modules or MCMs) contain several integrated circuits or ICs. Most IC die are comprised of core electronics at its center and input/output electronics, or an I/O ring at its periphery. The core electronics usually perform the primary function of the IC while the I/O ring provides a buffered external interface.

The I/O ring is typically comprised of several (sometimes hundreds) of I/O cells, one for each external signal of the IC. The I/O ring may contain several I/O cell types (e.g. input cells, output cells, tristate output cells and bi-directional cells), one for each external signal type. The transistors of the I/O ring are much larger than those of the core electronics. The core electronics drive devices are contained entirely within the IC die, while the I/O cells typically drive the an external media or devices external to the IC die. Depending on the particular application, the external media is typically referred to as an interconnect, a net, a backplane, a bus, or a bi-directional data line.

I/O cells of different ICs can have different electronic operating characteristics. When two or more I/O cells of different ICs are connected together through a media, the connecting net often requires some form of biasing (pull-up or pull-down) and/or termination to ensure the error-free operation of all the connected I/O cells.

For example, some nets connect a TTL output cell to a CMOS input cell. Such a net requires a pull-up resistor to ensure that the TTL logic high output voltage exceeds the logic high switching threshold voltage of the CMOS input.

Similarly, biasing is typically required in a net connecting two or more tristate output or bi-directional cells. Such a net may require a pull-up or a pull-down resistor to ensure that the net voltage is at a valid logic level when none of the connected I/O cells are driving.

Biasing is also required in nets having physically long trace lengths, such as I/O cells connected across a backplane. When twice the propagation delay of the connecting trace exceeds the edge rates (output rise and fall times) of the connected I/O cells, that trace must be treated like a transmission line. Transmission line effects, such as ringing, overshoots and undershoots, result from I/O driver loading by the characteristic impedance, identified as Z.sub.O, of the connecting trace and signal reflections off impedance discontinuities along the length and especially at the ends of the trace. Such effects can cause data signals to inadvertently cross logic thresholds, which is detrimental or even fatal to device operation.

To minimize these effects, terminations are required at one or both ends of the trace. Terminations have been designed to provide an impedance that closely matches the characteristic impedance of the trace, thus reducing the effective impedance discontinuities and thereby reducing reflections.

As circuit complexity, clock frequencies and edge rates have increased, the number of interconnects requiring biasing and/or termination has increased. Unfortunately, implementing bias and termination requirements with discrete components at the MCM or printed wiring assembly (PWA) level can consume a considerable amount of valuable multichip package (MCP) and/or primed wiring board (PWB) area resulting in increased system size, weight, power requirements and cost.

Currently, some ICs utilize fixed I/O cell biasing at the wafer-level. This biasing usually consists of a single bias resistor with one end tied to the external port of the I/O pad to be biased and the other end tied to a fixed DC level, either power or ground. Unfortunately, The use of fixed wafer-level biasing has been limited because of the varying and often conflicting application dependent bias requirements at the MCM, PWA and/or system levels.

SUMMARY OF THE INVENTION

A bi-directional programmable I/O cell is disclosed. The bi-directional programmable I/O cell has variable electrical characteristics which are selected via control inputs. The variable electrical characteristics can include a data transmission mode, an input bias impedance value and an input bias direction mode. The input bias direction mode has an independent submode and a dependent submode. The dependent submode can operate in a ring latch mode or an active termination mode. The independent submode is further comprised of a static submode and a dynamic submode. The static submode is further comprised of a pull-up mode and a pull-down mode. The bias impedance value is can be selected from a plurality of impedances. The bi-directional programmable I/O cell has a continuous or pulsed output in the data transmission mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a CMOS bi-directional I/O cell.

FIG. 2 is a schematic diagram of a bi-directional I/O cell having multiple programmable active input biases.

FIG. 3 is a schematic diagram depicting a gate-level implementation of a controller used in a bi-directional I/O cell having multiple programmable active input biases.

FIG. 4 is a schematic diagram depicting multiple bi-directional programmable I/O cells with common input bias and data output control busses.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 schematically depicts a CMOS bi-directional I/O cell 100 connected between a core 180 and an external interconnect 190. I/O cell 100 is comprised of a controller 110, an output drive block 120, a bias block 130 and an input protection block 140. Controller 110 has an IN port 101, an OUT port 102, an OE port 103, an IO port 104, an OH port 105 and an OL port 106. Table 1 provides a description of the aforementioned ports and describes whether controller 110 receives an input signal from the port (input) or transmits an output signal from the port (output).

TABLE 1 ______________________________________ Controller 110 Ports Port Description Type ______________________________________ IN port 101 Data input from core Input OUT port 102 Data output to core Output OE port 103 External output enable Input IO port 104 External data input Input OH port 105 Pull-up transistor control Output OL port 106 Pull-down transistor control Output ______________________________________

In the preferred embodiment, output drive block 120 is comprised of a p-channel pull-up transistor 121 and an n-channel pull-down transistor 122 arranged in a totem-pole configuration. The source of pull-up transistor 121 is connected to a positive supply 150 and the drain is connected to external interconnect 190. The drain of pull-down transistor 122 is connected to external interconnect 190 while the source is connected to negative supply 160. The gate of pull-up transistor 121 is connected to OH port 105, while the gate of pull-down transistor 122 is connected to OL port 106. The digital signals on OH port 105 and OL port 106 can be referred to as drive block control signals. Table 2 is a truth table describing the output state of drive block 120, based on the logic levels of the signals at OH port 105 and OL port 106 and the corresponding operation of transistors 121 and 122.

TABLE 2 ______________________________________ Truth Table for Drive Block 120 Inputs (Drive Block Control Signals) Pull-up Pull-down OH OL Transistor Transistor Output port 105 port 106 121 122 State ______________________________________ 0 0 On Off High drive 0 1 Not allowed Not allowed 1 0 Off Off No drive 1 1 Off On Low drive ______________________________________ 0 = logic low, 1 = logic high

In the preferred embodiment, bias block 130 is comprised of a pull-up resistor 131 and a pull-down resistor 132. Pull-up resistor 131 is connected between the positive supply 150 and external interconnect 190, while pull-down resistor 132 is connected between external interconnect 190 and the negative supply 160. One skilled in the art will recognize that a weak transistor can be substituted for resistors 131 and 132. Bias block 130 ensures that the voltage on external interconnect 190 is pulled to a valid logic level when transistors 121 and 122 are off.

In the preferred embodiment, input protection block 140 is comprised of a positive clamp diode 141 and a negative clamp diode 142. The anode of the positive clamp diode 141 and the cathode of the negative clamp diode 142 are connected to external interconnect 190. The cathode of the positive clamp diode 141 is connected to the positive supply 150, while the anode of the negative clamp diode 142 is connected to the negative supply 160. Diodes 141 and 142 clamp the voltage on external interconnect 190 to one diode drop above and below the positive and negative supplies, respectively.

I/O cell 100 exchanges data between core 180 and external interconnect 190. Thus, I/O cell 100 has an output data path from core 180 to IN port 101 to OH port 105 and OL port 106, which correspondingly controls transistors 121 and 122 which, in turn, drive external interconnect 190 to a voltage. Similarly, I/O cell 100 has an input data path from external interconnect 190 to IO port 104 to OUT port 103 to core 180.

Controller 110 performs the logic function described by the truth table depicted in Table 3. One skilled in the art will recognize how to construct the circuitry needed to perform the described function. It should be noted that OH port 105 and OL port 106 drive the gates of p-channel transistor 121 and n-channel transistor 122, respectively, and are a function of the logical signals on IN port 101 and OE port 103. The logical signal on OUT port 102 is a buffered version of the logical signal on IO port 104.

TABLE 3 ______________________________________ Truth Table for Controller 110 Inputs Outputs IN OE IO OH OL OUT ______________________________________ 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 ______________________________________ 0 = logic low, 1 = logic high

FIG. 2 schematically depicts a bi-directional programmable I/O cell 200. It should be noted that components having the same function as described in FIG. 1 have retained the same numerical identification. Bi-directional programmable I/O cell 200 is comprised of a controller 210, a drive block 220 and an input protection block 140.

Controller 210 has an OEM port 201, an OEH port 202, an OEL port 203, an IN port 101, an OUT port 102, a BD port 206, a BM port 207, at least two B ports 208.sub.1 and 208.sub.N, at least two OH ports 105.sub.1 and 105.sub.N an I/O port 104 and at least two OL ports 106.sub.1 and 106.sub.N. Table 4 provides a description of the aforementioned ports and describes whether controller 210 receives an input signal from the port (input) or transmits an output signal from the port (output). In the preferred embodiment, all of the input signals, except for the signal on IO port 104, are generated by core 180.

TABLE 4 ______________________________________ Controller 210 Ports Name Description Type ______________________________________ OEM 201 External data output enable mode select Input OEH 202 External data output enable -- active high Input OEL 203 External data output enable -- active low Input IN 101 Data input from core Input OUT 102 Data output to core Output BD 206 Input bias default select Input BM 207 Input bias mode select Input B(N:1) 208 Multiple input bias impedance select Input OH.sub.N 105.sub.N Control for pull-up transistor 221.sub.N Output IO 104 External data input Input OL.sub.N 106.sub.N Control for pull-down transistor 222.sub.N Output ______________________________________

In this particular embodiment, drive block 220 is comprised of one or more p-channel pull-up transistors 221.sub.N and n-channel pull-down transistor 222.sub.N, arranged in totem pole pairs. The gate of pull-up transistor 221.sub.1 is connected to the OH.sub.1 port 105.sub.1 of controller 210, while the gate of pull-down transistor 222.sub.1 is connected to the OL.sub.1 port 106.sub.1 of controller 210. Likewise, the gate of pull-up transistor 221.sub.N is connected to the OH.sub.N port 105.sub.N of controller 210, while the gate of pull-down transistor 222.sub.N is connected to the OL.sub.N port 106.sub.N of controller 210. The drains of all transistors 221 and 222 are connected to external interconnect 190. The sources of pull-up transistors 221 are connected to the positive supply 150, while the sources of all pull-down transistors 222 are connected to the negative supply 160.

As will be described, bi-directional programmable I/O cell 200 provides several alterable electrical characteristics, including a data transmission mode, either pulsed or continuous, a bias impedance value or magnitude and a bias direction, either independent or dependent. The input bias direction mode has an independent submode and a dependent submode. The dependent submode can operate in a ring latch mode or an active termination mode. The independent submode is further comprised of a static submode and a dynamic submode. The static submode is further comprised of a pull-up mode and a pull-down mode. The bias impedance value is can be selected from a plurality of impedances. The bi-directional programmable I/O cell has a continuous or pulsed output in the data transmission mode.

Input bias impedance and bias direction on external interconnect 190 are independently controlled. The input bias impedance is controlled by the bias select inputs, B(N:1) port 208.sub.N:1. If N=2, as many as four (2.sup.N) different bias impedances can be selected. In the preferred embodiment, four different impedances can be selected: 30 ohms, 50 ohms, 75 ohms and a high impedance. Transistors 221 and 222 are sized for an on-impedance of 50 ohms and transistors 221.sub.2 and 222.sub.2 are sized an on-impedance of 75 ohms. In the preferred embodiment, data transmission (output) mode impedance is 30 ohms.

The bias direction is controlled via BM port 207 and BD port 206 and OUT port 102. In the independent bias mode (i.e. BM=0), the bias direction tracks the independent logic level on BD port 206. Thus, if the BD port 206 is at a logic 0, external interconnect 190 is pulled low (i.e. to the negative supply) with the selected bias impedance. Likewise, if the BD port 206 is at a logic 1, external interconnect 190 is pulled high (i.e. to the positive supply) with the selected bias impedance. It should be noted that the logic level at BD port 206 can be either static or dynamic. Thus, if the logic level is dynamic, external interconnect 190 will track the logic level at BD port 206.

In the dependent input bias mode (i.e. BM=1), the bias direction tracks the logic level at OUT port 102, which is dependent on the logic level of I/O port 104, which is being biased. Thus, in dependent mode, the active bias behaves like a ring latch if the impedance of the selected bias impedance is high. A ring latch is useful on bussed nets that connect the outputs of multiple tristate drivers. A ring latch biases a net to its last driven logic state to ensure a valid logic level on the net even when all connected drivers are off (in a high impedance state). It should be noted that typically, an impedance between 1 k-ohms and 10 k-ohms is needed to operate in the ring latch mode.

If the magnitude of the selected bias impedance is close to the characteristic impedance of the connected trace, while bi-directional programmable I/O cell 200 is in the dependent input bias mode, the bias will be in active mode. An active bias behaves like an active transmission line termination. Such a termination has several advantages, including reduced energy consumption, faster logic transitions and reduced tinging effects. One such active termination is described in a co-pending application entitled "Termination Circuit for High Speed Applications", by Lance Sundstrom, Ser. No. 08/269,867, filed Jun. 30, 1994, and herein incorporated by reference.

OEM port 201 determines whether the data transmitted by programmable I/O cell 200 at external interconnect 190 is continuous (OEM=0) or pulsed (OEM=1). In a continuous data output mode, controller 210 activates all pull-up transistors 221.sub.N or all pull-down transistors 222.sub.N such that the logic level at external interconnect 190 is driven to the logic level at IN port 101 for as long as OEM port 201=0 and OEH port 202=1 and OEL port 203=0. In a pulsed data output mode, controller 210 turns on all pull-up transistors 221.sub.N or all pull-down transistors 222.sub.N such that the logic level at external interconnect 190 is driven to the logic level at IN port 101 if and for so long as OEM port 201=1 and OEH port 202=1 and OEL port 203=0 and IN port 101.noteq.OUT port 102.

As described, B port 208 provides N different programmable active input biases. In the interest of clarity, FIG. 2 shows only the first (N=1) and the last (N=N) portions of the bias circuitry. Furthermore, all of the truth tables will be defined for a system where N=2. From the description supplied herein, one skilled in the art will recognize how to construct a controller 210 and drive block 220 where N is greater than two.

The signal at OUT port 102 is a buffered version of the signal at the IO port 104. As described in Table 5, the remaining ports on controller 210 are functionally grouped into two sets of input ports, one set for input bias control and the other set for data output control, and a common set of output ports, for drive block control. Hereinafter, functional grouping of ports will be referred to as a control bus.

TABLE 5 ______________________________________ Input and Output Control Busses Functional Inputs Input Data Outputs Bias Control Output Control Drive Block Control ______________________________________ BM 207 OEM 201 OH.sub.N 105.sub.N BD 206 OEH 202 OL.sub.N 106.sub.N B(N:1) 208 OEL 203 OUT 102 IN 101 OUT 102 ______________________________________

The logical value at the ports will determine which of the two input control busses (input bias control or data output control) has active control of the output control bus (drive block control). The active control bus is selected based on the truth table defined in Table 6. At any given time, only one of the two input control busses will be in control.

TABLE 6 ______________________________________ Active Input Control Bus Select Truth Table OE OEH OEL IN OUT Controlling Bus ______________________________________ X X 1 X X Input Bias X 0 X X X Input Bias 0 1 0 X X Data Output 1 1 0 0 0 Input Bias 1 1 0 0 1 Data Output 1 1 0 1 0 Data Output 1 1 0 1 1 Input Bias ______________________________________ 0 = logic low, 1 = logic high, X = don't care

The drive block control outputs as a function of input bias control inputs and the resulting drive block 220 transistor states are defined by the truth table of Table 7.

TABLE 7 __________________________________________________________________________ Input Bias Mode Truth Table Control Inputs Control Outputs Drive Transistors BM BD B.sub.2 B.sub.1 OUT OH.sub.1 OL.sub.1 OH.sub.2 OL.sub.2 221.sub.1 222.sub.1 221.sub.2 222.sub.2 __________________________________________________________________________ X X 0 0 X 1 0 1 0 Off Off Off Off 0 0 0 1 X 1 1 1 0 Off On Off Off 0 0 1 0 X 1 0 1 1 Off Off Off On 0 0 1 1 X 1 1 1 1 Off On Off On 0 1 0 1 X 0 0 1 0 On Off Off Off 0 1 1 0 X 1 0 0 0 Off Off On Off 0 1 1 1 X 0 0 0 0 On Off On Off 1 X 0 1 0 1 1 1 0 Off On Off Off 1 X 0 1 1 0 0 1 0 On Off Off Off 1 X 1 0 0 1 0 1 1 Off Off Off On 1 X 1 0 1 1 0 0 0 Off Off On Off 1 X 1 1 0 1 1 1 1 Off On Off On 1 X 1 1 1 0 0 0 0 On Off On Off __________________________________________________________________________ 0 = logic low, 1 = logic high, X = don't care

The drive block control outputs are a function of the data output control inputs and the resulting drive block 220 transistor states are defined by the truth table of Table 8. The control block 210 contains the necessary digital logic gates to perform the functions of truth tables Table 6, Table 7 and Table 8.

TABLE 8 __________________________________________________________________________ Output Drive Mode Truth Table Control Inputs Drive Control Outputs Drive Transistors OE IN OUT OH.sub.1 OL.sub.1 OH.sub.2 OL.sub.2 221.sub.1 222.sub.1 221.sub.2 222.sub.2 __________________________________________________________________________ 0 0 X 1 1 1 1 Off On Off On 0 1 X 0 0 0 0 On Off On Off 1 0 1 1 1 1 1 Off On Off On 1 1 0 1 0 0 0 On Off On Off __________________________________________________________________________ 0 = logic low, 1 = logic high, X = don't care

Bi-directional programmable I/O cell 200 implements all input bias functions with transistors 221 and 222 and integrates both the input bias functions and the data output drive functions into drive block 220. Transistors 221 and 222 of the same totem pole transistor pair are sized for the same on-impedance for balance high and low on-impedances. Transistors 221 and 222 of different totem pole transistor pairs are sized for different on-impedances to allow for variable input bias impedance selection. It should be noted that bi-directional programmable I/O cell 200 can be implemented with any complimentary transistor technology, including GaAs, CMOS and bi-polar technologies.

FIG. 3 schematically illustrates the preferred gate-level implementation of controller 210. As before, components having the same function as described in the previous figures have retained the same numerical identification. Controller 210 is comprised of a buffer 720, two 2:1 (two-to-one) digital multiplexers 730a and 730b, a 2-input XOR gate 740, at least three 2-input AND gates 750.sub.1, 750.sub.N, and 755 having one inverting input, a 2-input OR gate 760 having one inverting input, a 2-input AND gate 770, at least two 2-input OR gates 780.sub.1 and 780.sub.N, and at least two 2-input NAND gates 790.sub.1 and 790.sub.N. As depicted, IO port 104 is connected to the input of buffer 720. OUT Port 102 is connected to the output of buffer 720, the first input of XOR gate 740 and to the 1-select data input of multiplexer 730a. IN port 101 is connected to the second input of XOR gate 740 and to the 1-select data input of multiplexer 730b. The output of XOR gate 740 is connected to the non-inverting input of OR gate 760. OEM port 201 is connected to the inverting input of OR gate 760. The output of OR gate 760 is connected to the first input of AND gate 770. OEH port 202 is connected to the non-inverting input of AND gate 755. OEL port 203 is connected to the inverting input of AND gate 755. The output of AND gate 755 is connected to the second input of AND gate 770. The output of AND gate 770 is connected to the first inputs of OR gates 780.sub.1 and 780.sub.N and to the select input of multiplexer 730b. BD port 206 is connected to the 0-select data input of multiplexer 730a. BM port 207 is connected to select input of multiplexer 730a. The data output of multiplexer 730a is connected to the 0-select data input of multiplexer 730b. The data output of multiplexer 730b is connected to the inverting inputs of AND gates 750.sub.1 and 750.sub.N and to the first inputs of NAND gates 790.sub.1 and 790.sub.N. B(N) port 208.sub.N is connected to the second input of OR gate 780.sub.N. B(1) port 208.sub.1 is connected to the second input of OR gate 780.sub.1. The output of OR gate 780.sub.N is connected to the second input of NAND gate 790.sub.N and to the non-inverting input of AND gate 750.sub.N. The output of OR gate 780.sub.1 is connected to the second input of NAND gate 790.sub.1 and to the non-inverting input of AND gate 750.sub.1. OL.sub.N port 106.sub.N is connected to the output of AND gate 750.sub.N. OL(1) port 106.sub.1 is connected to the output of AND gate 750.sub.1. OH(1) port 105.sub.1 is connected to the output of NAND gate 790.sub.1. OH(N) port 105.sub.N is connected to the output of NAND gate 790.sub.N.

FIG. 4 schematically depicts multiple bi-directional programmable I/O cells 200 having common control busses. Components having the same function as described in the previous figures have retained the same numerical identification. In this figure, only the first (x=1) and last (x=N) hi-directional programmable I/O cells 210.sup.x are shown. In order to have hi-directional programmable I/O cells 210.sup.x operate with common control busses, each port of each bi-directional programmable I/O cell 210.sup.x are electrically connected to the same port of the other bi-directional programmable I/O cells 210.sup.x, with the exception of IN ports 101.sup.x, OUT ports 10.sup.2x and I/O ports 104.sup.x.

Although only two bi-directional programmable I/O cells 200 have been shown, one skilled in the art will recognize that several bi-directional programmable I/O cells 200 can be connected in the manner described. This is particularly useful in devices designed to operate with a parallel data bus. Many data buses have either 32, 64 or 128 data lines. To effectively control such a bus, a separate bi-directional programmable I/O cell 200 is needed for each line.

Although the present invention has been described with reference to preferred embodiments, those skilled in the art will recognize changes that may be made in form or detail without departing from the spirit and scope of the invention. For example, this invention has described four different impedances (30 ohms, 50 ohms, 75 ohms and a high impedance) that could be placed on interconnect 190. Different impedance values could be selected depending on the specific application. It should also be noted that the number of impedances to select from could either be increased or decreased. One skilled in the art will realize that such a change may require the addition or removal of impedance enable lines, transistor totem pole pairs and logic circuitry.

Controller 210 can have several different embodiments without deviating from the scope and spirit of the invention. For example, the bias input control bus could be replaced with a serial bias control register. Multiple bias control registers could be loaded through a single serial scan port, such as an IEEE 1149.1 bus.

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