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Claims  |
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What is claimed is:
1. A video display apparatus, for use in a computer system, for
simultaneously displaying a plurality of video images on a display screen,
the apparatus comprising:
a plurality of video memories for storing a plurality of video signals,
respectively;
video control signal generation means for generating a plurality of
read-permit signals indicating times for reading said plurality of video
signals from said plurality of video memories, respectively;
memory control means for generating a plurality of read control signals
from said plurality of read-permit signals and for supplying said
plurality of read control signals to said plurality of video memories to
allow said plurality of video signals to be read out of said plurality of
video memories, said memory control means comprising means for generating
a plurality of clock signals which are different from each other and
respectively synchronous with said plurality of video signals read out of
said plurality of video memories;
selection signal generating means for generating a video selection signal
which indicates a change in selection of said plurality of video signals
at a plurality of positions on the display screen;
first selection means for selecting one of said plurality of video signals
in response to said video selection signal;
second selection means for selecting one of said plurality of clock signals
corresponding to the one of said plurality of video signals selected by
said first selection means in response to said video selection signal; and
display means including the display screen for displaying a video image as
a function of the one of said plurality of video signals and the one of
said plurality of clock signals selected by said first and second
selection means, respectively.
2. A video display apparatus as claimed in claim 1, wherein
said selection signal generating means comprises:
a memory, having a memory area corresponding to a specific area including a
plurality of pixels on the display screen, for storing video selection
data which indicates to select one of said plurality of video signals for
each of said plurality of pixels; and
control signal supply means for supplying a selection data read control
signal to said memory to read out said video selection data from said
memory as said video selection signal.
3. A video display apparatus as claimed in claim 2, wherein
said control signal supply means comprises a transmission path for
transmitting one of said plurality of read control signals to said memory
as said selection-data read control signal.
4. A video display apparatus as claimed in claim 1, wherein
said display means comprises a digital-to-analog converter for converting a
digital video signal selected by said selection means to an analog video
signal in response to said clock signal selected by said selection means.
5. A video display apparatus as claimed in claim 1, wherein
said plurality of video memories comprises a first video memory;
said video control signal generation means comprises means for generating a
first signal having a first period which corresponds to a scanning time
for one scanning line on the display screen of said display means; and
said memory control means comprises:
a first PLL circuit for generating from said first signal a first clock
signal having a period which is N1 times the first period of said first
signal, where N1 is an integer;
horizontal address generation means for generating a horizontal address for
said first video memory, said horizontal address generation means
comprising horizontal address update means for increasing said horizontal
address in response to each pulse of said first clock signal;
vertical address generation means for generating a vertical address for
said first video memory; and
address combining means for combining said vertical address and said
horizontal address to produce an address to be supplied to said first
video memory.
6. A video display apparatus as claimed in claim 5, further comprising:
a processor for executing arithmetic and logical operations; and
a bus for connecting said processor with said plurality of video memories
and connecting said processor with said memory control means; and wherein
said processor comprises means for changing a value of said integer N1 in
said first PLL circuit to scale a first video image in a horizontal
direction, said first video image being represented by a first video
signal read out of said first video memory.
7. A video display apparatus as claimed in claim 6, wherein
said video control signal generation means comprises means for generating a
second signal having a second period which corresponds to a scanning time
for one display screen of said display means; and
said memory control means further comprises:
means for generating from said first signal supplied from said video
control signal generation means a first scanning-line update signal
indicating a timing which corresponds to an end of one scanning line for
said first video signal read out of said first video memory; and
a second PLL circuit for generating from one of said first and second
signals a second scanning-line update signal having a period which is N2
times the second period of said second signal, where N2 is an integer; and
wherein
said horizontal address generation means comprises means for resetting said
horizontal address to a predetermined initial value in response to each
pulse of said first scanning-line update signal; and
said vertical address generation means comprises vertical address update
means for updating said vertical address by adding an address increase to
said vertical address in response to each pulse of said first
scanning-line update signal, said address increase being a product of an
address difference corresponding to a predetermined number of scanning
lines on said display screen and the number of pulses of said second
scanning-line update signal which are occurred between latest two pulses
of said first scanning-line update signal.
8. A video display apparatus as claimed in claim 7, wherein
said processor comprises means for changing a value of said integer N2 in
said second PLL circuit to scale said first video image in a vertical
direction.
9. A computer system comprising:
display means including a display screen for displaying a video image;
a plurality of video memories for storing a plurality of video signals,
respectively;
video control signal generation means for generating a plurality of
read-permit signals indicating times for reading said plurality of video
signals from said plurality of video memories, respectively;
memory control means for generating a plurality of read control signals
from said plurality of read-permit signals and for supplying said
plurality of read control signals to said plurality of video memories to
allow said plurality of video signals to be read out of said plurality of
video memories, said memory control means comprising means for generating
a plurality of clock signals which are different from each other and
respectively synchronous with said plurality of video signals read out of
said plurality of video memories;
selection signal generating means for generating a video selection signal
which indicates a change in selection of said plurality of video signals
at a plurality of positions on the display screen;
first selection means for selecting one of said plurality of video signals
in response to said video selection signal; and
second selection means for selecting one of said plurality of clock signals
corresponding to the one of said plurality of video signals selected by
said first selection means in response to said video selection signal,
wherein the video image displayed on said display screen is displayed as a
function of the one of said plurality of video signals and the one of said
plurality of clock signals selected by said first and second selection
means, respectively.
10. A method for simultaneously displaying a plurality of video images on a
display screen, the method comprising the steps of:
storing a plurality of video signals in a plurality of video memories;
generating a plurality of read-permit signals indicating times for reading
said plurality of video signals from said plurality of video memories;
generating a plurality of read control signals from said plurality of
read-permit signals;
supplying said plurality of read control signals to said plurality of video
memories to cause said plurality of video signals to be read out of said
plurality of video memories;
generating a plurality of clock signals which are different from each other
and respectively synchronous with said plurality of video signals read out
of said plurality of video memories;
generating a video selection signal which indicates a change in selection
of said plurality of video signals at a plurality of positions on the
display screen;
selecting one of said plurality of video signals in response to said video
selection signal;
selecting one of said plurality of clock signals corresponding to the one
of said plurality of video signals selected in response to said video
selection signal; and
displaying a video image as a function of said one of said plurality of
video signals and said one of said plurality of clock signals selected in
the selecting steps.
11. A method as claimed in claim 10, wherein
said step of generating the video selection signal comprises the steps of:
providing a memory, having a memory area corresponding to a specific area
including a plurality of pixels on the display screen, said memory being
arranged to store video selection data which indicates to select one of
said plurality of video signals for each of said plurality of pixels; and
supplying a selection-data read control signal to said memory to read out
said video selection data from said memory as said video selection signal.
12. A method as claimed in claim 11, wherein
said step of supplying the selection-data read control signal comprises the
step of transmitting one of said plurality of read control signals to said
memory as said selection-data read control signal.
13. A method as claimed in claim 10, wherein
said step of displaying the video image comprises the step of converting a
selected digital video signal to an analog video signal in response to
said selected clock signal.
14. A method as claimed in claim 10 wherein
said step of generating the plurality of read-permit signals comprises the
step of generating a first signal having a first period which corresponds
to a scanning time for one scanning line on the display screen; and
said step of generating the plurality of read control signals comprises the
steps of:
generating from said first signal a first clock signal having a period
which is N1 times the first period of said first signal, where N1 is an
integer;
generating a horizontal address for said first video memory, and increasing
said horizontal address in response to each pulse of said first clock
signal;
generating a vertical address for a first video memory of said plurality of
video memories; and
combining said vertical address and said horizontal address to produce an
address to be supplied to said first video memory.
15. A method as claimed in claim 14, further comprising the step of
changing a value of said integer N1 to scale a first video image in a
horizontal direction, said first video image being represented by a first
video signal read out of said first video memory.
16. A method as claimed in claim 15, wherein
said step of generating the plurality of read-permit signals comprises the
step of generating a second signal having a second period which
corresponds to a scanning time for one display screen of said display
means; and
said step of generating the plurality of read control signals further
comprises the steps of:
generating from said first signal a first scanning-line update signal
indicating a timing which corresponds to an end of one scanning line for
said first video signal read out of said first video memory; and
generating from one of said first and second signals a second scanning-line
update signal having a period which is N2 times the second period of said
second signal, where N2 is an integer; and
said step of generating the horizontal address comprises the step of
resetting said horizontal address to a predetermined initial value in
response to each pulse of said first scanning-line update signal; and
said step of generating the vertical address comprises the step of updating
said vertical address by adding an address increase to said vertical
address in response to each pulse of said first scanning-line update
signal, said address increase being a product of an address difference
corresponding to a predetermined number of scanning lines on said display
screen and the number of pulses of said second scanning-line update signal
which are occurred between latest two pulses of said first scanning-line
update signal.
17. A method as claimed in claim 16, further comprising the step of
changing a value of said integer N2 to scale said first video image in a
vertical direction. |
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Claims |
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Description |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and an apparatus for
simultaneously displaying a plurality of video images on a display screen
based on video signals stored in a plurality of video memories.
2. Description of the Related Art
FIGS. 34(A) through 34(C) show operation of a conventional video display
apparatus of a personal computer system. Some recent personal computers
can be operated by a plurality of operating systems (OS). FIG. 34(A) shows
a display screen operated by a first OS, or MS-WINDOWS (trademark of
Microsoft Corp.), where an image generated by a second OS, or MS-DOS
(trademark of Microsoft Corp.) is displayed in a window of the first OS.
FIGS. 34(B) and 34(C) show address spaces of these two operating systems.
In order to display an image generated by the second OS within a window of
the first OS in the conventional system, video data should be transferred
from a video memory (VRAM) of the second OS to another video memory
(A-VRAM) of the first OS as indicated by the arrow in FIGS. 34(B) and
34(C). Since the transfer of the video data is executed by a CPU, it
requires quite a long time and causes undesirable delay to the other
processing by the CPU. Such problems often arise when a plurality of video
memories are used in the video display apparatus.
SUMMARY OF THE INVENTION
An object of the present invention is thus to simultaneously display a
plurality of video images on a display screen according to video data
stored in a plurality of video memories without transferring the video
data among the video memories.
The above object is at least partly attained by a video display apparatus,
for use in a computer system, for simultaneously displaying a plurality of
video images on a display screen, comprising: a plurality of video
memories for storing a plurality of video signals, respectively; video
control signal generation means for generating a plurality of read-permit
signals indicating timings of reading of the plurality of video signals
from the plurality of video memory, respectively; memory control means for
generating a plurality of read control signals from the plurality of
read-permit signals, supplying the plurality of read control signals to
the plurality of video memories to allow the plurality of video signals to
be read out of the plurality of video memories, and generating a plurality
of clock signals which are respectively synchronous with the plurality of
video signals read out of the plurality of video memories; selection
signal generating means for generating a video selection signal which
indicates to change selection of the plurality of video signals at a
plurality of positions on the display screen; selection means for
selecting one of the plurality of video signals and one of the plurality
of clock signals in response to the video selection signal; and display
means having the display screen for displaying a video image as a function
of the video signal and the clock signal selected by the selection means.
The selection means selects one of the plurality of video signals and also
selects one of the plurality of clock signals corresponding to the
selected video signal. This allows a plurality of video images to be
displayed simultaneously and on the display screen according to video data
stored in the plurality of video memories without transferring the video
data among the video memories.
Preferably, the selection signal generating means comprises: a memory,
having a memory area corresponding to a specific area including a
plurality of pixels on the display screen, for storing video selection
data which indicates to select one of the plurality of video signals for
each of the plurality of pixels; and control signal supply means for
supplying a selection-data read control signal to the memory to read out
the video selection data from the memory as the video selection signal.
In a preferred embodiment of the present invention, the control signal
supply means comprises a transmission path for transmitting one of the
plurality of read control signals to the memory as the selection-data read
control signal.
The display means comprises a digital-to-analog converter for converting a
digital video signal selected by the selection means to an analog video
signal in response to the clock signal selected by the selection means.
According to an aspect of the present invention, the plurality of video
memories comprises a first video memory; and the video control signal
generation means comprises means for generating a first signal having a
first period which corresponds to a scanning time for one scanning line on
the display screen of the display means. The memory control means
comprises: a first PLL circuit for generating from the first signal a
first clock signal having a period which is N1 times the first period of
the first signal, where N1 is an integer; horizontal address generation
means for generating a horizontal address for the first video memory, the
horizontal address generation means comprising horizontal address update
means for increasing the horizontal address in response to each pulse of
the first clock signal; vertical address generation means for generating a
vertical address for the first video memory; and address combining means
for combining the vertical address and the horizontal address to produce
an address to be supplied to the first video memory.
In a preferred embodiment, the video display apparatus further comprises: a
processor for executing arithmetic and logical operations; and a bus for
connecting the processor with the plurality of video memories and
connecting the processor with the memory control means; and wherein the
processor comprises means for changing a value of the integer N1 in the
first PLL circuit to scale a first video image in a horizontal direction,
the first video image being represented by a first video signal read out
of the first video memory.
The video control signal generation means comprises means for generating a
second signal having a second period which corresponds to a scanning time
for one display screen of the display means. The memory control means
further comprises: means for generating from the first signal supplied
from the video control signal generation means a first scanning-line
update signal indicating a timing which corresponds to an end of one
scanning line for the first video signal read out of the first video
memory; and a second PLL circuit for generating from one of the first and
second signals a second scanning-line update signal having a period which
is N2 times the second period of the second signal, where N2 is an
integer. The horizontal address generation means comprises means for
resetting the horizontal address to a predetermined initial value in
response to each pulse of the first scanning-line update signal. The
vertical address generation means comprises vertical address update means
for updating the vertical address by adding an address increase to the
vertical address in response to each pulse of the first scanning-line
update signal, the address increase being a product of an address
difference corresponding to a predetermined number of scanning lines on
the display screen and the number of pulses of the second scanning-line
update signal which are occurred between latest two pulses of the first
scanning-line update signal.
The processor comprises means for changing a value of the integer N2 in the
second PLL circuit to scale the first video image in a vertical direction.
The present invention is also directed to a computer system comprising the
video display apparatus.
The present invention is further directed to a method for simultaneously
displaying a plurality of video images on a display screen. The method
comprises the steps of: providing a plurality of video signals stored in a
plurality of video memories, respectively; generating a plurality of
read-permit signals indicating timings of reading of the plurality of
video signals from the plurality of video memory, respectively; generating
a plurality of read control signals from the plurality of read-permit
signals, supplying the plurality of read control signals to the plurality
of video memories to allow the plurality of video signals to be read out
of the plurality of video memories, and generating a plurality of clock
signals which are respectively synchronous with the plurality of video
signals read out of the plurality of video memories; generating a video
selection signal which indicates to change selection of the plurality of
video signals at a plurality of positions on the display screen; selecting
one of the plurality of video signals and one of the plurality of clock
signals in response to the video selection signal; and displaying a video
image as a function of the selected video signal and the selected clock
signal.
These and other objects, features, aspects, and advantages of the present
invention will become more apparent from the following detailed
description of the preferred embodiment with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating a general structure of a computer
system having a video display apparatus embodying the invention;
FIGS. 2(A) through 2(D) illustrate memory areas of four video memory units
60 through 63 in terms of dimensions of display screens;
FIGS. 3(A) and 3(B) show an address map of operating systems utilizing the
four video memory units;
FIG. 4 shows a relation between a screen display on the color monitor 90
with read-permit signals VPIE and HPIE output from the video control
signal generator 80;
FIG. 5 is a block diagram illustrating the internal structure of the video
control signal generator 80;
FIGS. 6(a) through 6(k) are timing charts showing the operation of the
video control signal generator 80 in the horizontal direction;
FIGS. 7(a) through 7(k) are timing charts showing the operation of the
video control signal generator 80 in the vertical direction;
FIG. 8 is a block diagram illustrating the internal structure of the memory
control unit 71;
FIGS. 9(a) through 9(h) are timing charts showing the operation of the
memory control unit 71;
FIG. 10 is a block diagram illustrating the internal structure of a
waveform shaping unit 143;
FIG. 11 are timing charts showing the operation of the waveform shaping
unit 143;
FIG. 12 is a block diagram illustrating the internal structure of the first
video memory unit 61;
FIG. 13 is a block diagram illustrating the internal structure of the
memory 162 of FIG. 12;
FIG. 14 is a block diagram illustrating the internal structure of the
serial read control unit 161 of FIG. 12;
FIGS. 15(a) through (o) are timing charts showing the operation of the
serial read control unit 161;
FIGS. 16(A) through 16(C) conceptually show the relationship between
addresses of a memory and a display screen corresponding to the memory;
FIGS. 17(a) through 17(f) are timing charts showing the operation of the
serial read control unit 161 in vertical image expansion;
FIGS. 18(a) through 18(f) are timing charts showing the operation of the
serial read control unit 161 in vertical image compression;
FIGS. 19(A) and 19(B) show various settings of the memory control units and
the permit signal generator circuits when only a first video image is
displayed;
FIGS. 20(A) and 20(B) show various settings of the memory control units and
the permit signal generator circuits when a second video image is not
scaled and displayed totally;
FIGS. 21(A) and 21(B) show various settings of the memory control units and
the permit signal generator circuits when the second video image is not
scaled and displayed only partly;
FIGS. 22(A) and 22(B) show various settings of the memory control units and
the permit signal generator circuits when the second video image is
horizontally expanded and displayed totally;
FIGS. 23(A) and 23(B) show various settings of the memory control units and
the permit signal generator circuits when the second video image is
vertically expanded and displayed totally;
FIGS. 24(A) and 24(B) show various settings of the memory control units and
the permit signal generator circuits when the second video image is
vertically compressed and displayed totally;
FIG. 25 is a block diagram illustrating the internal structure of the
moving picture write control unit 74;
FIGS. 26(a) through 26(h) are timing charts showing the horizontal control
operation of the moving picture write control unit 74;
FIGS. 27(a) through 27(i) are timing charts showing the vertical control
operation of the moving picture write control unit 74;
FIG. 28 is a block diagram illustrating the internal structure of the
3-port video memory unit 63;
FIG. 29 is a block diagram illustrating the internal structure of the
3-port memory 263;
FIG. 30 is a block diagram illustrating the internal structure of the
serial write control unit 260;
FIGS. 31(a) through 31(k) are timing charts showing the operation of the
serial write control unit 260;
FIG. 32 is a block diagram showing another structure of the video signal
switching unit;
FIG. 33 is a block diagram showing another structure of the V-PLL unit; and
FIGS. 34(A) through 34(C) show the operation of a conventional video
display apparatus.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The preferred embodiment of the present invention will be described in the
following order:
A. Structure and Operation of Apparatus
B. Video Control Signal Generator
C. Memory Control Unit and Video Memory Unit
D. Various Settings in Video Image Scaling
E. Moving Picture Write Control Unit
F. 3-Port Video Memory Unit
G. Modifications
A. Structure and Operation of Apparatus
FIG. 1 is a block diagram illustrating the structure of a computer system
having a video display apparatus embodying the present invention. A CPU 50
is connected with a memory unit 60, first and second video memory units 61
and 62 and a 3-port video memory unit 63 via a CPU bus 52. The three video
memory units 61, 62, and 63 receive control signals output from first
through third memory control units 71, 72, and 73, respectively. Video
signals are serially read out of the video memory units 61, 62, and 63
according to the control signals. The first memory control unit 71
provides the control signal to the memory unit 60 as well as to the first
video memory unit 61. The memory unit 60 stores a multiplexing signal MPX
which is used to select one of the video signals read out of the three
video memory units 61 through 63. Structures and functions of the four
memory units 60 through 63 will be described later in detail.
The 3-port video memory unit 63 has a read port connected to the third
memory control unit 73, a first write port connected with the CPU bus 52,
and a second write port connected to a moving picture write control unit
74. The moving picture write-control unit 74 receives video data of moving
pictures supplied from a video signal separating/digitizing control unit
76 and a moving picture data decompression unit 78. The video signal
separating/digitizing control unit 76 divides a composite video signal,
which is supplied from a TV tuner or a video player, into synchronizing
signals and component video signals (RGB signals or YUV signals), and
converts the component video signals to digital video signals, and
supplies the digital video signals to the moving picture write-control
unit 74. The moving picture data decompression unit 78 decompresses
compressed video data stored in a CD-ROM, a hard disk, or a
magneto-optical disk, and transmits the decompressed video data to the
moving picture write-control unit 74. The moving picture write-control
unit 74 writes the supplied video data of moving pictures into the 3-port
video memory unit 63. An internal structure and operation of the moving
picture write-control unit 74 will be described in detail later.
The computer system is further provided with a video control signal
generator 80, a video signal switching unit 82, a clock signal switching
unit 84, three digital-to-analog converters (D-A converter) 86, three
amplifiers 88, and a color monitor 90. The video control signal generator
80 generates and supplies vertical read-permit signals VPIE1, VPIE2, and
VPIE3, and horizontal read-permit signals HPIE1, HPIE2, and HPIE3 to the
three memory control units 71 through 73 to instruct read-out timings of
video signals. The video signal switching unit 82 selects one of three
video signals RGB01, RGB02, and RGB03 read out of the three video memory
units 61 through 63, and supplies the selected video signal to the D-A
converters 86. The clock signal switching unit 84 selects one of three
clock signals CLK1, CLK2, and CLK3 output from the three memory control
units 71 through 73, and supplies the selected clock signal to the D-A
converters 86 as a synchronizing signal of digital-to-analog conversion.
The video signal switching unit 82 and the clock signal switching unit 84
are supplied with the multiplexing signal MPX from the memory unit 60.
The D-A converters 86 converts the 24-bit digital video signal RGB0,
wherein 8 bits are allocated to each color of RGB, to analog videos
signals AR, AG, and AB. These analog video signals AR, AG, and AB are
amplified by the amplifies 88 and transmitted to the color monitor 90
while the color monitor 90 receives a vertical synchronizing signal VSYNC
and a horizontal synchronizing signal HSYNC output from the video control
signal generator 80.
FIGS. 2(A) through 2(D) illustrate memory spaces of the four memory units
60 through 63 in terms of dimensions of display screens. The space of each
memory unit is defined by a width or the number of lines Wv in the
vertical direction, a height or the number of pixels Wh in the horizontal
direction, and a depth or the number of bits Nb allocated to each pixel.
As illustrated in FIG. 2(A), the space of the memory unit 60 corresponds
to a display screen of 1,600 pixels.times.1,200 lines and has a depth of 2
bits. Multiplexing data stored in the memory unit 60 are supplied to the
video signal switching unit 82 and the clock signal switching unit 84 as
the multiplexing signal MPX. The depth of the memory unit 60 is set equal
to the number of bits which identifies the maximum number of video memory
units to be mounted on the computer system. The embodiment shown in FIG. 1
has three video memory units, and the memory unit 60 accordingly has the
depth of 2 bits.
The first video memory unit 61 corresponds to a display screen of 1,600
pixels.times.1,200 lines and has a depth of 24 bits as illustrated in FIG.
2(B). The first video memory unit 61 stores full-color natural video data.
The first video memory unit 61 can be realized by three memories having a
depth of 8 bits.
The memory unit 60 and the first video memory unit 61 have identical memory
spaces corresponding to the same display screen. The first memory control
unit 71 (FIG. 1) supplies the read-out signal commonly to the memory unit
60 and the first video memory unit 61, which respectively output the
multiplexing signal MPX and the video signal RGB01 stored at corresponding
positions in the respective memory units.
As shown in FIGS. 2(C) and 2(D), the second video memory unit 62
corresponds to a display screen of 640 pixels.times.400 lines and has a
depth of 24 bits, and the 3-port video memory unit 63 corresponds to a
screen of 800 pixels.times.600 lines and has a depth of 24 bits. The three
video memory units 61 through 63 may correspond to an identical display
screen. The first through the third memory control units 71 through 73
receive the read-permit signals VPIE1-3 and HPIE1-3 supplied from the
video control signal generator 80, and read the video signals RGB01-3 out
of the video memory units 61 through 63 according to the read-permit
signals, respectively.
FIG. 3(A) shows an address map of three operating systems (OS) controlling
the three video memory units 61 through 63, respectively. The three video
memory units 61 through 63 are respectively managed by different operating
systems, that is, multi-OS, OS-1, and OS-2 as shown in FIG. 3(A) The
multi-OS has a function of temporarily switching the system control to
another OS. Each OS has a memory region corresponding to the respective
video memory units 61 through 63. Arrows with numerals 1 through 4 in the
drawing of FIG. 3(A) show the procedure of an OS switching process. When a
user inputs, through a keyboard 40 or a mouse 42, a certain instruction
which requires switching of the system control from the multi-OS to the
OS1, a BIOS (basic input/output system) gives a switching instruction to
the multi-OS (step 1). The multi-OS gives over the system control to the
OS1 in response to the switching instruction (step 2). The OS1 executes a
required processing according to the certain instruction, and switches
back the system control to the multi-OS upon completion of the processing
(step 3). Video images stored in the video memory units 61 through 63 are
then displayed on the color monitor 90 via the BIOS (step 4).
FIG. 3(B) is a plan view illustrating the video images read out of the
video memory units 61 through 63 and displayed on the color monitor 90.
Although the plural operating systems are used in the embodiment, only one
OS may be used to manage a plurality of video memory units. For example,
the three video memory units 61 through 63 may be controlled with only one
OS.
FIG. 4 shows a relation between a screen display on the color monitor 90
and the read-permit signals VPIE1 through VPIE3 and HPIE1 through HPIE3
output from the video control signal generator 80. Symbols W01, W02, and
W03 in FIG. 4 denote three video display areas on the color monitor 90, in
which respective images are displayed according to the three video signals
RGB01-3 read out of the three video memory units 61 through 63.
Waveforms of signals on an X1-X2 line are shown in the lower portion of
FIG. 4: the horizontal synchronizing signal HSYNC, the horizontal
read-permit signals HPIE1-3 supplied from the video control signal
generator 80 to the three memory control units 71 through 73, and a
horizontal component HMPX of the multiplexing signal MPX read out of the
memory unit 60. Waveforms of signals on a Y1-Y2 line are shown in the
right hand side of FIG. 4: the vertical synchronizing signal VSYNC, the
vertical read-permit signals VPIE1-3 supplied from the video control
signal generator 80 to the three memory control units 71 through 73, and a
vertical component VMPX of the multiplexing signal MPM read out of the
memory unit 60.
The horizontal read-permit signal HPIE1 given to the first video memory
unit 61 is kept at a high (H) level in a display range between a left-end
position A and a right-end position F on the color monitor 90. The
vertical read-permit signal VPIE1 is also kept at an H level in the whole
vertical range on the screen. The first video signal RGB01 is thus read
out of the first video memory unit 61 while both the horizontal and the
vertical read-permit signals HPIE1 and VPIE1 are kept at the H level. In
the same manner, the second video signal RGB02 is read out of the second
video memory unit 62 while both the horizontal and the vertical
read-permit signals HPIE2 and VPIE2 are kept at the H level. The third
video signal RGB03 is read out of the third video memory unit 63 while
both the horizontal and the vertical read-permit signals HPIE3 and VPIE3
are kept at the H level.
The video signal switching unit 82 selects and outputs one of the three
video signals RGB01-3 in response to the multiplexing signal MPX supplied
from the memory unit 60. Like the first video signal RGB01, the
multiplexing signal MPX successively shows values of the multiplexing data
for each pixel in each scanning line on the color monitor 90. For the
clarity of illustration, however, the variation in the multiplexing signal
MPX is shown as a variation in the horizontal component HMPX and that in
the vertical component VMPX in FIG. 4. Actually, a series of horizontal
components HMPX arranged in the order of scanning constitute the
multiplexing signal MPX.
When the horizontal component HMPX of the multiplexing signal MPX varies as
1, 2, 3, 1 on the X1-X2 line as shown in FIG. 4, the video signal
switching unit 82 successively selects the video signals RGB01, RGB02,
RGB03, and RGB01 accordingly.
The CPU 50 determines the multiplexing data stored in the memory unit 60
according to the size and position of each video display area specified on
the screen of the color monitor 90. When the user specifies the
dimensions, the positions, and the spatial arrangement of the second and
the third video display areas W02 and W03 through keystrokes on the
keyboard or clicks of the mouse, the CPU 50 generates multiplexing data
based on the specification and writes the multiplexing data into the
memory unit 60. A basic video image, such as a background image, is
displayed in the first video display area W01 which has a fixed size.
Video images of different sizes as shown in FIGS. 2(B), 2(C), and 2(D) are
usually displayed with different synchronizing signals suitable to
respective sizes. Therefore it has been difficult for the conventional
systems to simultaneously display the video images of different sizes
overlapping one another. In the computer system of the embodiment as
illustrated in FIG. 1, the first through the third memory control units
71, 72, and 73 output clock signals CLK1, CLK2, and CLK3, which are
respectively synchronous with the video signals read out of the video
memory units 61 through 63, to the clock signal switching unit 84. The
clock signal switching unit 84 then selects one of the clock signals in
response to the multiplexing signal MPX read out of the memory unit 60,
and supplies the selected clock signal to the D-A converter 86. The D-A
converter 86 executes digital-to-analog conversion according to the clock
signal synchronous with the video signal output from the video signal
switching unit 82. In this manner, the video signals read out of the video
memory units 61 through 63 are successively converted to analog video
signals AR, AG, and AB in response to the clock signals CLK1, CLK2, and
CLK3 respectively synchronous with the video signals. The analog video
signals AR, AG, and AB output from the D-A converter 86 can precisely
reproduce the video images accordingly.
As described above, the computer system of the embodiment displays video
images while the video signal switching unit 82 successively selects one
of the video signals RGB01 through RGB03 read out of the three video
memory units 61 through 63. The computer system allows high-speed display
of a plurality of video images in an overlapping arrangement. The
digital-to-analog conversion in response to the clock signals synchronous
with the video signals allows a plurality of video images having different
sizes to be reproduced precisely.
Since the memory unit 60 and the first video memory unit 61 have the
identical memory spaces corresponding to the screen o | | |
